JPH0645293A - Formation of gate electrode - Google Patents

Abstract

(57) [Summary] [Object] To provide a method for forming a gate electrode which avoids dry etching damage when a gate region of a compound semiconductor Schottky gate field effect transistor is opened. [Structure] A first insulating film 7 and a second insulating film 7 are formed on an operating layer 2 made of a compound semiconductor formed on a semi-insulating compound semiconductor substrate 1.
Of the insulating film 8 are sequentially stacked, and an opening is formed in the second insulating film 8 by anisotropic dry etching using the resist film having an opening in the gate region forming portion as a mask, and then the first insulating film 7 is formed. An opening is formed by etching with low damage or no damage, and the electrode metal layer 6 is formed including the opening.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode, and more particularly to a method of forming a gate electrode of a compound semiconductor Schottky gate field effect transistor.

[0002]

2. Description of the Related Art As one of conventional methods of forming a gate electrode of a Schottky gate field effect transistor (FET) using a compound semiconductor, it is formed on an operating layer made of a compound semiconductor formed on a semi-insulating GaAs substrate. There is known a method of forming an opening corresponding to the gate electrode pattern in the insulating film and forming a metal layer to be a gate electrode in the opening.

4A to 4D are sectional views showing the order of steps for explaining the conventional method of forming a gate electrode.

As shown in FIG. 4A, an insulating film 3 made of silicon dioxide (SiO ₂ ) is formed on a semiconductor substrate 1 on the surface of which an operating layer 2 is formed by an epitaxial growth method or an ion implantation method by a CVD method or the like. And a first photoresist 4 having an opening corresponding to the gate electrode pattern formed thereon.
Is formed by a normal photoresist process.

Then, the insulating film 3 is made to correspond to the gate electrode pattern by anisotropic dry etching using the first photoresist as a mask, for example, anisotropic dry etching using a mixed gas of CHF ₃ and O ₂ . Form an opening. The anisotropic dry etching is used here to obtain the fine gate length of the gate opening pattern with good controllability and reproducibility. Then, by removing the first photoresist 4, the structure shown in FIG. 4B is obtained.

Next, as shown in FIG. 4C, an electrode metal layer 5 to be a gate electrode is formed on the entire surface including the surface of the insulating layer 3 and the operation layer 2 exposed by the opening by a sputter deposition method or a vacuum deposition method. Then, a second photoresist 6 having a gate electrode pattern is formed by a normal photoresist process.

Next, the ion milling method or the reactive ion etching method (RI) using the second photoresist 6 as a mask is used.
The metal layer 5 is etched by E) or the like to form the insulating film 3
Is removed by a wet etching method as shown in FIG.
The electrode shown in (d) is obtained.

[0008]

In the conventional method of forming a gate electrode described above, the operating layer is formed by the ion bombardment of anisotropic dry etching using a mixed gas of CHF ₃ and O ₂ when opening the gate region. There is a problem that carriers are damaged and carriers near the surface are reduced. This decrease in carriers is recovered to some extent by heat treatment at 400 ° C. or higher, but is not completely recovered. The decrease rate depends on the dry etching conditions and overetching time, and it depends on the reproducibility of the dry etching rate and the in-plane distribution of the substrate. , The carrier decrease rate varies, and F
There is a problem that the ET characteristics vary greatly and the yield decreases.

According to the experiments conducted by the inventors, under the conventional conditions, when the gate region is opened by anisotropic dry etching,
SiO ₂ of 30 nm (nanometer) or more on the gate opening surface
When the film was left and the residual film was opened by wet etching, there was no decrease in carriers near the surface. However,
Variation of residual SiO ₂ film thickness within the semiconductor wafer is 60 ± 3
Since the thickness is 0 nm, the SiO ₂ film is 30 nm over the entire surface.
When anisotropic dry etching is performed under the above-mentioned conditions, SiO
₂ There was also a problem that the residual film thickness varied from 30 to 90 nm and the spread and variation of the opening became large when opening by wet etching.

An object of the present invention is to reduce damage at the time of opening a gate region and provide an FET as designed with good in-plane uniformity.

[0011]

A feature of the present invention is that a first insulating film and a second insulating film are sequentially laminated on an operating layer made of a compound semiconductor formed on a semi-insulating compound semiconductor substrate. And a step of forming a resist film in which a gate region forming portion is opened, and using the resist film as a mask, the second insulating film is anisotropically dried by using an etching gas having an etching rate faster than that of the first insulating film. Etching by an etching method to form a first opening, and the second opening
Forming a second opening by etching a portion of the first insulating film below the first opening formed in the insulating film by an etching method different from the anisotropic dry etching method; And a step of forming an electrode metal layer in the gate region including the surface of the operating layer exposed in the opening formed of the first and second openings.

Another feature of the present invention is a step of sequentially laminating a first insulating film, an intermediate layer, and a second insulating film on an operating layer made of a compound semiconductor formed on a semi-insulating compound semiconductor substrate. A step of forming a resist film having an opening in a gate region forming portion and etching the second insulating film by an anisotropic dry etching method using the resist film as a mask to form a first opening; Using the second insulating film as a mask, the portion of the intermediate layer below the first opening is etched by an etching method different from the anisotropic dry etching method to form a second opening, and further below the first opening. First
Forming a third opening in the insulating film portion, and forming an electrode metal layer in the gate region including the surface of the operating layer exposed in the opening formed by the first, second and third openings. And forming a gate electrode including.

Another feature of the present invention is a step of sequentially laminating a first electrode metal layer and an insulating film on an operating layer made of a compound semiconductor formed on a semi-insulating compound semiconductor substrate, and forming a gate region. Forming a resist film having an opening in a portion thereof, and etching the insulating film by an anisotropic dry etching method using the resist film as a mask to form an opening; and the first electrode exposed in the opening. Forming a second electrode metal layer in the gate region including the surface of the metal layer.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be specifically described with reference to the drawings.

FIGS. 1A to 1F are sectional views showing the main steps of forming a gate electrode according to the first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, semi-insulating Ga is used.
On the semiconductor substrate 1 made of As substrate, the Si concentration is about 2 × 10 ¹⁷ cm ⁻³ by the molecular beam epitaxy method (MBE method).
After growing the operating layer 2 made of n-type GaAs to a thickness of 200 nm, the first insulating film 7 made of SiO ₂ is formed by CVD.
Film is formed to a thickness of 50 ± 5 nm, and then a second insulating film 8 made of silicon nitride (Si ₃ N ₄ ) is formed by CVD.
Method to form a film with a thickness of 400 nm, and then 50
The first photoresist 4 having a thickness of 0 nm is spin-coated and dried, and the width W ₁ corresponding to the gate electrode pattern is 0.45 μm and the length (dimension in the direction perpendicular to the paper surface of the drawing) is 100 μm by a normal photoresist process. The opening 12 is formed.

Next, as shown in FIG. 1 (b), CHF _3
Second by anisotropic dry etching by reactive ion etching (RIE) using mixed gas of oxygen and O 2
An opening 13 having a bottom width W ₂ of 0.45 ± 0.01 μm is formed in the insulating film 8. At this time, the etching rate of the first insulating film 7 made of SiO ₂ is 1/10 or less as compared with the second insulating film 8 made of Si ₃ N _4, which is sufficiently slow,
The SiO ₂ film is scarcely etched, and the SiO ₂ film with a film thickness of 50 ± 5 nm remains almost uniformly within the surface of the semiconductor wafer. Therefore, damage to the operating layer under the opening due to RIE can be prevented.

As shown in FIG. 1C, the SiO ₂ film 7 is opened 1 by wet etching with buffered hydrofluoric acid.
4 is formed. Since the etching at this time is isotropic, the opening is slightly expanded and the width W ₃ is about 0.55 μm.
Met. This etching only forms an opening of the SiO ₂ film 7 having a thin film thickness of about 50 ± 5 nm and good in-plane uniformity, and the variation in the opening dimension is as small as ± 10% or less, and there is no problem in FET characteristics.

Next, as shown in FIG. 1 (d), the first photoresist 4 is removed by O ₂ plasma treatment, organic solvent treatment, etc., and then tungsten silicide (WSi) having a thickness of 100 nm and a thickness of 50 nm are formed. An electrode metal layer 5 made of titanium nitride (TiN) and gold (Au) having a film thickness of 200 nm is sequentially formed by sputtering deposition or the like, and is used as a mask for processing the electrode metal layer 5 into a gate electrode pattern by a normal photoresist process. A second photoresist 6 is formed.

After that, the electrode metal layer 5 is etched by the ion milling method using argon (Ar) using the second photoresist 6 as a mask, and the second photoresist 6 is removed by O ₂ plasma treatment, organic solvent treatment and the like. By doing so, the structure of FIG. 1 (e) is obtained.

Further, by removing the first insulating film 7 and the second insulating film 8 by wet etching, FIG.
A desired gate electrode shown in is obtained.

As described above, according to the first embodiment of the present invention, damage to the operating layer 2 due to RIE for making an opening in the second insulating film 8 with high dimensional accuracy is prevented from occurring in the first insulating film. Membrane 7
And the first insulating film 7 is opened by wet etching, so that the operating layer 2 is not damaged.

The threshold voltage of the FET adopting the gate electrode forming method of this embodiment is 420 ± 20 ° C. in the conventional example.
Although it was deviated from the design value by about 1 V even after the annealing in Example 1, in this example, the design value was obtained without annealing, and the uniformity within the substrate and the reproducibility were good.

Next, a second embodiment of the present invention will be described using the same FIGS. 1 (a) to 1 (f).

In the second embodiment, CHF ₃ and O are used as a method for forming an opening in the SiO ₂ film which is the first insulating film 2.
RIE by SF _{6 which} has less ion impact than the mixed gas of ₂ and can perform anisotropic etching than wet etching.
Use the method.

Since the etching at this time is anisotropic etching, the width of the opening W ₃ is small and is about 0.5 μm. After that, the gate electrode having the structure of FIG. 1F is obtained by the same process as in the first embodiment.

The threshold voltage of the FET adopting the gate electrode forming method of this embodiment is 400 ± 20 ° C. in the conventional example.
Although it was deviated from the design value by about 1 V even after annealing, the FET of the present embodiment was obtained as designed, and the uniformity in the substrate,
The reproducibility was also good.

Next, a third embodiment of the present invention will be described. 2A to 2F are sectional views showing the main steps of forming the gate electrode according to the third embodiment of the present invention in the order of steps.

First, as shown in FIG. 2A, semi-insulating Ga is used.
On the semiconductor substrate 1 made of As substrate, the Si concentration is about 2 × 10 ¹⁷ cm ⁻³ by the molecular beam epitaxy method (MBE method).
After the operating layer 2 made of n-type GaAs is grown to a thickness of 200 nm, the first insulating film 7 made of SiO ₂ is formed by CVD.
Was deposited to a thickness of 40 ± 4 nm, such as by law, followed by the intermediate layer 9 made of an aluminum film is formed to a thickness of 20nm by sputtering deposition method or a vacuum evaporation method, a second further composed of SiO ₂ An insulating film 8 is formed to a thickness of 400 nm by a CVD method or the like, and then a photoresist 4 having a thickness of 500 nm is spin-coated and dried, and a width W ₃ corresponding to a gate electrode pattern is 0.4 μm by a normal photoresist process. , The length (dimension in the direction perpendicular to the plane of the drawing) is 1
An opening 15 of 00 μm is formed.

Next, as shown in FIG. 2B, the bottom width W _{4 of} the second insulating film 8 is 0 by anisotropic dry etching by the RIE method using a mixed gas of CHF ₃ and O _2. An opening 16 of 0.4 μm is formed. At this time, the etching rate of the intermediate layer 9 made of aluminum is 1/100 or less that of the second insulating film 8 made of SiO _2, which is sufficiently slow, so that the intermediate layer 9 is hardly etched, and the first insulating film is not etched. Since most of the film thickness 7 of 40 and the film thickness of the intermediate layer 9 of 20 nm remains, it is possible to sufficiently prevent the operating layer 2 in the opening from being damaged by RIE.

Next, as shown in FIG. 2C, the intermediate layer 9
RIE using CCl ₄ gas for the aluminum film
The opening 17 is formed by using the second insulating film 8 as a mask. At this time, the etching rate of the SiO ₂ film that is the first insulating film 7 is 1/100 or less that of the aluminum film that is the intermediate layer 9, which is sufficiently slow, so that the first insulating film 7 is hardly etched. RI of the operating layer 2 below the opening
E Damage can be sufficiently prevented. Then, the first insulating film 7 is wet-etched with buffered hydrofluoric acid to form an opening therein. Since the etching at this time is isotropic etching, the opening up to that point is slightly expanded and its width is about 0.5 μm. This etching has a film thickness of 4
Only the openings were formed in the first embodiment, which was as thin as 0 nm and had good in-plane uniformity, and the variation in the opening dimensions was as small as ± 10% or less, and there was no problem. The second insulating film 8 and the intermediate layer 9 are also etched by this etching, but this has little effect on the opening size.

Next, as shown in FIG. 2D, the first photoresist layer 4 is removed by O ₂ plasma treatment or organic solvent treatment, and then WSi having a thickness of 100 nm and a thickness of 50 nm are formed.
nm of TiN and 200 nm of thickness of Au are sequentially formed by a sputter deposition method or the like, and a second photoresist 6 for processing the electrode metal layer 5 into a gate electrode pattern is formed by a normal photoresist process. To do.

Next, using the second photoresist 6 as a mask, the electrode metal layer 6 is etched by an ion milling method using Ar (argon), and then the second photoresist 6 is treated with O ₂ plasma and an organic solvent. The structure of FIG. 2 (e) is obtained by removing it by processing or the like.

Further, the first insulating film 7, the intermediate layer 9, and the second insulating film 8 are removed by etching with buffered hydrofluoric acid to obtain the gate electrode shown in FIG. 2 (f).

As described above, according to this embodiment,
Damage to the operating layer 2 due to RIE for forming an opening with high dimensional accuracy in the second insulating film 8 is prevented by the intermediate layer 9 and the first insulating film 7 made of aluminum. RIE damage to form the opening is the first
Is prevented by the insulating film 7. Further, the first insulating film 7
Is opened by wet etching, so that the operating layer 2 is not damaged.

Further, in the present embodiment, since the second insulating film 8 and the intermediate layer 9 can be processed by RIE, the opening size can be controlled with high precision, and the adoption of the intermediate layer allows the underlying layer in each etching step to be controlled. Since the etching selectivity ratio between and can be increased, uneven thickness of the lower layer due to non-uniform etching rate in the substrate does not occur, and the uniformity of the opening size within the substrate surface and between the substrates is also good, and locally No part to be damaged.

The gate electrode formed by the conventional method is F
Although the threshold voltage of ET was deviated from the design value by about 1 V even after the heat treatment at 400 ° C., the gate electrode of the present example could obtain the designed value without the heat treatment, and the uniformity and reproducibility within the substrate were obtained. Was also good.

Next, the same FIG. 2 for the fourth embodiment.
A description will be given using (a) to (f).

In this embodiment, the intermediate layer 9 has a film thickness of 20 n.
m alumina (Al ₂ O ₃ ) film is used. The materials and film thicknesses of the other layers are the same as those in the third embodiment.

According to the fourth embodiment, as shown in FIG. 2B, the second insulating film 8 is formed under the same conditions as those of the third embodiment.
Al _{2 of the} intermediate layer 9 when the opening is formed by RIE of
Since the etching rate of O ₃ is 1/100 or less than that of SiO ₂ of the second insulating film 8, Al ₂ O ₃ of the intermediate layer 9 having a film thickness of 20 nm and the first insulating film 7 having a film thickness of 50 nm are used. Of S
The iO ₂ can prevent the operating layer 2 from being damaged by RIE.

Next, Al _{2 of the} intermediate layer 9 shown in FIG.
Wet etching with phosphoric acid is used for opening etching of the O ₃ film. The SiO ₂ of the underlying first insulating film 7 is not etched by phosphoric acid. Next, the first insulating film 7 is wet-etched with buffered hydrofluoric acid. At this time, since Al ₂ O ₃ has high resistance to buffered hydrofluoric acid, etching can be performed using Al ₂ O ₃ as a mask. At this time, since the openings of the intermediate layer 9 and the first insulating film 7 are both wet-etched isotropically, there is no damage to the operating layer 2 and the width of the opening bottom of the first insulating film 7 is about 0. Although it spreads to 55 μm, the thicknesses of the first insulating film 7 and the intermediate layer 9 are as thin as 40 nm and 20 nm, respectively, and the in-plane uniformity is good, so that the dimensional controllability is sufficient.
Enter within 5%.

The same steps as those of the third embodiment will be described below with reference to FIG.
A gate electrode having the structure of (f) is obtained. However, since the intermediate layer 9 is an insulator in this embodiment, it can be used as a gate electrode in the structure of FIG.

As described above, according to the fourth embodiment, damage to the operating layer 2 due to RIE for forming a highly accurate opening in the second insulating film 8 is prevented by the intermediate layer 9 made of Al ₂ O ₃ and the second layer. This is prevented by the first insulating film 7 and the opening etching of the intermediate layer 9 and the first insulating film 7 is wet etching so that no damage occurs.

The gate electrode formed by the conventional method is F
Although the threshold voltage of ET was deviated from the design value by about 1 V even after the heat treatment at 400 ° C., the gate electrode of the present example obtained the same value as the design value even when the heat treatment was not performed, and the uniformity in the substrate, The reproducibility was also good.

Next, a fifth embodiment will be described with reference to FIGS.
Will be explained. 3A to 3D are sectional views showing the main steps of the third invention in the order of steps.

First, as shown in FIG. 3A, semi-insulating Ga is used.
The semiconductor substrate 1 made of As substrate has a thickness of 20 by MBE method.
After the operating layer 2 made of n-type GaAs having a thickness of 0 nm and a Si concentration of 10 ¹⁷ cm ⁻³ is grown, WSi having a film thickness of 50 nm, for example, is sputter-deposited as the first electrode metal layer 10. Next, for example, a SiO ₂ film having a thickness of 500 nm is formed as the insulating film 3 by a CVD method, and then a first photoresist 4 having a gate region opened is formed, and the insulating film 3 is formed by anisotropic dry etching using CF ₄ gas, for example. An opening 18 is formed in the. At this time, if CF ₄ gas is used, SiO ₂ and WSi
Since a high etching selection ratio can be obtained with, the WSi exposed in the opening is hardly etched. What is more important here is that if the WSi film has a thickness of about 30 nm or more, it is possible to completely shield irradiation ions during dry etching, and prevent damage to the operating layer 2 due to dry etching. You can

Next, as shown in FIG. 3B, after removing the first photoresist layer 5, for example, a T film having a film thickness of 50 nm is formed.
The second electrode metal layer 1 made of i and Au having a thickness of 400 nm
1 is sequentially formed by a sputter deposition method, a vacuum deposition method, or the like, and subsequently, a second photoresist 6 for processing the second electrode metal layer 11 into a gate electrode pattern is formed.

Next, as shown in FIG. 3C, the second electrode metal layer 11 is etched by the ion milling method using the second photoresist 6 as a mask to remove the second photoresist 6, and then the second photoresist 6 is removed. The insulating film 3 is removed by, for example, a wet etching method using buffered hydrofluoric acid, and then the WSi except for the gate region is removed by an isotropic dry etching method using, for example, SF ₆ gas to form a gate electrode. obtain.

In this case, since the WSi film thickness is as thin as 50 nm and the in-plane uniformity is good, the side etching amount is small even if the isotropic etching is used, and the controllability of the gate length is not deteriorated. Further, in this embodiment, since the openings of the insulating film 3 are all formed by the anisotropic dry etching method, the spread of the opening width is suppressed, and the electrodes are formed by the side etching in the isotropic dry etching of the first electrode metal layer. Since the width is slightly narrowed, it is suitable for forming a fine gate.

The gate electrode formed by the conventional method is F
The threshold voltage of ET was deviated from the designed value by about 1 V even after the heat treatment at 400 ° C., but the gate electrode of this example obtained the designed value even without the heat treatment, and the uniformity in the substrate and the reproduction were obtained. The property was also good.

[0051]

As described above, according to the present invention, the first insulating film or the intermediate layer having a function as an etching stopper layer is introduced at the time of opening the insulating film in the gate region by anisotropic dry etching. Damage to the operating layer can be reduced. In addition, since it functions as an etching stopper layer, variations in the film thickness of these layers within the substrate are small, and there is an effect that variations in the opening dimensions when these layers are opened by isotropic etching can be reduced.

Therefore, by adopting the method of forming a gate electrode of the present invention, it is possible to obtain an FET having a design value without variations in FET characteristics with good in-plane uniformity and reproducibility.

[Brief description of drawings]

FIG. 1 is a sectional view in a main process of first and second embodiments of the present invention.

FIG. 2 is a sectional view in the main process of the third and fourth embodiments of the present invention.

FIG. 3 is a sectional view in a main step of a fifth embodiment of the present invention.

FIG. 4 is a cross-sectional view in the main steps of the conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Operation layer 3 Insulating film 4 First photoresist 5 Electrode metal layer 6 Second photoresist 7 First insulating film 8 Second insulating film 9 Intermediate layer 10 First electrode metal layer 11 Second electrode Metal layer 12-18 Opening

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Mikio Kanamori 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation

Claims (3)

[Claims] 1. A step of sequentially laminating a first insulating film and a second insulating film on an operating layer made of a compound semiconductor formed on a semi-insulating compound semiconductor substrate, and a gate region forming portion is opened. Forming a resist film, and using the resist film as a mask, the second insulating film is etched by an anisotropic dry etching method using an etching gas having an etching rate faster than that of the first insulating film to form a first opening. And a step of etching the portion of the first insulating film below the first opening formed in the second insulating film by an etching method different from the anisotropic dry etching method. Gate electrode, and a step of forming an electrode metal layer in the gate region including the surface of the operating layer exposed in the opening formed of the first and second openings. of Forming method. 2. A step of sequentially stacking a first insulating film, an intermediate layer, and a second insulating film on an operation layer made of a compound semiconductor formed on a semi-insulating compound semiconductor substrate, and a gate region forming portion. Forming a first opening by forming a resist film having an opening formed therein and using the resist film as a mask to etch the second insulating film by an anisotropic dry etching method; As a mask, the portion of the intermediate layer under the first opening is etched by an etching method different from the anisotropic dry etching method to form a second opening, and further the first insulating film under the first opening is formed. Forming a third opening in the portion, and the first, second and third
And forming an electrode metal layer in the gate region including the surface of the operating layer exposed in the opening of the gate electrode. 3. A step of sequentially laminating a first electrode metal layer and an insulating film on an operating layer made of a compound semiconductor formed on a semi-insulating compound semiconductor substrate, and a resist having a gate region forming portion opened. Forming a film, etching the insulating film by an anisotropic dry etching method using the resist film as a mask to form an opening, and a gate including the surface of the first electrode metal layer exposed in the opening A step of forming a second electrode metal layer in the region, the method of forming a gate electrode.