JPH01107577A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To suppress the decrease in drain current and to obtain a field effect transistor having excellent characteristics, by using a metal film, which is provided on a semiconductor active layer as an etching stopper. CONSTITUTION:An N-type GaAs active layer 2 is provided on a semi-insulating GaAs substrate 1. An aluminum film 3 is deposited on the active layer 2 to a thickness of 0.1mum. A silicon oxide film 4 is deposited on the aluminum film 3 to a thickness of 0.5mum. Then, the silicon oxide film 4 undergoes selective anisotropic dry etching under the conditions of pressure of 8X10<-2>Torr and electric power of 0.9W by using CF4 gas. Thus, the side wall part of the silicon oxide film 4, which is vertical to the surface of the active layer 2 is provided. Then a tungsten silicide film 5 is deposited on the surface including the side wall part to a thickness of 0.5mum. Then, anisotropic etching is performed under the conditions of pressure of 2X10<-1>Torr and electric power of 0.25W by using CF4 gas. The tungsten silicide film 5 is made to remain only at the side wall part. The tungsten silicide film 5 at the other part is removed. Thus the deterioration of the characteristics of the TFT is suppressed. The field effect transistor having a minute gate electrode 6 and the excellent characteristics can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor.The present invention relates to a method for manufacturing a medium-barrier gate type field effect transistor.

[Conventional technology]

In order to improve the characteristics of a field effect transistor, it is most effective to shorten the gate length of K. As a means of forming a field effect transistor having a fine gate electrode with a gate length of 1 μm or less, there is a method of using a metal film that is left on the side wall of the insulating film by anisotropic drying or etching.

FIGS. 2(a) to 2(d) are cross-sectional views of semiconductor chips shown in order of steps for explaining a conventional method of manufacturing a field effect transistor.

As shown in Fig. 2 (a) K, semi-insulating G a A s
On the active layer 2 formed on the substrate l, a silicon oxide film 4 is deposited by chemical vapor deposition (hereinafter referred to as CVD) Ic.

Next, as shown in FIG. 2(b) Ic, a side wall portion straight to the surface of the active layer 2 is selectively etched by reactive ion etching (hereinafter referred to as IE) using CF4 gas. , and a tungsten silicide layer 5 is formed on the table IT1 including the side wall portion x! Multiply by i.

Next, as shown in Fig. M2 [c) K, the entire surface of the IEK layer was anisotropically etched using cp gas, and only the side wall portion was etched with tungsten oxide. A gate electrode 6 is formed by removing the tungsten silicide Nn 5 from other parts except for the tungsten silicide Nn 5.

Next, as shown in FIG. 2(d), only the % silicon oxide film 4 is etched and removed, and the electrodes near both sides of the gate electrode 60 are removed.
A source electrode 7 and a drain electrode 8/ having ohmic contacts are selectively formed on the e-layer 2 to form a GaAs-type field effect transistor (hereinafter MES).
[Problems to be Solved by the Invention] In the case of field effect transistors, especially MES FETs, the characteristics of the interface between the gate electrode and the semiconductor active layer are important; If the surface of the semiconductor active layer under the gate electrode is damaged, good FET characteristics cannot be obtained.

In the conventional method for manufacturing field effect transistors described above, the surface of the semiconductor active layer under the gate electrode is damaged by etching when forming the sidewalls of the insulating film, and the four channels of the channel are damaged.
The purpose of the present invention is to suppress the deterioration of FET characteristics due to such etching damage,
An object of the present invention is to provide a method for manufacturing a field effect transistor having a fine gate electrode and having good characteristics.

[Means for Solving the Problems] The method for manufacturing a field effect transistor of the present invention includes forming a metal film on an active layer provided on a semi-insulating semiconductor substrate, and forming an insulating film on the metal film. a step of selectively removing the insulating film (by an anisotropic drying or etching method) to form a sidewall portion of the insulating film; and depositing a conductive film on the surface including the sidewall portion and anisotropically removing the insulating film. a step of removing the conductive film in other parts while leaving only the conductive film on the side wall portion by a conductive etching method; a step of etching to form a gate electrode having a two-layer structure of the gold II4 film and the conductive film; and a step of selectively forming a source electrode and a drain electrode on the active layer near both sides of the gate electrode. It consists of:

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1(t3) to 1(d) are cross-sectional views of semiconductor chips shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in Figure 1 (al) 5, an n-type GaAs active layer 2 is provided on a semi-absolute GaAJ substrate l, and an aluminum film 3 is deposited to a thickness of 0.1 μm on the active layer 2. , a silicide film with a thickness of 0.5 μm is deposited on the aluminum film 3. Next, using CF4 gas at a pressure of 8×10
The silicon oxide film 4 is selectively anisotropically etched and etched under the condition of Torr1 power of 0.9 W to provide a sidewall portion of the silicon oxide film 4 perpendicular to the surface of the active layer 20.

Next, as shown in FIG. 1 (tb), tungsten silicide l[5 is deposited to a thickness of 0.5 μm on the surface including the side wall portion.

Next, as shown in FIG. 1 [c) K, anisotropic dry etching was performed using CF gas under the conditions of a pressure of 2×10 Torr and a power of 0.25 W, leaving the tungsten silicide film 5 only on the side wall portion. Tungsten silicide film 5 in other parts
remove.

Next, as shown in FIG. 1(d)K, the silicon oxide film 4 is etched and removed using hydrofluoric acid. Next, using the tungsten silicide film 5 as a mask, the sialuminium oxide [3] is removed by etching using phosphoric acid, and a gate electrode 6 having a two-layer structure of the aluminum film 3 and the tungsten silicide film 50 is formed.

Next, a source electrode 7 is formed by sequentially depositing an AuGe alloy with a thickness of gO, 1jjm and Ni with a thickness of 0.034m by vapor deposition on the active layer 2 near both sides of the gate electrode 6 by the lJ7 off method. and selectively forming a drain electrode 8, 4
A Siohmic contact is formed by alloying treatment in a hydrogen atmosphere at 20° C. to construct a GaAsMES FET.

Here, the aluminum film 3 is formed by forming the sidewall part of the silicon oxide film 4 perpendicular to the active layer 2 by anisotropic drying and ticking.
It has the role of absorbing damage so that the damage caused by the CF4 gas does not directly reach the surface of the active layer 20, which is the lower p-interface of the gate electrode 6, and at the same time serves as the lower layer of the gate electrode 6. Therefore, the properties of the material of this damage absorbing layer include that it is resistant to dry etching using CF4 gas to etch the silicon oxide film 4, and is resistant to ticks and etching liquid that does not dissolve the silicon oxide film 4. The material must be easily removable, and aluminum is a suitable material for this purpose. Furthermore, silicon nitride may be used as a substitute for silicon oxide.

〔Effect of the invention〕

As explained above, the present invention provides a method for forming a metal film on the surface of a semiconductor active layer when forming an insulating film side wall part using an anisotropic dryer and a tick to form a fine gate electrode with a gate length of 1 μm or less. By etching and removing the active layer, the surface of the active layer is prevented from being damaged by dry etching and ticks, and the decrease in drain current due to L-ray lysis, FETt# trits, or a decrease in the activation rate of the channel is suppressed. This has the effect that a field effect transistor with good characteristics can be manufactured.

[Brief explanation of the drawing]

1(a) to td) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a field effect transistor. 1...Semi-insulating GaAs substrate, 2...
...Active layer, 3...--1 Luminic membrane, 4...
. . . Silicon oxide film, 5 . . . Tungsten silicide film, 6--- Gate electrode, 7 . Agent Patent Attorney Susumu Uchihara 7 Trap v5 No Enko Yu 2 Diagram

Claims (1)

[Claims] A step of forming a metal film on an active layer provided on a semi-insulating semiconductor substrate and forming an insulating film on the metal film, and selectively removing the insulating film by an anisotropic dry etching method. A step of providing a side wall portion of the insulating film, depositing a conductive film on the surface including the side wall portion, and using an anisotropic etching method to leave only the conductive film on the side wall portion and removing the conductive film on other portions. a step of removing the insulating film and then etching the metal film using the conductive film as a mask to form a gate electrode having a two-layer structure of the metal film and the conductive film; A method for manufacturing a field effect transistor, comprising the step of selectively forming a source electrode and a drain electrode on the active layer near both sides.