JPH0646874B2 - Digital speed controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase controller for controlling the rotation speed of a controlled object.

Configuration of Conventional Example and Its Problems FIG. 1 shows a conventional example of a digital type speed control device.
Is a controlled body (a motor or a rotating body driven by a motor), 2 is a frequency generator (hereinafter referred to as FG), 3 is a digital speed comparing means, 4 is a digital filter, and 5 is a driving means.

The rotational speed of the controlled object 1, that is, the rotational speed, is detected by the _{FG 2} as a signal (FG signal) S _FG having a frequency proportional to the speed. FG signal S _FG is input to a digital speed comparing means 3, digitally discriminating the frequency by the clock pulse CK ₁ (speed comparison) to detect the digital velocity error information D ₁ to. The speed error information D ₁ is digitally processed by the digital filter 4 and led to the driving means 5, and the driving means 5 controls the rotational speed of the controlled object 1 to realize a digital speed control device. .

First, the operation of the speed comparison means 3 will be described with reference to the waveform chart illustrated in FIG.

The speed comparison means 3 has an FG signal S _FG and a clock pulse CK.
Input ₁ and latch pulse S that precedes in timing
Create _LA and the following preset pulse S _PR . Normally, the speed comparison means 3 is composed of an M-bit binary counter, and the speed error information D ₁ is obtained from the lower N bits. That is, the trapezoidal wave S _TZ is created by the preset pulse S _PR and is latched by the latch pulse S _LA to obtain the speed error information D ₁ . The trapezoidal wave S _TZ is an analog representation of the digital operation of the speed comparison means 3. T _i is the reference period for speed comparison, and T _FG is the period of the FG signal S _FG .

A is T _FG > T _i and the rotation speed is slower than the reference speed, B is T
_{When FG} = Ti, they are equal, and C is a fast state. In state A, the trapezoidal wave S _{TZ has} the minimum value (“L” level), in state B the central value (the center of the slope), and in state C the maximum value. (“H” level) is latched (sampled), and acceleration is performed in state A, deceleration is performed in state C, and stable in state B.

Next, an example of the digital filter 4 will be described. The digital filter shown in FIG. 1 is a U / F which has frequency dividing means and an up / down counter (U / D counter) as basic constituent elements.
Although it is a D counter type digital filter, it may be a cumulative addition type digital filter having addition means and storage means as basic constituent elements.

The components of the digital filter 4 are frequency dividing means 4 _A , U /
The D counter 4 _C is the main, and in addition, the magnitude discriminating means 4 _B , the multiplying means 4 _D , and the adding means 4 _E can be used according to the purpose. The frequency dividing means 4 _A receives the output D ₁ of the speed comparing means 3 as an input, and the absolute value of the difference from the reference digital signal D ₀ | D ₁ -D ₀ |
The clock pulse CK ₂ is divided into a frequency proportional to, and the divided output S ₁ is used as the clock input of the U / D counter 4 _C.
The output D ₁ of the speed comparison means and the reference digital signal D ₀ are input to the size determination means 4 _B to determine the magnitude, and the determination output S ₂
Is referred to as up-down switching input of the U / D counter 4 _C.
As a result, the output D ₁ of the U / D counter 4 _C is the reference value D.
Whether it is larger or smaller than ₀ , up or down is switched, and a clock proportional to the absolute value of the difference | D ₁ -D ₀ | is counted. This operation is the integration of D ₁ with reference to D ₀ , and the integrated output D ₂ is obtained from the U / D counter 4 _C.
If the reference value D ₀ is set to a specific value, the magnitude discriminating means 4
_B can be eliminated. For example, by setting the reference value _{D 0} at the center value 100 ...... 0 output _{D 1} (or 011 ...... 1), can be used most significant bit of the output _{D 1} as the level decision signal. The multiplying means 4 _D and the adding means 4 _E are for adding proportional elements. That is, the multiplication unit ₄ at the _D multiplied by (real number including 1) the coefficient K to the output _{D 1,} integrated output in the adding means _{4 E D 2} and the multiplication output _{D 3}
And are added. However, the addition output D ₄ becomes a proportional integration output. Here, when D ₂ has the opposite polarity to D ₁ , D _{3 is set} to D
_It is necessary to set the polarity opposite to ₁ or to use the addition means 4 _E as a subtraction means.

As is apparent from the above description, when the digital filter 4 is used as an integrating circuit, only the integral output D ₂ is obtained and is guided to the driving means 5. When it is used as the proportional integrating circuit, the proportional integral output D ₄ is obtained. It may be configured so as to lead to the driving means 5.

By the way, the outputs D ₂ and D ₄ when the U / D counter type digital filter is used are not necessarily specified, and the speed pull-in of the controlled object 1 (transition from a low speed or high speed state to a steady state) is smooth and speedy. Not done This is due to the initial state of the U / D counter _{4 C.} For example, when the output D ₁ has the minimum value (all bits “0”) in the activated state and the output D ₂ has the minimum value or a value in the vicinity thereof, the controlled object 1 can be smoothly activated. However, the output D ₂
If the value exceeds a certain value and is within the maximum value (all bits “1”), smooth startup cannot be performed. In this case, the U / D counter 4 _C is activated with the down count. Further, the speed of the controlled object 1 is activated and the speed comparison means 3
Output D within the comparison range of (inclination period of trapezoidal wave S _TZ )
₁ changes from the minimum value to the intermediate value, but at this time the output D
_{Since 2} is near the minimum value, it is not possible to immediately shift to the steady state, and here again, it is necessary to wait for the U / D counter 4 _C to count up. Then, after repeating up and down several times, it shifts to a steady state. This operation is the same not only at the time of startup but also when shifting from a low speed or a high speed to a steady state by speed switching or the like. As described above, simply using the digital filter requires a lot of time for pulling in the speed at the time of start-up or speed switching. This problem occurs not only in the U / D counter type digital filter but also in the case of the cumulative addition type digital filter due to the storage means.

An object of the present invention is to solve the above-mentioned problems of the conventional example, and it is an object of the present invention to provide a digital speed control device in which the speed pull-in time is shortened at the time of startup or speed switching. .

According to the present invention, a digital filter constituting a digital type speed control device is controlled according to a speed comparison state of a speed comparison means to shorten a speed pull-in time at the time of starting or speed switching. Is.

Description of Embodiments The configuration and operation of the present invention will be described below with reference to embodiments.

FIG. 3 is an electrical block diagram of a digital speed control device showing an embodiment of the present invention.

In FIG. 3, 6 is a state detecting means for detecting the state of speed comparison of the speed comparing means 3, and the detection output S ₃ of this state detecting means 6 controls the U / D counter 4 _C. The point is the difference from the conventional example of FIG. The points of the present invention will be described below.

Normally, the speed comparison means 3 operates as shown in FIG. 2 and forms and uses the signals S _NH and S _NL shown in FIG. 4 to form the trapezoidal wave S _TZ . This is the M forming the speed comparison means 3.
It is a signal necessary for taking out the lower N bits output from the bit binary counter only for one cycle before the end of counting. S
_NH is the “H” level period of the trapezoidal wave S _TZ (1st state)
S _NL is a signal for setting "L" level period C (third state), and S _NL is a signal for setting the speed comparison period b (second state) in which a speed comparison error can be detected by these two signals. ) Is set.

FIG. 5 shows an example of a concrete circuit of the state detecting means 6, which produces a signal S ₃ for controlling the U / D counter 4 _C from the outputs S _NH , S _{NL of the} speed comparing means 3. FIG. 6 shows the operation waveforms of FIG. 5, where A is the operation at the time of starting (acceleration) and B is the operation at the time of deceleration.

In FIG. 5, 7 is a first shift register, 8 is a second shift register, 7 _A , 7 _B , 8 _A and 8 _B are D flip-flops (DFF), 7 _C is a 2-input NAND gate ( 2 NAN
D), 8 _C and 8 _D are 2-input NOR gates (2 NOR). Signals S _NH and S _NL are respectively D of the first shift register 7.
D inputs of FF7 _A and 7 _B , and latch by latch pulse S _LA . The Q output of DFF7 _A is output as signal SH (H), and D
Q output of FF7 _B is NAND with signal S _NL at 2 NAND7 _C
Take D and output as signal RE (L). Then the signals SE (H), R
E (L) is the D input of DFF8 _A , 8 _B of the second shift register 8 and is latched by the latch pulse S _LA or the preset pulse S _PR . 2NOR 8 _C takes the NOR of the O output of DFF 8 _A and the signal SE (H), outputs the signal RE (H), and outputs 2NOR
At 8 _D, the O output of DFF8 _B and the signal RE (L) are NORed and the signal SE (L) is output. These four types of signals SE (H), R
E (L), RE (H) and SE (L) are the detection output S ₃ of the state detecting means 6 and are used for controlling the U / D counter 4 _C as required.

It should be noted that DFF7 _B and 2NAND7 _C of the first shift register 7
Is a start command function of the normal speed comparison means 3,
It is not always necessary to newly provide the state detecting means 6.

FIG. 7 is a specific circuit example showing a configuration for controlling the U / D counter 4 _C. A shows a configuration in which control is performed only when transitioning from startup (acceleration) to a steady state, and B shows a configuration in which control is performed when transitioning from startup (acceleration) and deceleration to a steady state.

In FIG. 7A, all the flip-flops FF1 to FF8 forming the U / D counter 4 _C are reset input terminals R
In addition, only the FF8 of the most significant bit is also provided with the set input terminal S. The signal SE (L) is input to the reset input R, and the signal SE (L) is input to the set input S. By doing so, all bits of the U / D counter 4 _C are reset by the signal RE (L) and the output D is output during the acceleration period C at startup.
₂ can be controlled to the minimum value (all bits “0”),
The same start command as the output D ₁ of the speed comparison means 3 can be issued. When the speed comparison period B is entered, the reset operation is canceled and the signal SE (L) causes the highest FF8.
Only for a moment, the output D ₂ is controlled to the center value. If the U / D counter _4C is controlled as described above, the acceleration command (minimum value) is continuously issued during the acceleration period C at startup, and when the speed comparison period B is entered, the output D ₂ is the value closest to the immediate steady state ( The central value) can be controlled, and smooth and speedy speed pull-in is possible.

FIG. 7B shows that the same operation is performed when the rotational speed of the controlled object 1 is switched from the high speed to the low speed and the speed comparison period B is entered via the deceleration period a. In this case, flip-flops each having a reset input terminal R and a set input terminal S are used for FF1 to FF8,
2OR9 that takes the OR of signals RE (L) and RE (H), signal SE (L)
It is composed of 2OR10 that takes the OR of SE and SE (H). In addition,
The control operation by the signals RE (L) and SE (L) is the same as that in FIG. Since the output D ₁ of the speed comparison means 3 has the maximum value (all bits “1”) during the deceleration period a, all bits of FF1 to FF8 are set by the signal SE (H) and controlled to the maximum value. . Further, when the speed comparison period B is entered, all the lower bits FF1 to FF7 except the most significant bit FF8 are momentarily reset by the signal RE (H) and controlled to the central value. By doing so, the transition from deceleration to the steady state can be performed smoothly and speedily, and the speed pull-in can be shortened.

In the above-described embodiment of the present invention, it cannot be denied that the configurations of the state detecting means 6 and the U / D counter 4 _C are slightly complicated.

Figure 8 shows another embodiment of the present invention, it is an emphasis is on the simplification of the state detecting means 6 and the U / D counter 4 _C. The difference from the embodiment of the present invention in FIG. 5 is that the output gate means 11 is provided at the output part of the U / D counter 4 _C , and the output D ′ ₂ of the output gate means 11 is input to the adder means 4 _E. And The output gate means 11 controls the output S ₃ of the state detection means 6 in the same manner as the U / D counter 4 _C. Further, the output gate means 11 may be configured to gate and output the output D ₄ of the adding means 4 _E.

FIG. 9 shows a concrete circuit example of the U / D counter 4 _C and the output gate means 11.

9A and 9B correspond to FIGS. 7A and 7B, respectively,
U / D counter ₄ comprises a set input terminal S only the most significant bits FF8 to form a _C, other lower bits FF1~FF
7 has only a reset input terminal. Inverter 12 in FIG. 9 A is intended to invert the signal RE (L), the input of 2AND11 _A in the output gate means 11 to control the output of FF8. The outputs of the lower bits FF1 to FF8 are passed through the output gate means 11 without a gate. In such a configuration, in the acceleration period C at startup, the signal RE (L) controls the U / D counter 4 _C to the center value and the FF 8
Output is prohibited and the output D' ₂ of the output gate means 11 is controlled to the minimum value (all bits "0"). When the speed comparison period B is entered, this control operation is released and the output D' ₂
Is D ₂ .

Further, 2OR13 in FIG. 9B is an O of the signals SE (H) and RE (L).
It is a gate that takes R, and a lower bit of the output gate means 11 is provided with a 2OR gate of 11 _{B to} 11 _H , and a signal SE
(H) controls the outputs of the lower bits FF1 to FF7. In the arrangement according, by the reduction period b in the signal SE (H) prohibits output of the lower bits FF1~FF7 controls the central value of the U / D counter 4 _C, the output D of the output gate means 11 _'2 Is controlled to the maximum value (all bits “1”). (Note, 2AND11 _A is open.) Then, to release the control by the signal Once in the speed comparison period b SE (H), the output D _'2 is made to be D _2.

With the configuration of FIGS. 9A and 9B described above, the second shift register of the state detecting means 6 shown in FIG. 5 can be dispensed with,
Simplification can be achieved together with the U / D counter 4 _C.

The above description is only one operation example, and it goes without saying that various configurations are possible without departing from the concept of the present invention. Further, the present invention is not limited to the digital type speed control device using the digital filter having the frequency dividing means and the U / D counter as its basic constituent elements, and can be applied to the case of using a known cumulative addition type digital filter. . Generally, a cumulative addition type digital filter has an addition means 14 and a storage means 15 as basic constituent elements as shown in FIG. 10, an output D ₁ of a speed comparison means 3 which is an input digital signal is one input of the addition means 14, and an addition means The output D ₂ of 14 is stored in the storage means 15 by the detection timing signal (for example, latch pulse S _LA ) of the speed comparison means, and the output of the storage means 15 is used as the other input of the addition means 14. When a proportional element is added to this integral element, a multiplication means 16 and a second addition means 17 are added. Also in the case of the digital filter shown in FIG. 10, the object of the present invention can be achieved by controlling the storage means 15 by the output S ₃ of the state detection means 6,
As in the case of FIG. 8, it is possible to use any of the output gate means 18, 19, 20 (shown by broken lines) to control the output S ₃ of the state detecting means 6.

Advantageous Effects of Invention The present invention provides a speed comparison in a digital speed controller using a frequency dividing means, a digital filter or an adding means having a U / D counter as a basic constituent element, and a digital filter having a storing means as a basic constituent element. Since the operation state of the means is detected and the U / D counter or the storage means is controlled by the detected output, the speed pull-in at the time of starting can be performed smoothly and speedily, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is an electrical block diagram showing a conventional example of a digital type speed control device, FIG. 2 is an operation waveform diagram of a speed comparing means, and FIG. 3 is an electric diagram showing an embodiment of a digital type speed control device of the present invention. 4 is an operational waveform diagram of the speed comparison means, FIG. 5 is a concrete circuit diagram of the state detection means in one embodiment of the present invention, FIG. 6 is an operation waveform chart of FIG. 5, and FIG. Is a concrete circuit diagram showing a control method of the up / down counter, FIG. 8 is an electrical block diagram showing another embodiment of the digital speed control device of the present invention, and FIG. 9 is a control method of the up / down counter and output gate means. FIG. 10 is an electrical block diagram for explaining an example of application of the cumulative addition digital filter to the present invention, showing a specific circuit configuration of FIG. 3 ... Speed comparison means, 4 ... Digital filter, 4 _A
...... Dividing means, 4 _B ...... Size discriminating means, 4 _C ...... Up-down counter, 4 _D ...... Multiplying means, 4 _E ...... Adding means, 5 ...... Driving means, 6 ...... State detecting means, 11 ...... Output gate means, 14, 17 …… Adding means, 15 …… Storage means, 16 …… Multiplying means, 18, 19, 20 …… Output gate means.

Claims (1)

[Claims] 1. A speed comparison means for detecting speed error information as a digital quantity by discriminating a rotation frequency signal detected from a controlled object, a digital filter for filtering an output of the speed comparison means, and the digital filter. Drive means for controlling the rotation speed of the controlled body according to the output of the control means, a first state in which the rotation speed of the controlled body is high and is outside the comparison area of the speed comparison means, and rotation of the controlled body. The second state in which the speed is within the comparison area of the speed comparison means and the third state in which the rotational speed of the controlled object is low and is outside the comparison area of the speed comparison means are detected, and the first state is detected. In the state, the digital filter is controlled so that the output has the maximum value (or the minimum value), and in the third state, the output of the digital filter has the minimum value (or the minimum value). Daine)
And a state detecting means for initializing the digital filter so that the output becomes the center value immediately after entering the second state.