JPH0412797Y2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field This invention relates to a speed and phase control circuit for a rotating body suitable for application to a drum servo circuit or a capstan servo circuit of a VTR.

Background Art and Problems Drum servo circuits and capstan servo circuits are provided with servo loops that match the rotational speed and rotational phase of the motors that drive each with reference speeds and reference phases. In this case, hold the phase servo loop at a certain value until the speed servo loop stabilizes, then activate the phase servo loop after the speed servo loop stabilizes.
I'm trying to apply phase servo.

The value of the phase control signal to be held is set to the lower limit value or upper limit value of the dynamic range of the phase servo system. On the other hand, the phase lock point in a phase servo circuit is set near the center of the circuit's dynamic range, so
When starting phase servo, it is always necessary to pull in from the very end, which has the drawback that it takes a long time to lock the phase.

Therefore, in such a case, it is preferable to set the value of the phase control signal to be held at an intermediate value of the dynamic range. It may be necessary to provide a separate circuit to obtain the phase control signal,
Furthermore, it is necessary to provide a peripheral circuit for switching and controlling this circuit, which complicates the circuit configuration, and there is no benefit in putting it into practical use.

Purpose of the invention Therefore, in this invention, a predetermined phase control signal to be held can be obtained without complicating the circuit configuration, thereby shortening the phase lock time.

Summary of the invention Therefore, in this invention, part of the speed and phase control system of the rotating body is constructed digitally, and a means for forming a phase control signal based on the output of a counter controlled by the phase signal of the rotating body is used. , an intermediate value setting means for the phase control signal is associated with the intermediate value setting means, and the intermediate value setting means is operated until the speed of the rotating body is controlled within a predetermined speed range.

Embodiment Next, an example of this invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of a speed and phase control circuit 10, in which 10A is a speed servo system, 10A is a speed servo system, and 10A is a speed servo system.
B indicates a phase servo system. A drum is exemplified as a rotating body to be controlled. The drum motor 1 is provided with a frequency generator FG and a rotational phase generator PG.
A speed signal (rectangular wave signal) proportional to the rotational speed of the drum motor 1 and a rotational phase signal (pulse signal) related to the rotational phase are obtained, respectively.

In the speed servo system 10A, 2 is a counter for measuring rotational speed, 3 is a latch circuit for counter output, and the set pulse P _SS of the counter 2 is formed based on, for example, the rising edge of the speed signal. Rope pulse) _PLS is formed based on the falling edge of the speed signal. Therefore, a counter output proportional to the rotational speed of the drum motor 1 is latched, and this is converted into a predetermined analog speed control signal by the DA converter 4, which is supplied to the drum motor 1 via the drive amplifier 5. .

If the rotational speed of the drum motor 1 deviates significantly from the reference speed, the output of the counter 2 will overflow.

When an overflow occurs, the counter output immediately before overflow must be held at that value. For this purpose, the counter 2 is provided with an overflow detection and control circuit 6.

Similarly, the phase servo system 10B is provided with a counter 7 and a latch circuit 8 for measuring the rotational phase, and the counter 7 is set with a rotational phase reference signal P _SP (a pulse signal having the same period as the rotational phase signal), The counter output is latched by a latch pulse _PLP based on the signal. The latch output proportional to the rotational phase difference is output as an analog phase control signal in the D-A converter 9.
It is converted into S _P and supplied to the drum motor 1 together with the speed control signal S _S , and control is performed such that the rotational phase is locked to the reference phase. Reference numeral 11 indicates an adder circuit for adding both signals.

Now, the above-mentioned counter 8 and the D-A converter 9 constitute a phase control signal forming means 12, and in this invention, an intermediate value setting means 15 for the phase control signal _SP is connected to the phase control signal forming means 12. will be provided. In this example, as the intermediate value setting means 15, a setting circuit is used which forcibly sets the latch data of the latch circuit 8 to the intermediate value data of the maximum latch data.

FIG. 2 shows an example of the latch circuit 8 and the set circuit 15 which is intermediate value setting means.

The figure shows an example of a circuit that latches an N+1 bit counter output.
a to 17n are provided, and gate circuits 16a to 16
n consists of a pair of NANDs 18 and 19, each of which is supplied with a latch pulse _PLP and data gated thereby (N+1 bit data).

The flip-flops 17a to 17n, except for the flip-flop 17n corresponding to the most significant bit MSB, are composed of 3-input NANDs, and therefore receive set pulses in addition to the outputs of the gate circuits 16a to 16n-1.
_PS and reset pulse _PR are supplied. The set pulse P _S is a pulse for setting the output to "1", and the reset pulse P _R is a pulse for setting the output to "0". These pulses P _S ,
P _R is a control pulse for making the output of the counter 7 analogized into a waveform (ramp waveform) used for rotational phase control, as will be described later.

The set circuit 15 is associated with a flip-flop 17n corresponding to the most significant bit, which is comprised of an inverter 21 and a NAND 22 as shown, and the inverter 21 is supplied with the pulse P _C shown in FIG. 3C.

The pulse P _C is a pulse indicating whether or not the rotational speed is within the speed lock range, and in this example, the output of a decoder provided in the control circuit 6 is used. In other words, the speed pulse P _U (Fig. 3 A) obtained when the rotation speed is much faster than the locking range, and the speed pulse obtained when the rotation speed is much slower than the lock range.
It is formed from P _D (B in the same figure). Therefore, by passing both pulses P _D and P _U through the OR gate 25, a pulse P _C related to the rotational speed can be obtained. In this pulse P _C , section T _N indicates a section outside the lock range, and T _L indicates a lock range section.

The NAND outputs of the phase-inverted pulse _C (FIG. 3D) and reset pulse P _R (FIG. 3F) are supplied to one NAND 23 constituting the flip-flop 17n, and the pulse _C is supplied to the other NAND 24.
is supplied to

Next, the operation of the latch circuit 8 including the set circuit 15 will be explained. When the rotation speed is outside the lock range, that is, in the section T _N , the set pulse P _S and the reset pulse P _R have the polarities shown in E and F in FIG. Therefore, the interval
In T _N , the flip-flop 1 of the smallest bit LSB
The outputs of flip-flop 17n-1 from bit 7a to MSB-1 all become "0".

In the above interval T _N , the output (NAND output) of the set circuit 15 is "H", but since the phase-inverted pulse _C is "0", one of the four input NANDs 24 becomes "0". The output of flip-flop 17n becomes "1". That is, in the section T _N outside the lock range, only the MSB bit becomes "1", and data corresponding to exactly 1/2 of the dynamic range of the latch circuit 8 is set. Therefore,
The phase control signal S _P is a signal having a level 1/2 of the maximum control level.

In addition, the section where the rotation speed is within the lock range
At T _L , the phase of pulse P _C is reversed, so the MSB
The set pulse P _S and the reset pulse P _R are released so that the lock state of the flip-flop 17n for the counter 7 is released, and the output when the output of the counter 7 is analogized has a ramp waveform as shown in FIG. 4A.
The polarity and pulse width are selected. in this case,
In the ramp period _TRL , both the set pulse _PS and the reset pulse _PR become "1", so the latch operation of the N+1 bit data is performed by the latch pulse _PLP .

In this way, when the rotation speed is outside the lock range, the level of the phase control signal S _P is 1/2 of the maximum amplitude.
Therefore, when the rotation speed falls within the lock range and the lock of the phase servo system is released, the phase servo starts with the phase control signal S _P of 1/2 of the maximum amplitude, so the lock time of the phase servo is shortened. In other words, the phase pull-in speed becomes faster.

In addition, in devices that digitally perform phase servo, the set and reset pulses P _S and _PR shown in Figure 3 or Figure 4 have been used for a long time, so there is no need to newly form them. By adding some circuits such as , set circuit 15, etc., the above-mentioned operation can be realized.

FIG. 5 and subsequent figures show other embodiments of this invention.

Figure 5 shows an example of a case where a counter for measurement is shared.If the ramp waveform for speed control and the ramp waveform for phase control are made not to overlap, one counter, for example, counter 2 for rotational speed measurement, can be used. can also be used as a phase measurement counter. Note that this shared configuration is not directly related to the gist of this invention, so a detailed explanation thereof will be omitted.

In this example as well, it is sufficient to associate the set circuit 15 with the latch circuit 8.

Figure 6 shows a case where this idea is applied to a PWM modulation type servo circuit, and the figure is an example of a phase servo circuit. In the figure, the clock CK supplied to the counter 7 is controlled by a gate pulse _PG formed by a rotational phase signal and a reference phase signal. The counter output is transferred to the memory 30, and the most significant bit of the transferred counter output is read out and the flip-flop 31 is set.
It is reset by an inverted pulse ₀ of clock CK ₀ with the same bit period as the most significant bit.

Since the timing at which the most significant bit is obtained differs depending on the counter output, the timing at which the flip-flop 31 is set is different, and this modulates the pulse width of the clock _CKO.If this is passed through the low-pass filter 32, the drum A phase control signal corresponding to the rotational phase of the motor 1 is generated.

Now, in the rotary phase servo circuit using such a PWM modulation method, the phase control signal forming means 12 is composed of the memory 30, the flip-flop 31, and the low-pass filter 32, so the intermediate value setting means 15 is connected to this means 12. provided.

In this example, the intermediate value setting means 15 is constituted by a logic gate. This logic gate 15 has first and second
It is composed of AND gates 41 and 42 and an OR gate 43, and the first AND gate 41 is connected to the memory 30.
This is to gate the output data of the AND gate 4, and the gate pulse used is the phase-inverted version of the pulse P _C.
2 is for gating the clock C _O , and the pulse P _C is used as the gate pulse. The OR outputs of the first and second AND gates 41 and 42 are used as a set pulse for the flip-flop 31.

With this configuration, when the rotational speed falls within the lock range (section T _L ), the first AND gate 41 opens and the flip-flop 31 is set with the output data of the memory 30, so the same rotational phase servo as described above is activated. It is done. Then, in the section T _N outside the lock range, the second AND gate 42 is opened, and the flip-flop 31 is set and reset by the pulse CK ₀ of a constant period.
The flip-flop 31 outputs a pulse with a duty of 50%.

Since the pulse output with a duty of 50% becomes an analog output with a value approximately in the middle of the dynamic range, the same effect as described above can be obtained.

Note that the rotating body is not limited to the above-mentioned drum, but may be a capstan or other rotating body.

Effects of the invention As explained above, according to this invention, a predetermined phase control signal to be held can be obtained with a relatively simple configuration, so it is possible to shorten the phase lock time as desired. can.

[Brief explanation of the drawing]

1, 5 and 6 are system diagrams showing an example of a control circuit for the rotational speed and rotational phase according to this invention, and FIG. 2 is a connection diagram showing an example of the main parts thereof,
FIGS. 3 and 4 are waveform diagrams for explaining the operation, respectively. 2 and 7 are counters, 3 and 8 are latch circuits, 4,
9 is a DA converter, 1 is a motor, 12 is a control signal forming means, and 15 is an intermediate value setting means.

Claims (1)

[Scope of utility model registration request] First counter 2 for measuring the rotational speed of the rotating body
a rotational body speed control circuit 10A having a first latch circuit 3 for latching the output of the first counter, and means 6 for detecting an overflow of the first counter; In the speed and phase control circuit for a rotating body, which includes a phase control circuit 10B having a second counter 7 for phase measurement and a second latch circuit 8 that latches the output of the second counter, the above-mentioned overflow detection Overflow detection pulse obtained by means
Only the MSB of the above second latch circuit is set to 1 by the PC.
1. A speed and phase control circuit for a rotating body, characterized in that it is provided with intermediate value setting means 15 for setting intermediate values.