JPH065709B2 - CMOS integrated circuit - Google Patents

Description

The present invention relates to a CMOS integrated circuit, and more particularly to a CMOS integrated circuit having latch-up resistance.

[Conventional technology]

Conventionally, the occurrence of latch-up due to external noise has been a problem in CMOS integrated circuits, and special attention has been paid to the design of I / O buffers.

As an example of the latch-up measure, it is common practice to separate the P-channel transistor and the N-channel transistor from each other. It surrounded the transistor regions of the channel and N channel.

[Problems to be solved by the invention]

Among the I / O buffers of the conventional CMOS integrated circuit described above, particularly in the output buffer, the P channel transistor region and the N channel transistor region are separated from each other in order to separate the P channel transistor region and the N channel transistor region from each other.
The channel transistor was arranged. Therefore, the output buffer becomes large in the lateral direction, and in the case of a circuit configuration having a large number of pins, there is a drawback that the chip size is limited by the number of output buffers.

On the other hand, if the P-channel transistor and the N-channel transistor are vertically stacked in order to reduce the bonding pad interval, the P-channel transistor and the N-channel transistor need to be separated from each other, so that an unnecessary isolation region is required for the circuit operation. Therefore, there is a drawback that the chip size is increased. In addition, it was not enough to take measures against latch-up simply by increasing the transistor interval of each channel.

The object of the present invention is to eliminate the above-mentioned drawbacks and eliminate the occurrence of the latch-up phenomenon without increasing the chip size.
It is to provide a MOS integrated circuit.

[Means for solving problems]

A CMOS integrated circuit according to the present invention includes an internal region formed on a first conductivity type semiconductor substrate and an I / I surrounding the internal region.
A second conductivity type isolation well region that separates the P channel MOS transistor and the N channel MOS transistor of the O buffer and is connected to a constant potential source, and a single channel MOS transistor provided outside the isolation well region And an external region formed with.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of an embodiment of the present invention, showing a case where a P-type well region for isolation is formed on an N-type semiconductor substrate.

In FIG. 1, an N-type semiconductor substrate 10 includes an internal region 4 in which a logic circuit and the like are formed, a region 2 in which a P channel MOS transistor as a single channel MOS transistor is provided, a bonding pad 1 and the like. An external area is provided, which further surrounds this internal area 4 and
An isolation P-type well region 3 (shaded to make it easy to see) for separating the O channel P channel MOS transistor and the N channel MOS transistor is provided.

FIG. 2 is an enlarged plan view of the B portion in FIG. 1, and shows a separation state of the P channel MOS transistor and the N channel MOS transistor of the I / O buffer by the separation P type well region 3. FIG. 3 is a sectional view taken along the line AA 'of the embodiment shown in FIG.

2 and 3, the isolation P-type well region 3 and the P-type well region 7 are grounded on the N-type semiconductor substrate 10.
And are formed. And in this P-type well region
An N-channel transistor region 9 in which an N-channel MOS transistor 9A forming an I / O buffer is formed is provided. On the other hand, I /
P channel MOS transistor 2 forming an O buffer
A P channel transistor region 2 in which A is formed is provided.

In FIGS. 2 and 3, 5 is an N ⁺ type diffusion layer region,
6 is a P ⁺ type diffusion layer region.

If positive noise equal to or higher than the power supply voltage is applied to the output terminal OUT, the drain of the P-channel MOS transistor 2A is forward biased and holes are injected into the N-type semiconductor substrate 10. In general, when this hole reaches the P-type well region 7, a PNP bipolar transistor is formed and its operation starts. However, as shown in this embodiment, the grounding P-type well region 3 for isolation exists between them. At this time, most of the injected holes are absorbed by the separating P-type well region 3 before reaching the P-type well region 7 in which the N-channel MOS transistor is formed. Therefore, the current amplification factor α of the PNP transistor is equivalently
Has become extremely small and does not satisfy the condition for latch-up occurrence.

On the other hand, if negative noise is added to the output terminal OUT,
Contrary to the above, the drain of the N channel MOS transistor 9A is forward biased and electrons are injected into the P type well region 7. This electron is also absorbed by the N ⁺ type diffusion layer region 5 before reaching the N type semiconductor substrate 10 by the same reason as described above. This N ⁺ type diffusion layer can be further enhanced by forming it in the P type well region 7 by adding another step.

FIG. 4 is a plan view of another embodiment of the present invention in which the arrangement of the separation P-type well region 3 as an absorption layer for injected carriers and the N ⁺ -type diffusion layer region 5 for setting the substrate potential is exchanged. And has the same effect as in the case of FIG.

In the above embodiment, the case of forming the P-type well region for isolation on the N-type semiconductor substrate has been described, but it goes without saying that the N-type well region for isolation may be formed on the P-type semiconductor substrate. is there.

〔The invention's effect〕

As described above, according to the present invention, the P-type well region or the N-type well region separates the inner region from the outer region, and only the single-channel MOS transistor exists in the outer region, so that the external surge is prevented. It is possible to obtain a CMOS integrated circuit that effectively prevents the latch-up that occurs and that does not pressurize the internal region even when the number of pins such as the gate array is large.

[Brief description of drawings]

1 is a plan view of an embodiment of the present invention, FIG. 2 is an enlarged plan view of portion B of FIG. 1, and FIG. 3 is an A- of the embodiment shown in FIG.
FIG. 4 is a sectional view taken along the line A ', and FIG. 4 is a plan view of another embodiment of the present invention. 1 ... Bonding pad, 2 ... P channel transistor region, 3 ... Separation P type well region, 5 ... N ⁺ type diffusion layer region, 6 ... P ⁺ type diffusion layer region, 7 ... P type well region, 9 ...
N-channel transistor region, 10 ... N-type semiconductor substrate.

Claims (1)

[Claims] 1. An internal region formed on a first conductivity type semiconductor substrate and a P-channel MOS transistor and an N-channel MOS transistor of an I / O buffer which surround the internal region and are separated from each other and connected to a constant potential source. A second conductivity type isolation well region and an external region provided outside the isolation well region and having a single-channel MOS transistor formed therein.