JPH0659643A - Distortion correction method for liquid crystal display device - Google Patents

Abstract

(57) [Abstract] [Purpose] In a PLL circuit of a liquid crystal display device, distortion of a display image is corrected. [Structure] In order to output a dot clock synchronized with a horizontal synchronizing signal of an input video signal, in a PLL circuit of a liquid crystal display device composed of a phase comparator 1, an LPF unit 2, a VCO unit 3 and a frequency dividing unit 4, horizontal synchronization is performed. A timing control unit 5 which is synchronized with the signal and outputs a control signal that allows the frequency of the dot clock from the VCO unit 3 to be varied within one horizontal synchronization period according to the distortion of the display image, and this control signal and L
The addition unit 6 that adds the output signal of the PF unit 2 and the average value of the signal from the addition unit 6 are set to LP so that the increment and decrement of the variable frequency thereof become the same within one horizontal synchronization period.
And a level shift unit 7 that matches the output level of the F unit. The signal from the level shift unit 7 is used as a control voltage of the VCO unit 3, and the pulse width of the output dot clock of the VCO unit 3 is changed. The display image is distorted in the opposite direction to correct the distortion of the display image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distortion correction method for a liquid crystal display device for correcting optical distortion of a display image in a projector or the like using the liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display device of a projector of this type has, for example, 1 LA as a system for driving a TFT type liquid crystal.
The T (Line at a Time) system is adopted. According to this drive system, a signal sampled during one horizontal synchronization period (1H) of an input video signal is displayed as an image in the next one horizontal synchronization period. It In this case, in order to display the sampled signal (image) on the liquid crystal display device, a dot clock (fck) synchronized with the horizontal synchronizing signal of the input video signal is required. The PLL circuit shown in FIG. 3 is used.

In the figure, this PLL circuit is composed of a phase comparator 1, an LPF (low-pass filter) unit 2, a VCO unit 3 and a frequency dividing unit (1 / N frequency dividing unit) 4.
The LL circuit tracks the horizontal synchronizing signal of the input video signal and matches the phase of the output dod clock with the horizontal synchronizing signal.

Further, in the liquid crystal display device, since the position of each pixel is fixed and does not physically move, the display position of the image is determined by the sampling position during the one horizontal synchronizing period. . The sampling position is determined by a dot clock (shown in FIG. 4B) determined by the number of pixels of the liquid crystal and the display effective period and a start pulse (shown in FIG. 4C) that determines the sampling start position.

[0005]

By the way, a display image of a liquid crystal display device such as the above-mentioned prosector may be optically distorted. In this case, since the normal sampling position is a timing after a fixed time from the rise of the dot clock (shown by the dotted line in FIG. 4), the sampling position can be changed by changing the pulse width of the dot clock. Since the position of each pixel is physically unchanged, it is possible to correct the optical distortion.

However, the frequency fck of the dot clock is fh (the frequency of the horizontal synchronizing signal) × N,
When the pulse width of the dot clock is changed according to the distortion of the display image, the frequency fck of the dot clock is 1 /
N does not become fh, that is, the number of dot clocks in one horizontal synchronization period changes, and the PLL circuit does not lock. Therefore, there is no means for correcting the optical distortion of the display image. It was

The present invention has been made in view of the above problems, and an object thereof is to provide a distortion correction method for a liquid crystal display device capable of correcting optical distortion of a display image of the liquid crystal display device. is there.

[0008]

In order to achieve the above object, the distortion correction method for a liquid crystal display device of the present invention enables an image by an input video signal to be displayed on the liquid crystal display device.
When the dot clock is generated in synchronization with the horizontal sync signal of the same input video signal, the pulse width of the dot clock is varied within one horizontal sync period of the horizontal sync signal according to the distortion of the display image of the liquid crystal display device. However, the gist is that the dot clock is modulated so that the increment and decrement of the variable pulse width become the same.

[0009]

With the above structure, in the PLL circuit for generating the dot clock, the frequency of the dot clock output from the VCO section is changed according to the distortion of the display image, that is, the pulse width is changed, and the variable. The increments and decrements by minutes are made the same within one horizontal synchronization period (1H). Therefore, the number of dot clocks generated within one horizontal synchronization period does not change, the PLL circuit is reliably locked, and the sampling position for image display can be changed according to the display image. You can
Then, by distorting the display image in the opposite direction, the distortion of the display image is corrected.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A distortion correction method for a liquid crystal display device according to the present invention is
FT-type liquid crystal is converted to 1LAT (Line at a Ti
me) When driven by the driving method, the pulse width of the dot clock generated in synchronization with the input video signal is changed within one horizontal synchronization period (1H) according to the optical distortion, and within the same one horizontal synchronization period. Then, the dot clock is FM-modulated so that the variable amount, the increased amount, and the reduced amount of the pulse width become the same.

Therefore, the PLL circuit for generating the dot clock has the configuration shown in FIG. Note that FIG.
In FIG. 3, those parts which are the same as those corresponding parts in FIG. 3 are designated by the same reference numerals, and a duplicate description will be omitted.

In the figure, this PLL circuit synchronizes with a horizontal synchronizing signal of an input video signal and outputs a control signal according to the optical distortion, and a timing control section 5 and a control signal from the timing control section 5 to an LPF. The addition unit 6 to be added to the output signal of the unit 2, the DC component of the output signal of the addition unit 6 is removed, and the level is shifted so as to be equal to the average value.
And a level shift section that uses the control voltage of the O section 3.

Next, a distortion correction method for a liquid crystal display device to which the PLL circuit having the above configuration is applied will be described with reference to the time chart of FIG. First, it is assumed that the image displayed on the liquid crystal display device is distorted by the optical system.

When any instruction is given to the timing control section 5, that is, an instruction according to the optical distortion, the timing control section 5 synchronizes with the horizontal synchronizing signal of the input video signal, A control signal that changes the frequency of the clock from the VCO unit 3 according to the optical distortion within one horizontal synchronization period (1H) is output (shown in FIG. 2B).
The output control signal of the timing control unit 5 is L at the addition unit 6.
The signal from the PF unit 2 (shown in FIG. 2C) is added (added to FIG. 2D), and the added signal has its DC component removed by the level shift unit 7 and its average. The value is level-shifted so as to match the output signal level of the LPF unit 2. The signal obtained by the level shift unit 7 is clocked from the VCO unit 3 in accordance with the optical distortion within one horizontal synchronization period. 2 becomes a control voltage that increases or decreases the frequency (shown by a and b in FIG. 2D), and the increase and decrease of this frequency become the same.

When the input control voltage of the VCO unit 3 becomes higher, the frequency of the output clock of the VCO unit 3 becomes higher,
In other words, the pulse width of the dot clock becomes narrower,
When the display image spreads in the horizontal direction and the input control voltage is low, the frequency of the output clock of the VCO unit 3 becomes low,
In other words, the pulse width of the dot clock becomes wider,
The display image is clogged in the horizontal direction, and the display image is distorted. Therefore, the timing control unit 5 may be instructed so that the input control voltage of the VCO unit 3 varies according to the state of the display image. For example, when the display image is optically distorted, It is sufficient to add the distortion of the reverse characteristic to.
The output control signal of the timing controller 5 is as shown in FIG.
The signal does not have to be the straight line shown in (b), and may be a curve signal corresponding to the distortion of the display image.

In this way, by issuing the instruction of the distortion having the opposite characteristic, the control voltage corresponding to the optical distortion of the display image becomes V.
Since it is input to the CO unit 3, in the VCO unit 3, the frequency of the current output clock (dot clock) is changed within one horizontal synchronization period, that is, the pulse width of the dot clock is increased and decreased, and The increment and decrement are made the same within one horizontal synchronization period. Therefore, the number of dot clocks generated within the one horizontal synchronization period does not change, that is, the lock of the PLL unit is not released, and the pulse width of the dot clock is variable according to the distortion of the display image. As a result, the displayed image is distorted by the reverse characteristic, and as a result, the distortion of the displayed image is corrected.

[0017]

As described above, according to the distortion correction method for a liquid crystal display device of the present invention, since an image according to an input video signal can be displayed on the liquid crystal display device, it is synchronized with the horizontal synchronizing signal of the input video signal. When a dot clock is generated by changing the pulse width of the dot clock within one horizontal synchronizing period of the horizontal synchronizing signal in accordance with the distortion of the display image of the liquid crystal display device, the pulse width is increased or decreased. Since the dot clock is modulated so that the same becomes, the sampling position for image display can be changed according to the distortion of the display image within one horizontal synchronization period.
Further, since the number of dot clocks generated within one horizontal synchronization period does not change, a PL that generates the same dot clock is generated.
There is a useful effect that the L circuit is reliably locked and the distortion (optical distortion) of the display image can be corrected.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a PLL circuit to which an embodiment of the present invention is applied, to which a distortion correction method for a liquid crystal display device is applied.

FIG. 2 is a schematic time chart diagram for explaining the distortion correction method for the liquid crystal display device of the present invention.

FIG. 3 is a schematic block diagram of a PLL circuit used in a conventional liquid crystal display device.

FIG. 4 is a schematic time chart diagram for explaining the operation of the conventional liquid crystal display device.

[Explanation of symbols]

 1 phase comparator 2 LPF section 3 VCO section 4 frequency division section 5 timing control section 6 adder section 7 level shift section

Claims (1)

[Claims] 1. When a dot clock is generated in synchronization with a horizontal synchronizing signal of the input video signal so that an image based on the input video signal can be displayed on a liquid crystal display device, within one horizontal synchronizing period of the horizontal synchronizing signal. With the pulse width of the dot clock is varied according to the distortion of the display image of the liquid crystal display device,
The distortion correction method for a liquid crystal display device, wherein the dot clock is modulated so that the increment and the decrement of the variable pulse width are the same.