JPH0659658A - Look up table device - Google Patents

Abstract

(57) [Abstract] [Purpose] With a small amount of hardware, a flat panel display and a CRT display can be commonly and simultaneously used, and high-speed display can be achieved. [Structure] Image data transferred from a frame memory in units of four pixels is latched by an input latch 101, and then output by a shift register 102 pixel by pixel in order of display, and a color palette memory 111 outputs R, G, and B colors. The CRT display 20 is converted into brightness information and converted into an analog brightness signal by the DA converter 121.
It is output to 0. Further, of the image data latched by the input latch 101, the image data of the second to fourth pixels is converted into luminance information for each color by the color palette memories 112 to 114. Memories 111-114
The luminance information from 1 to 3 is latched by the output latches 131 to 134 at the output timing of the luminance information corresponding to the first pixel, and is output to the flat panel display 300.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a look-up table device for a display device applied to information processing equipment such as a computer.

[0002]

2. Description of the Related Art Conventionally, a look-up table device used for displaying an image on a display device of information processing equipment such as a computer has a built-in DA converter (digital / analog conversion circuit) for a color CRT display. There was something.

On the other hand, in recent years, flat panel displays such as LCD displays (liquid crystal displays) are often used for display output of information processing equipment.

However, in order to display a color or gradation on a flat panel display, luminance information is required as digital data of several bits, so that it is not possible to use the above-mentioned look-up table device for a color CRT display. could not.

[0005]

As described above, in the past, it was not possible to use a look-up table device for a CRT display to perform color or gradation display on a flat panel display. Apart from
A dedicated memory, an LSI with a built-in memory, etc. had to be prepared independently, which was a space and cost burden.

The present invention has been made in view of the above circumstances, and an object thereof is a lookup which can be used commonly and simultaneously for a flat panel display and a CRT display while achieving a high speed display with a small amount of hardware. To provide a table device.

[0007]

According to the present invention, an input latch for inputting image data from a frame memory in units of n pixels, and image data for n pixels input by the input latch are displayed pixel by pixel in display order. A parallel / serial conversion circuit for outputting and a first for converting a color or gradation index of image data output pixel by pixel from the parallel / serial conversion circuit into brightness information and outputting the brightness information.
Of the color palette memory and the image data for n pixels input by the input latch, the color or gradation index of each image data of n-1 pixels except one pixel in a predetermined display order is used as luminance information. Second to nth color palette memories for converting to and outputting the first color and the first color
And a digital / analog conversion circuit (DA converter) for converting the luminance information converted and output from the color palette memory into an analog luminance signal and outputting the analog luminance signal to the CRT display, and converting output from the first to nth color palette memories. The luminance information corresponding to one pixel in the predetermined display order is latched at the timing when the luminance information is converted and output from the first color palette memory, and is digitally output to the flat panel display. Through nth output latch.

[0008]

In the above structure, image data is periodically fetched in n pixel units from the frame memory into the input latch so that high speed display data processing can be performed. The parallel image data for n pixels fetched by the input latch is sent to the parallel / serial conversion circuit, and is output pixel by pixel in the display order. The image data output from the parallel / serial conversion circuit pixel by pixel in the display order becomes an address of the first color palette memory. As a result, the luminance information corresponding to the address (that is, the color or gradation index of the image data) is sequentially output from the first color palette memory pixel by pixel.

Further, of the image data of n pixels taken in by the input latch, one pixel in a predetermined display order, for example, n-1 pixels excluding the first pixel (second to nth pixels).
Image data of the second pixel)
Of the color palette memory at the same time to become the address of the same memory, so that the address (that is, the second to the nth color palette memory) is read from the second to the nth color palette memories.
Luminance information corresponding to the color or gradation index of the image data of the th pixel is output at the same time.

Luminance information sequentially output pixel by pixel from the first color palette memory is led to a DA converter,
The converter converts into an analog luminance signal. A CRT display can be connected to the output of the DA converter, and the CRT display is performed by sending an analog luminance signal output from the converter to the CRT display.

In addition, 1 from the first color palette memory
The luminance information that is sequentially output pixel by pixel is also guided to the first output latch. The first output latch performs a latch operation at the timing when the luminance information of the first pixel (one pixel in a predetermined display order) is output from the first color palette memory. As a result, the first output latch receives the data in n-pixel units by the input latch and outputs the pixels one by one in the display order (from the first pixel to the n-th pixel) by the parallel / serial conversion circuit. Of the image data
Only the luminance information corresponding to the color or gradation index of the image data of the first pixel (one pixel in a predetermined display order) is sequentially latched.

The luminance information output in parallel from the second to nth color palette memories, that is, the first pixel (in a predetermined display order) of the image data taken in n pixel units by the input latch. N-1 pixels (second pixel)
The luminance information corresponding to the color or gradation index of the image data of the (nth to nth pixel)
Of the first output latch and is latched at the same timing as the first output latch.

A flat panel display can be connected to the outputs of the first and second output latches, and digital luminance information for n pixels output in parallel from the latch is sent to the flat panel display. Thus, a flat panel display is performed.

As described above, in the above configuration, even if digital luminance information is sent to the flat panel display in units of n pixels for high-speed display data processing, for one pixel, the luminance information is sent to the DA converter. 1 color palette memory can be shared, so the number of color palette memories can be reduced by one compared to the case of using two look-up table devices for a flat panel display and a CRT display. Since it can be shared, the amount of hardware can be reduced.

[0015]

1 is a block diagram showing the configuration of a look-up table device according to an embodiment of the present invention.

In FIG. 1, reference numeral 100 is a look-up table device, which is a CRT display 200 and L.
Flat panel displays 300 such as a CD display, an EL (electro luminescence) display, and a plasma display can be connected in parallel.

In the look-up table device 100, reference numeral 101 is for inputting image data in a plurality of pixels (pixels), for example, in units of 4 pixels (4p) from a frame memory (not shown) in which image information for screen display is stored. Input latch of. In this embodiment, it is assumed that the image data of one pixel (1p) on the frame memory is composed of 8-bit color or gradation index. The input latch 101 performs a latch operation by the clock signal CK1.

Reference numeral 102 designates the image data of 4 pixels (4p) input by the input latch 101 as 1 pixel (1
p) for each parallel / serial conversion circuit, for example, a shift register (SR). Shift register 102
Performs a parallel / serial conversion operation (shift operation) with the clock signal CK2 having a quarter cycle of the clock signal CK1.

111 is the output of the shift register 102 (1
This is a color palette memory for reading out and outputting the luminance information of each color of R (red), G (green), and B (blue) by using the pixel color or gradation index) as an address input. This brightness information has, for example, an 8-bit structure,
56 gradations can be displayed.

Reference numerals 112 to 114 denote three pixels of the image data for four pixels input by the input latch 101, excluding one pixel (first pixel) in a predetermined display order, for example, the first display order. The color or gradation index of each image data (second to fourth pixels) is used as an address input to read 8-bit luminance information of each color of R (red), G (green), and B (blue). A color palette memory for output.

The color palette memories 111 to 114 are
Both are composed of RAM, and the contents are the same. However, in this embodiment, the color palette memory 11
A low-speed RAM having a memory speed of about 1/4 that of the color palette memory 111 is used for each of 2 to 114.

Reference numeral 121 denotes a DA converter which converts the luminance information output from the color palette memory 111 into analog luminance signals for each of R, G and B colors. The CRT display 200 can be connected to the output of the DA converter 121.

Reference numerals 131 to 134 denote color palette memory 1
It is an output latch that latches the luminance information output from 11 to 114 by the clock signal CK3. The clock signal CK3 has the same cycle as the clock signal CK1, that is, four times the cycle of the clock signal CK2, and corresponds to the timing at which the luminance information corresponding to the first pixel is output from the color palette memory 111. The flat panel display 300 can be connected to the outputs of the output latches 131 to 134.

Reference numeral 141 is a CPU interface (CPU-IF) which forms an interface with a host CPU such as a microprocessor (not shown). The host CPU reads / writes the contents of the color palette memories 111 to 134 via the CPU interface 141. Next, the operation of the configuration of FIG. 1 will be described.

First, the host CPU has the color palette memories 111 to 114 in the look-up table device 100.
On the other hand, by performing a common write operation via the CPU interface 141, the same contents are preset in the memories 111 to 114.

Next, when actually displaying an image on the CRT display 200 and / or the flat panel display 300 using the look-up table device 100, the host CPU sends a clock signal CK1 from a frame memory (not shown). The image data (4 × 8 bits) is read in units of 4 pixels (4p) in synchronization with the clock signal having the same cycle as the above, and is transferred to the lookup table device 100.

The input latch 101 in the look-up table device 100 latches the image data transferred from the frame memory in units of 4 pixels by the clock signal CK1. The image data for 4 pixels (4 × 8-bit color or gradation index) latched by the input latch 101 is guided to the shift register 102 as it is.

The shift register 102 includes an input latch 10
Image data for 4 pixels (4p) from 1 is output one pixel by one pixel (1p) in the display order in synchronization with the clock signal CK2 (of a quarter of the clock signal CK1). The image data output from the shift register 102 on a pixel-by-pixel basis is guided to the color palette memory 111.

The color palette memory 111 is addressed with the image data (8-bit color or gradation index) output from the shift register 102 on a pixel-by-pixel basis as an address input. As a result, every time image data (8-bit color or gradation index) is output from the shift register 102 on a pixel-by-pixel basis, the color palette memory 1 indicated by the image data is output.
8-bit luminance information (digital luminance information) for each color of R, G, B at the 11th address position is read from the memory 111. That is, the image data (8-bit color or gradation index) output from the shift register 102 on a pixel-by-pixel basis is converted by the color palette memory 111 into 8-bit luminance information for each color of R, G, and B.

Now, of the image data of 4 pixels (4 × 8 bit color or gradation index) latched by the input latch 101, the image data of the pixel in the second display order (8 bit color or The gradation index) is stored in the color palette memory 112, and the image data (8-bit color or gradation index) of the pixel in the third display order is stored in the color palette memory 113.
The image data (8-bit color or gradation index) of the pixels in the second (last) display order is introduced to the color palette memory 114, respectively.

The color palette memories 112 to 114 are
The image data (8-bit color or gradation index) of the second to fourth pixels of the image data of four pixels latched by the input latch 101 is addressed as an address input. As a result, every time the input latch 101 latches the image data in units of 4 pixels, the color palette memories 112 to 11 indicated by the image data of the second to fourth pixels among them.
The 8-bit luminance information for each color of R, G, and B at the 4 internal address positions is read from the memories 112 to 114, respectively. That is, the image data (8-bit color or gradation index) of the second to fourth pixels of the image data of four pixels latched by the input latch 101 is read by the color palette memories 112 to 114. , G, B are converted into 8-bit luminance information for each color.

The 8-bit luminance information for each color of R, G, B output from the color palette memory 111 is guided to the DA converter 121. The DA converter 121 converts the brightness information for each color of R, G, B from the color palette memory 111 into an analog brightness signal and outputs it to the CRT display 200. As a result, CRT display is performed on the CRT display 200.

The luminance information for each color of R, G, B output from the color palette memory 111 is also led to the output latch 131. The output latch 131 is (clock signal CK
The latch operation is performed at the timing when the luminance information corresponding to the first pixel is output from the color palette memory 111 by the clock signal CK3 having the same period as 1 (that is, a period four times the clock signal CK2). This allows
Of the luminance information for each color of R, G, and B output from the color palette memory 111, only the luminance information corresponding to the first pixel is latched in the output latch 131.

On the other hand, the color palette memories 112 to 11
The luminance information for each color of R, G, and B corresponding to the second to fourth pixels output from No. 4 is output by the output latch 132.
Lead to ~ 134. Like the output latch 131, the output latches 132 to 134 perform a latching operation with the clock signal CK3 (having the same cycle as the clock signal CK1, that is, four times the cycle of the clock signal CK2). As a result, the output latches 132 to 134 have the color palette memory 11
Luminance information for each color of R, G, B corresponding to the second to fourth pixels output from Nos. 2 to 114 is latched.

As described above, in the output latches 131 to 134, every time image data is latched by the input latch 101 in units of 4 pixels, the first to fourth pixels forming the latched 4 pixels. The luminance information for each color of R, G, B corresponding to is latched at the same timing. R, G, B latched by the output latches 131 to 134
The luminance information (digital luminance information) for each color is output to the flat panel display 300 simultaneously for four pixels. As a result, flat panel display is performed on the flat panel display 300.

In the above-mentioned lookup table device 100, when only the flat panel display 300 is connected and displayed, all the image data transferred from the frame memory in units of 4 pixels can be processed in parallel. Compared with the case where only the display 200 or both the CRT display 200 and the flat panel display 300 are connected and displayed, the clock signal CK
The cycle of 1 to CK3 can be quadrupled, so that the power consumption can be significantly reduced (about 1/4).

In the above embodiment, the input latch 101
The brightness information of the first pixel of the brightness information sequentially output from the color palette memory 111 in units of one pixel corresponding to the image data of four pixels latched by
The case of sharing a digital output to the flat panel display 300 has been described.
It is also possible to share any one of the fourth pixels for digital output to the flat panel display 300. In this case, the remaining 3 pixels except the shared pixel are input from the input latch 101 to the color palette memory 1
It suffices to supply pixels 12 to 114 one by one.

In the above embodiment, the input latch 101 is used.
The case where the shift register 102 is used as the parallel / serial conversion circuit for the image data of four pixels latched in the above has been described, but it is also possible to use a multiplexer that selectively outputs the image data of four pixels one pixel at a time in the display order. Is.

Further, in the above embodiment, the look-up table device 100 (the input latch 1 in
Although the image data input unit to 01) is 4 pixels, a low-speed color palette memory corresponding to the color palette memories 112 to 114 is used even if it is n pixels (n is an integer of 2 or more). The same application is possible by providing n-1 pieces and providing n output latches corresponding to the output latches 131 to 134.

[0040]

As described above in detail, according to the present invention,
Even if digital brightness information is sent to the flat panel display in units of n pixels for high-speed display data processing, for one pixel, a color palette memory for the CRT display that sends brightness information to the DA converter (first Since the color palette memory can be shared, the number of color palette memories for the flat panel display can be n−1 (of the second to nth color palette memories), and the lookup table device for the flat panel display and the CRT display can be used. It is possible to reduce the amount of hardware as compared with the case of independently providing.
Further, according to the present invention, since the input latch can be shared, the amount of hardware can be reduced also in this respect.

Further, according to the present invention, when only a flat panel display is connected and displayed, all the image data transferred from the frame memory in units of n pixels can be processed in parallel. Alternatively, as compared with the case where both a CRT display and a flat panel display are connected and displayed, the power consumption can be reduced by operating at a low speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a look-up table device according to an embodiment of the present invention.

[Explanation of symbols]

100 ... Look-up table device, 101 ... Input latch, 102 ... Shift register (SR, parallel / serial conversion circuit), 111-114 ... Color palette memory, 121 ... DA converter, 131-134 ... Output latch, 141 ... CPU interface (CPU-I
F), 200 ... CRT display, 300 ... Flat panel display.

Claims (1)

[Claims] 1. A look-up table device for a display device that performs color or gradation display, and an input latch for inputting image data in n-pixel units from a frame memory that stores image information for screen display. A parallel / serial conversion circuit that outputs the image data of n pixels input by the input latch pixel by pixel in the display order, and a color or gradation index of the image data that is output pixel by pixel from the parallel / serial conversion circuit. A first color pallet memory for converting and outputting to luminance information; and n-1 pixel of the image data of n pixels input by the input latch except one pixel in a predetermined display order. Second to nth color palette memos for converting the color or gradation index of each image data into luminance information and outputting it A digital / analog conversion circuit for converting the luminance information converted and output from the first color palette memory into an analog luminance signal and outputting the analog luminance signal to the CRT display; and converting from the first to nth color palette memories. The output brightness information is latched at the timing when the brightness information corresponding to one pixel in the predetermined display order is converted and output from the first color palette memory, and digitally output to the flat panel display. A lookup table device comprising: first to nth output latches;