JPH0668190A - Functional test program generation system - Google Patents

Abstract

(57) [Summary] [Purpose] To reduce the manpower and time required for the functional test of the actual LSI. [Structure] The MAX delay result holding unit 2 and the MIN delay result holding unit 3 hold the MAX delay and the MIN delay timing simulation results under each operating condition, respectively, and show the delay generated between the MAX delay and the MIN delay. Time difference
When the delay time difference between the MAX delay and the MIN delay held in the margin value information holding unit 4 does not exceed the allowable value in the product standard, the shared test program 6 is generated by strobe masking the test pattern in the period in which the delay time difference occurs. When the delay time difference exceeds the allowable value and causes an operation error, the operation condition is output as the error list 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function test program generation system included in an LSI design process.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of a conventional functional test program generation system. The simulation execution unit 1 performs a timing simulation under each operating condition in which the operating conditions of the product standard value, operating temperature, process used, power supply voltage, etc. are changed, and the maximum delay within the allowable range of the product standard is achieved. The MAX delay result holding unit 2 holds the simulation result when the time is set,
The MIN delay result holding unit 3 holds the simulation result when the minimum delay time is set within the allowable range of the product standard.

A test pattern generator (abbreviated as TPG) executing section 5 generates a MAX delay test program 8 from the data held in the MAX delay result holding section 2 and a data held in the MIN delay result holding section 3. MIN
The delay test program 9 is generated.

The functional test for verifying the signal propagation delay in the actual LSI test is performed as a result of the timing simulation executed under the operating condition corresponding to the operating condition in the actual test.
A functional test is performed twice using two programs, a MAX delay test program 8 and a MIN delay test program 9, which are generated by the TPG execution unit 5.

[0005]

Since the conventional functional test program generation system is configured as described above, the operating conditions such as the operating temperature, the process used, and the power supply voltage are changed from the operating conditions of the product standard value. Timing simulation of MAX delay and MIN delay is performed, the result of each delay condition is processed by TPG individually, and two test programs for MAX delay and MIN delay are used separately according to the operating conditions in the actual test. Since the function test is performed twice by using the above method, there is a problem that a lot of manpower and time are required for the function test of the actual machine.

The present invention has been made in order to solve such a problem, and by generating a function test program for both maximum delay and minimum delay, the manpower and time required for the function test of an actual machine are significantly increased. The purpose is to provide a functional test program generation system that reduces the

[0007]

According to the functional test program generation system of the present invention, as a result of the timing simulation in which the maximum delay and the minimum delay are set, in the signal propagation period in which the delay time difference occurs, the generated delay time difference is
If it does not exceed the allowable value stored in advance, a functional test program that does not compare the test pattern of the propagation period that causes the delay time difference and the signal propagation pattern in the actual circuit is generated, while the delay time difference exceeds the allowable value. When an operation error occurs, the operation condition that causes the operation error is output.

[0008]

The functional test program generation system according to the present invention has the maximum delay time and the minimum delay time in the signal propagation test pattern obtained by executing the timing simulation in which the maximum delay and the minimum delay are set under each operating condition. If the delay time difference of the signal propagation period in which the delay time difference is generated does not exceed the allowable value of the delay time difference stored in advance, the test pattern of this signal propagation period and the input input to the simulation circuit during the timing simulation. A function program that does not compare with a signal propagation pattern obtained by inputting a signal sequence into an actual circuit is generated. If the delay time difference exceeds the allowable value and causes an operation error,
Outputs operating conditions that cause an operating error.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. FIG. 1 is a block diagram of a functional test program generation system according to the present invention (referred to as the present invention system). The simulation execution unit 1 performs a timing simulation under each operating condition in which the operating conditions of the product standard value, operating temperature, process used, power supply voltage, etc. are changed, and the maximum delay within the allowable range of the product standard is achieved. The MAX delay result holding unit 2 holds the simulation result when the time is set, and the MIN delay result holding unit 3 holds the simulation result when the minimum delay time is set within the allowable range of the product standard.

The margin value information holding unit 4 holds the delay time difference between the maximum delay and the minimum delay allowed in the product standard as a margin value. The test pattern generator (abbreviated as TPG) execution unit 5 includes the MAX delay result holding unit 2
Compares the data held by the MIN delay result holding unit 3 with the data held by the MIN delay result holding unit 3, and the delay time difference in the period in which the delay time difference occurs between them does not exceed the margin value held in the margin value information holding unit 4. In the case of MAX, the strobe mask of the test pattern for the period with the delay time difference
The shared test program 6 for delay and MIN delay is generated, and when the delay time difference exceeds the margin value, the operation condition that causes an operation error is output as the error list 7.

The functional test for verifying the signal propagation delay in the actual LSI test is performed as a result of the timing simulation executed under the operating condition corresponding to the operating condition in the actual test.
Shared test program 6 generated by TPG execution unit 5
Perform functional tests using.

A procedure for generating a functional test program by the system of the present invention having the above-described configuration will be described with reference to the flowchart shown in FIG. In the figure, the sample signal value at time t of the MAX delay simulation result is Ma
x (t), MIN Let the sampled signal value at time t of the delay simulation result be Min (t) and the margin value be M.

The TPG execution unit 5 sets the maximum delay and the minimum delay under each operating condition, and the result of the timing simulation executed by the simulation execution unit 1 is M
Max (t) and Min (t) are extracted from the signal propagation test pattern held by the AX delay result holding unit 2 and the signal propagation test pattern held by the MIN delay result holding unit 3 (S1), Max (t t)
And Min (t) determine whether there is a time t at which the sample signal values do not match (S2). If there is no time t at which they do not match, there is no time difference between the MAX delay and MIN delay. The sample signal value is output as it is as a test pattern (S3).

If there is a time t at which the sampled signal values do not match as a result of the determination at step S2, a time t at which they do not match.
It is determined whether the delay time difference between the MAX delay and the MIN delay is less than the margin value M (S4).

When the delay time difference in the mismatch period is less than or equal to the margin value M, it is not necessary to verify the function of the actual device by comparing the output pattern of the actual device with the test pattern in the mismatch period in which the delay time difference is less than or equal to the margin value. , A test pattern obtained by strobe masking the test pattern in the mismatch period is output (S5).

On the other hand, if the result of determination in step S4 is that the delay time difference between the non-coincidence periods exceeds the margin value M, a logic operation error occurs, so the operation conditions in the timing simulation at that time are output as an error list (S
6).

[0017]

As described above, the system of the present invention generates a shared functional test program with the maximum delay and the minimum delay, and outputs an operating condition that causes an operating error as an error. It has an excellent effect of drastically reducing manpower and time required for.

[Brief description of drawings]

FIG. 1 is a block diagram of a system of the present invention.

FIG. 2 is a flowchart showing a procedure for generating a functional test program by the system of the present invention.

FIG. 3 is a block diagram of a conventional functional test program generation system.

[Explanation of symbols]

 1 Simulation execution unit 2 MAX delay result storage unit 3 MIN delay result storage unit 4 Margin value information storage unit 5 TPG execution unit 6 Shared test program 7 Error list

Claims (1)

[Claims] 1. An expected signal propagation pattern is obtained as a result of executing a timing simulation in which an input signal train is supplied to a simulation circuit and maximum delay and minimum delay of each circuit component under each operating condition are set. The test pattern is compared with the signal propagation pattern in the actual circuit obtained as a result of inputting the input signal sequence into the actual circuit, and it is verified whether or not the signal propagation delay in the actual circuit satisfies the specifications. In the system for generating a functional test program, a means for storing the allowable value of the delay time difference at the maximum delay time and the minimum delay time, and a signal propagation period in which a delay time difference occurs in the timing simulation between the maximum delay time and the minimum delay time. If the delay time difference between the maximum delay time and the minimum delay time does not exceed the allowable value, the test pattern in the signal propagation period And a means for generating a functional test program that does not compare the signal propagation pattern in the actual circuit in the signal propagation period, and if the delay time difference exceeds the allowable value to cause an operation error, cause the operation error A functional test program generation system comprising: means for outputting an operating condition.