JPH067595B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[Field of Industrial Application] The present invention relates to a metal-insulator-semiconductor field effect transistor (MISFET) having a simple structure. [Prior Art] In a conventional MISFET, two diffusion layer sources 8 and drains 9 of a conductivity type different from the conductivity type of the substrate are provided on the surface of a semiconductor substrate 1 as shown in FIG. The inversion layer 10 was formed on the surface of the substrate 1 via the insulating film 3, and a current was passed between the source 8 and the drain 9. Therefore, a source 8 and a drain 9 and two belief layers are required. [Object of the Invention] The present invention requires only one diffusion layer of a conductivity type different from the substrate conductivity type as compared with the conventional MISFET, and enables high integration of a circuit. [Structure and Operation of the Invention According to the Embodiment] Embodiment 1. Next, FIG. 2 shows a first embodiment, which is a basic structure of the present invention, for explaining the present invention in detail with reference to the drawings. Reference numeral 1 denotes a semiconductor substrate, a surface of which is provided with a diffusion layer 2 having a conductivity type different from that of the substrate, an insulating film 3 is provided on the surfaces of these two regions, and a gate electrode 4 is provided thereon. Has been. Next, the operation principle will be described. FIG. 3 is a potential diagram along the line AA ′ in FIG. A voltage VG is applied to the gate electrode 4 with respect to the substrate 1 to form a depletion layer 1 ′ on the substrate surface, and the electric field of this depletion layer is very strong so that Zener breakdown of electrons (arrow e ⁻ ) is possible. To Carriers generated in the depletion layer 1 ′ due to Zener breakdown (hereinafter referred to as zwitter carriers) are attracted to the potential VD of the diffusion layer 2 and flow into the diffusion layer 2 from the depletion layer 1 ′ on the substrate surface as indicated by arrow B in FIG. . As described above, the semiconductor device according to the present invention is
Allows operation with only one diffusion layer. Example 2. However, in order to obtain a strong electric field of the depletion layer 1 ′ that causes Zener breakdown with a relatively small voltage VG of the electrode 4, the substrate concentration is increased and the electrostatic capacitance per unit area of the insulating film 3 is increased. It is necessary to. A cross-sectional view of a second embodiment realizing this is shown in FIG. In FIG. 4, the insulating film 3 is made as thin as possible, and adjacent to the diffusion layer 2 having the same conductivity type as the substrate conductivity type and the concentration higher than that of the substrate on the substrate surface below the gate electrode 4 in order to increase the surface concentration. To be formed. In an actual device in which silicon dioxide is selected as the insulating film 3, the film thickness of silicon dioxide is 70Å, the concentration of the diffusion layer 5 is 5 × 10 ¹⁸ / cm ⁻³ , and the voltage VG of the electrode 4 is VG =
It can operate at 5V. Example 3. In the second embodiment shown in FIG. 4, the thinner the insulated wire 3 is, the better, but if it is too thin, a problem occurs. that is,
That is, a tunnel current flows between the gate electrode 4 and the diffusion layer 2. FIG. 5 is a sectional view of a third embodiment made to overcome this drawback. The diffusion layers 2 and 5 are separated from each other at a certain distance, and are located on the region from the point C to the diffusion layer 2 rather than on the insulating film 3 on the region from a certain point C to the diffusion layer 5 between them. By making the insulating film 3 ′ thicker, a tunnel current between the gate electrode 4 and the diffusion layer 2 can be prevented. Further, for example, if a nitrogen film having a relatively high dielectric constant is selected as the insulating film 3 and a silicon dioxide film having a high barrier and having a small current flow is selected as the insulating film 3 ', the two insulating films have redundancy. be able to. Example 4. Another method for maintaining the insulation between the gate electrode and the diffusion layer 2 is to separate the gate electrode 4 and the diffusion layer 2 by a certain distance l ₁ . FIG. 6 is a sectional view of the fourth embodiment by the above method. In this case, l ₁ needs to be smaller than the width W of the depletion layer 6 generated by the substrate 1 and the diffusion layer 2. l ₁ = W
In the case of, the Zener carrier generated by Zener breakdown in the depletion 1'of the substrate surface under the gate electrode 4 is the depletion layer 6
That Nagarekome the diffusion layer 2 of Te diameter but, W <depletion in l ₁ 1 'Tsuenakiyaria in the depletion layer 1 trapped' because can not flow out. Example 5. Also in the case of the fourth embodiment, a structure in which the diffusion layer 5 is provided in order to strengthen the surface electric field can be considered. A sectional view of the fifth embodiment showing this structure is shown in FIG. In this case, the diffusions 2 and 5 may be adjacent to each other. The insulating film 3 is preferably as thin as possible also in this embodiment. The material of the insulating film 3 may be silicon dioxide, silicon nitride having a high dielectric constant, alumina, or the like in all the examples. Example 6. Next, FIG. 8 shows a plan view of a sixth embodiment of the MISFET according to the present invention. Generally, in the MISFET, the current flows from the source to the drain only in one direction.
In the SFET, the Zener carrier generated by Zener breakdown near the surface of the substrate shown in the region 100 or the diffusion layer of the same conductivity type as the substrate may flow into the diffusion layer 2, so that the diffusion layer 2 of the conductivity type different from that of the substrate A structure shown at 100 surrounding the substrate or diffusion layer is efficient. Although FIG. 8 shows a quadrangle, other polygons or circles may be used as long as it has a surrounding structure. Next, the static characteristics of the MISFET according to the present invention are shown in FIG. In FIG. 9, the horizontal axis and the vertical axis represent the voltage VD and the current ID between the substrate 1 and the diffusion layer 2, respectively, and the voltage VG of the gate electrode 4 is used as a parameter. FIG. 9 shows the experimental results when the second embodiment shown in FIG. 4 was used. The substrate 1 is P-type and the concentration of the diffusion layer 5 is 6 × 10 ^1-8 c
m ^-3 , the insulating film 3 is 100 Å of silicon dioxide, and the width of the gate electrode 4 is for a sample of 200 μm. If the concentration of the diffusion layer 5 is further increased and the diffusion layer 5 is thinned with the insulating film 3, it is possible to obtain a current of 1 uA or more at a gate voltage of about 5V. As shown in FIG. 9, the static characteristics of the MISFET according to the present invention are similar to those of general MISFETs. Therefore, it can be used as an element such as a switching element and a logic circuit element. Example 7. FIG. 10 is a CM using the MISFET according to the present invention.
It is a seventh embodiment of the OS inverter circuit. Reference numeral 1 is an N-type substrate on which a P-type welter is formed. 2,2 '
Are N ⁺ type diffusion layers and P ⁺ type diffusion layers, and 5 and 5 ′ are P type diffusion layers and N type diffusion layers, respectively, which are short-circuited to each other and connected to the external terminal V out. The two elements are provided with gate electrodes 4 and 4'through an insulating film 3, which are short-circuited to each other and connected to a terminal Vin. The potential of 2'is fixed to Vss and the two potentials are fixed to Voo higher than Vss. Now, when Vin is set to V _DD , a strong electric field is generated only near the surface of the diffusion layer 2 ', and electrons are generated by Zener breakdown and flow into the diffusion layer 5'. Therefore, the potential Vout of 5'becomes equal to Vss. Conversely, when Vin is set to Vss, a strong electric field is generated only near the surface of the diffusion layer 2 and a current flows only between the diffusion layers 2'and 5, so that Vout
Will be equal to V _DD . The above shows that the inverter is operating. [Advantages of the Invention] As described above, the MISFET according to the present invention is
Despite the fact that there is no diffusion layer corresponding to the source of T, it operates almost the same as the conventional one, so a small area is required and the conventional MI is used in the semiconductor integrated circuit aiming at high integration in the future.
It is an important element that replaces SFET.

[Brief description of drawings]

FIG. 1 is a sectional view of a conventional MISFET, FIG. 2 is a sectional view of a MISFET of a first embodiment according to the present invention, FIG. 3 is a potential diagram showing the principle of the MISFET shown in FIG. 2, and FIG. Is a sectional view of the second embodiment of the present invention, FIG. 5 is a sectional view of the third embodiment of the present invention, FIG. 6 is a sectional view of the fourth embodiment of the present invention, and FIG. FIG. 8 is a sectional view of a fifth embodiment of the invention, FIG. 8 is a plan view of a sixth embodiment of the invention, FIG. 9 is a view showing static characteristics of the MISFET shown in FIG. 4, and FIG. FIG. 11 is a cross-sectional view of a CMOS inverter using a MISFET according to the seventh embodiment of the above. 1 ... Semiconductor substrate 1 '... Depletion layer of semiconductor substrate 2, 2' ... Substrate, well and diffusion layer of different conductivity type 3, 3 '... Insulating film 4 ... Gate electrode 5, 5 ... Substrate, Diffusion layer of the same conductivity type as the well 6 ... Depletion layer due to the substrate and the diffusion layer 7 ... Well 8 ... Source 9 ... Drain 10 ... Channel.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kojiro Tanaka 6-31-1, Kameido, Koto-ku, Tokyo Inside the Second Seikosha Co., Ltd. (56) References Japanese Patent Laid-Open No. 50-27483 (JP, A) Kai 50-30486 (JP, A) Tokuyama Shiba, "Electronics Technology Complete Book [3] MOS Devices" (2nd edition), (Showa 50-6-10) Industrial Research Committee, p. 299-P. 316

Claims (3)

[Claims] 1. A first region made of a semiconductor of a first conductivity type, a second region provided adjacent to or separated from the first region, a first region and a second region. A field effect type device comprising a gate electrode provided on the surface via a gate insulating film, and controlling a current flowing between the first region and the second region by a gate voltage applied to the gate electrode. In the transistor, the main component of the current is a zener carrier that flows between a valence band and a conduction band inside a depletion layer on the surface of the first region formed by the gate voltage. 2. The first region is a second diffusion layer of a first conductivity type, which is provided in the first diffusion layer of a first dielectric type and has a higher concentration than that of the first diffusion layer. The semiconductor device according to claim 1, wherein the semiconductor device is present. 3. The semiconductor device according to claim 2, wherein the second region is a third diffusion layer of a second conductivity type different from the first conductivity type.