JPH0680800B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a complementary MOSF.
It is about ET.

[Outline] The present invention is a P-well type CMOS circuit for converting a CMOS circuit pattern designed by the P-well type and an N-well type CMOS circuit pattern into each other without changing the respective pattern sizes and characteristics. Circuit pattern N channel MO
Thicker gate oxide film of SFET and thinner gate of P-channel MOSFET, or thinner gate oxide film of N-channel MOSFET and thicker gate oxide film of P-channel MOSFET of N-well type CMOS circuit pattern Is.

[Prior Art] In a complementary semiconductor circuit, a well is usually used for electrical isolation of elements.

A substrate of either P-type or N-type is used to perform deep diffusion of the opposite conductivity type to form a well.

An important issue is whether to use the N-type substrate for the P-well type or the P-type substrate for the N-well type.

It is necessary to think comprehensively which to select, but it is necessary to prioritize the characteristics of N channel or P channel, to reduce the overall chip size, or to install a special device. It is decided in consideration of whether there is.

The P-well CMOS has a simpler manufacturing process than the N-well CMOS, and can be said to be a well-established process with abundant industrial experience.

[Problems to be Solved] When a well is formed in a substrate, the surface concentration of the well becomes higher than the surface concentration of the substrate. Further, the current characteristics of the MOSFET are better when the surface concentration is lower, because the mobility of electrons or holes becomes smaller as the impurities become higher.

Further, the mobility of electrons is usually higher than that of holes, given the same impurity concentration. Therefore, forming the P-well on the N-type substrate provides a better balance between the N-channel and the P-channel than forming the N-well on the P-type substrate. Considering this point, the P-well method is easier to use. . However, the N-well method is adopted especially when the characteristics of the N-channel MOSFET are desired to be improved and used, or when a special device such as EPROM is mounted. Whether the P-well system or the N-well system is adopted, a normal circuit can be constructed by adopting either one, as long as it is designed according to the load for driving the dimension of the transistor.

However, there are cases where it is desired to combine a circuit designed with a P well and a circuit designed with an N well into one chip. For example, a P-well computer and N
This is a case where peripheral CMOS EPROMs composed of wells are integrated into one chip. In such a case, since the P-well method and the N-well method are used, it is impossible to synthesize them as they are.

If the transistor designed in the P-well system is changed to the N-well system, μ increases for the N-channel MOSFET and conversely decreases for the P-channel MOSFET. To correct this, the W / L ratio must be changed. However, in order to change W, it is necessary to change the size of the transistor itself, which is a big work because it requires a total design change.

[Means for Solving the Problem] By making the gate oxide film of the N-channel MOSFET thicker and the gate oxide film of the P-channel side thinner,
P-well CMOS circuit pattern is replaced by N-well CMOS
Allow the circuit to change without changing the size and characteristics of the transistor.

[Operation] The characteristics of the MOSFET can be evaluated by the drain current _ID .
The drain current _ID is represented by the equation (1).

The drain current I _D is the coefficient of the equation (1). Can be evaluated by It can be expressed as.

Εox is the dielectric constant of the gate insulating film Tox is the gate insulating film thickness V _{G is the} gate voltage, v _{D is the} drain voltage v _{T is the} threshold voltage, μ is the mobility W is the gate width, and L is the gate length.

When the transistor designed in the P-well system is changed to the N-well system, if the size of the transistor is not changed, that is, the gate width W is not changed and only the gate length L is corrected, the gate of the P-channel transistor is used. There are methods of shortening the length and increasing the gate length of the N-channel transistor, but there is a limit to this.

If the gate length is too short, punch through becomes a problem,
If it is too long, the gap between the adjacent gate electrode patterns becomes narrow and patterning becomes difficult.

In order to solve this, the present invention is to change the Tox in the equation (1) to obtain the I _D value in the P well. That is, in this case, the P-channel transistor side
This is achieved by making Tox thinner than the N channel side.

[Embodiment] FIG. 2 shows only a simplified element of a P-well type CMOS circuit pattern. P well 6 in N type substrate 1
Forming an N-channel MOSFET in the well,
A P-MOSFET is provided in the N substrate 1.

The CMOS circuit shown in FIG. 1 is obtained by converting the P-well type CMOS circuit pattern into the N-well type. Here, by simplifying the combination of complicated CMOS circuits,
Only the elements of the circuit are shown. The gate oxide film thickness of each transistor in the N-well CMOS circuit is changed in order to achieve almost the same characteristics (same β) as those of the transistors forming the P-well CMOS circuit of FIG. .

The gate oxide film thickness of the N-MOSFET in FIG.
By making it thicker than that of SFET, the N-MO of Fig. 2
We were able to realize β that is almost the same as SFET.

On the other hand, by making the gate oxide film thickness of the P-MOSFET of FIG. 1 thinner than that of the P-MOSFET of FIG. 2, it was possible to realize the same β as that of the P-MOSFET of FIG.
In this way, by making the gate oxide film thickness of the N-channel MOSFET thicker and the gate oxide film thickness of the P-channel MASFET thinner, the CMOS designed by the P-well method is formed.
The circuit can be easily changed to an N-well type CMOS circuit. It is needless to say that the present invention can be implemented even in the case where P and N are reversed in this embodiment.

[Effect of the Invention] By independently setting the gate oxide film thicknesses on the N-channel side and the P-channel side, a circuit designed by a P-well CMOS circuit can be manufactured by an N-well CMOS circuit process. The characteristics can be obtained with the same size and almost the same as the circuit designed by the P-well method without causing the problems of punch-through and patterning.

[Brief description of drawings]

FIG. 1 shows an N-well system converted by the method of the present invention.
It is a figure which shows one element of a CMOS circuit. FIG. 2 is a diagram showing one element of a P-well type CMOS circuit converted by the method of the present invention. 1 ... N-type substrate, 2 ... P-type substrate 3 ... Source region, 4 ... Gate polysilicon 5 ... Drain region, 6 ... P well 7 ... N well, 8 ... Gate oxide film

Claims (1)

[Claims] 1. A CM having a circuit pattern designed by a P-well method.
When converting the OS semiconductor device to the N-well type, N
When the CMOS semiconductor device whose circuit pattern is designed by the N well method is converted into the P well method by making it thicker than the gate oxide film of the channel MOSFET and thinner than the gate oxide film of the P channel MOSFET. By making the gate oxide film thinner and the gate oxide film of the P-channel MOSFET thicker, the P-well type CMOS semiconductor device and the N-well type CMOS semiconductor device are mutually converted without converting the circuit pattern. A method of manufacturing a semiconductor device characterized by the above.