JPH0684961A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To form a gate electrode having excellent uniformity of a threshold voltage, a fine gate length and a low resistance by selectively dry etching a GaAs layer at the time of forming a recess. CONSTITUTION:A high-purity GaAs layer 1, an N-type AlGaAs layer 2, an N<+> type GaAs layer 3 and ohmic electrodes 4 are formed on a semi-insulating GaAs substrate. An insulating film 5 is formed on an entire wafer. The film 5 is coated with polymethacrylate 6, exposed to an electron beam or an ion beam to form a gate opening. The gate opening of the film 5 is formed by dry etching. A gate opening of the layer 3 is opened by selective dry etching. Gate material is vapor-deposited on the film 5 and the gate opening, a pattern of an upper part of a mushroom type gate electrode is formed, and the unnecessary gate metal on the insulating film is removed. Thus, the fine gate electrode having a low resistance is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor using a heterojunction, and more particularly to a method for manufacturing a highly uniform field effect transistor having a low resistance electrode.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor (hereinafter referred to as FET) using a heterojunction of GaAs and AlGaAs is an FET (MESFE) using only GaAs.
T) It is considered as a device having higher speed and higher performance than T), and its application to low noise devices and high speed ICs is being studied.

For example, HE using a junction of undoped GaAs having a high electron affinity and AlGaAs having a low electron affinity containing N-type impurities as shown in FIG.
MT or MODFET has excellent high frequency characteristics and is also applied to IC (GaAs IC Symposium Technical Digest 1984 125)
Section). In order to improve the performance of an IC using such an element, the uniformity of the threshold voltage and the miniaturization of the gate electrode,
Low resistance is important.

Such an FET is manufactured by the following steps with respect to the uniformity of threshold voltage. Figure 4
(A) to (d) are sectional views of the device, and the steps will be described.

High-purity GaAs on a high-resistance GaAs substrate
Layer 1, N type Al _0.3 Ga _0.7 As layer 2, N ⁺ type GaAs
Form layer 3. Here, the N ⁺ type GaAs layer 3 is a cap layer for reducing the source resistance. First, element isolation is performed by mesa or ion implantation. Next, the ohmic electrodes 4 forming the source and the drain are formed with a predetermined interval. Subsequently, as shown in FIG. 4B, an optical resist 11 having an opening and covering the ohmic electrode 4 is formed at a desired position in a so-called channel region between the ohmic electrodes 4. Next, as shown in FIG. 4C, the N ⁺ type GaA is used with the optical resist 11 as a mask.
A recess (so-called recess region) is formed in the s layer 3 with GaAs and Al.
The N ⁺ -type GaAs layer 3 which is the cap layer is selectively etched by a reactive etching gas having a selectivity of GaAs (for example, a mixed gas of CCl ₂ F ₂ and He). After that, a gate electrode material such as Al is deposited by a well-known vacuum deposition method, and as shown in FIG. 4D, a lift-off method is applied to selectively form the Schottky gate electrode 12 in the recess. Obtain the formed recess gate structure.

Further, as a method for forming a fine gate electrode, exposure using an electron beam is known, and as a method for forming a gate electrode having a low resistance, Japanese Patent Publication No. 61-773.
The "pattern forming method" described in Japanese Patent Publication No. 70 is known. The "pattern forming method" described in the above publication is shown in FIG.
A description will be given using (a) to (c).

First, as shown in FIG. 5A, a low-sensitivity positive resist 14 is applied on the GaAs substrate 13, and then a high-sensitivity positive resist 15 is applied on the low-sensitivity positive resist 14. And then exposed by electron beam. Next, development is performed to obtain a mushroom type (T type) resist pattern. Next, as shown in FIG. 5B, the gate metal 9 is deposited. Next, as shown in FIG. 5C, by removing the low-sensitivity positive resist 14, the high-sensitivity positive resist 15, and the gate metal 9 using an organic solvent, the mushroom type (T Type) gate electrode 10 is formed.

[0008]

It is difficult to apply the selective dry etching to the recess formation by using the method of forming the mushroom type (T type) gate electrode described above. Since the PMMA (polymethylmethacrylate) -based resist used as a resist for electron beam exposure has no dry etching resistance, the mushroom-shaped (T-shaped) resist shape cannot be maintained. Particularly, the lower layer resist portion of the mushroom type (T type) is thinned by the dry etching, and the lift-off of the gate metal cannot be performed. Further, since the gate length is determined by the opening width of the lower layer resist, the thickness of the lower layer resist cannot be made thicker than necessary.

An object of the present invention is to overcome the performance limitations of the prior art as described above, to form a fine gate electrode with low resistance, and to manufacture a field effect transistor excellent in threshold voltage uniformity. Is provided.

[0010]

In order to achieve the above object, the present invention provides a high-purity GaAs layer serving as a channel layer and an N-type AlGaAs layer serving as a carrier supply layer on a semi-insulating GaAs substrate. N ^{+ as the} ohmic cap layer
In the case where an ohmic electrode is formed on a wafer on which a type GaAs layer is formed, a step of forming an insulating film on the entire surface of the wafer including the ohmic electrode, and coating PMMA (polymethylmethacrylate) on the insulating film. , A step of forming a gate opening by exposing with an electron beam or an ion beam, a step of opening the gate opening of the insulating film by dry etching, and a step of selectively dry etching the gate opening of the N ⁺ type GaAs layer. A step of forming an opening, a step of depositing a gate metal on the insulating film and the gate opening, a pattern of an upper portion of a mushroom type gate electrode, and a step of removing unnecessary gate metal on the insulating film. Is provided.

In order to achieve the above object, the present invention provides a high-purity GaAs layer as a channel layer and an N-type AlGaA as a carrier supply layer on a semi-insulating GaAs substrate.
s layer and N ⁺ type GaAs to be the ohmic cap layer
A step of forming an insulating film on the entire surface of the wafer including the ohmic electrode, in which an ohmic electrode is formed on the wafer having a layer formed thereon; and PMMA on the insulating film.
(Polymethylmethacrylate) is applied and exposed with an electron beam or an ion beam to form a gate opening, a step of opening the gate opening of the insulating film by dry etching, and a step of forming the N ⁺ -type GaAs layer. A step of opening the gate opening by selective dry etching; a step of forming a pattern on the upper part of the mushroom type gate electrode using an optical resist; and Ti / Al vapor deposition,
And a step of forming a mushroom type gate electrode by a lift-off method.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 and FIG. 2 are process sectional views of one embodiment of the present invention.

As shown in FIG. 1A, semi-insulating GaA
A high-purity GaAs layer 1 serving as a channel layer is formed on the s substrate.
μm, impurity concentration of the carrier supply layer 2 × 10 ¹⁸ cm
^-3 of Si-doped N-type AlGaAs layer 2 is formed to 300 angstroms, and Si-doped N ⁺ -type GaAs layer 3 having an impurity concentration of 3 × 10 ¹⁹ cm ^-3 is sequentially formed to 500 angstroms as an ohmic cap layer. Using the wafer thus formed, B as element isolation
⁺ Is ion-implanted at 30 keV and 1 × 10 ¹³ cm ⁻² to form the ohmic electrode 4 using AuGe / Ni.

Next, as shown in FIG. 1 (b), SiO ₂
An insulating film 5 made of is formed on the entire surface of the 1000 angstrom wafer. Next, a resist PMM for electron beam exposure
A6 is applied to 2000 angstrom, and the gate portion is exposed and developed to form an opening [FIG. 1 (c)]. Next, FIG.
As shown in (d), CF ₄ gas is used to dry-etch 7 the insulating film 5 in the gate portion to form an opening. Table 1 shows the etching rates of SiO ₂ and PMMA when dry etching 7 is performed with CF ₄ gas.

[0016]

[Table 1]

At this time, the PMMA 6 is also etched, but this is not a problem because the gate portion of the insulating film 5 is opened. Next, the N ⁺ -type GaAs layer 3 in the gate portion is covered with CCl.
Selective dry etching using ₂ F ₂ + He gas 8
Then, a recess is formed [FIG. 1 (e)]. CCl ₂ F ₂
Table 2 shows the etching rates of GaAs, SiO ₂ , and PMMA when selective dry etching 8 was performed for 10 minutes using + He gas.

[0018]

[Table 2]

In this case, the insulating film 5 can serve as a dry etching mask. Next, as shown in FIG. 2A, WSi, which is the gate metal 9, is vapor-deposited by a sputtering method, the gate metal 9 is embedded in the gate opening, and the mushroom type (T type) gate electrode 10 [FIG. b)] is formed.

Next, an optical resist is used to form a pattern on the upper part of the mushroom type (T type) gate electrode 10 [FIG. 2 (b)], and an unnecessary gate metal on the insulating film 5 is formed by using SF ₆ gas. 9 is removed, and an upper portion of the mushroom type gate electrode 10 is formed as shown in FIG.

By the above method, the selective dry etching 8 can be used, and the mushroom type (T
(Type) gate electrode 10 was formed, and a field effect transistor could be formed.

In this embodiment, the insulating film 5 is made of S
Although iO ₂ is used, the same can be realized by using a SiN film or SiON which serves as a mask for the dry etching 7 using CCl ₂ F ₂ + He gas.

FIGS. 1 and 3 are process sectional views of another embodiment of the present invention.

As shown in FIG. 1A, semi-insulating GaA
A high-purity GaAs layer 1 serving as a channel layer is formed on the s substrate.
μm, impurity concentration of the carrier supply layer 2 × 10 ¹⁸ cm
^-3 of Si-doped N-type AlGaAs layer 2 is formed to 300 angstroms, and Si-doped N ⁺ -type GaAs layer 3 having an impurity concentration of 3 × 10 ¹⁹ cm ^-3 is sequentially formed to 500 angstroms as an ohmic cap layer. Using the wafer thus formed, B as element isolation
⁺ Is ion-implanted at 30 keV and 1 × 10 ¹³ cm ⁻² to form the ohmic electrode 4 using AuGe / Ni.

Next, as shown in FIG. 1 (b), SiO ₂
An insulating film 5 made of is formed on the entire surface of the 500 Å wafer. Next, resist PMMA for electron beam exposure
6 is applied to 5000 Å, and the gate portion is exposed and developed to form an opening [FIG. 1 (c)]. Next, FIG.
As shown in (d), CF ₄ gas is used to dry-etch 7 the insulating film 5 in the gate portion to form an opening. At this time,
The PMMA 6 is also etched, but this does not cause a problem because the gate portion of the insulating film 5 is opened. Next, the N ⁺ -type GaAs layer 3 of the gate portion is selectively dry-etched 8 by using CCl ₂ F ₂ + He gas to form a recess [FIG. 1 (e)]. In this case, the insulating film 5 can serve as a dry etching mask. Next, using the optical resist 11, a mushroom type (T type) gate electrode 10 [FIG.
3 (b)] is formed [FIG. 3 (a)], Ti / Al is vapor-deposited, and a mushroom type (T type) gate electrode 10 is formed by a lift-off method as shown in FIG. 3 (b). To do.

By the method as described above, the selective dry etching 8 can be used, and further, the field effect transistor having the mushroom type gate electrode 10 can be formed.

[0027]

As described above, according to the present invention,
Since the GaAs layer can be selectively dry-etched during the recess formation, the threshold voltage is excellent in uniformity, and a gate electrode with a fine gate length and low resistance can be formed, thus realizing a high-performance field-effect transistor. The effect of being able to be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a partial process cross-sectional view of one embodiment and another embodiment of the present invention.

FIG. 2 is a process sectional view of the remaining portion of the embodiment of the present invention.

FIG. 3 is a process sectional view of a remaining portion of another embodiment of the present invention.

FIG. 4 is a process sectional view for explaining a conventional example.

FIG. 5 is a diagram showing a conventional pattern forming method.

[Explanation of symbols]

1 High-purity GaAs layer 2 N-type AlGaAs layer 3 N ⁺ -type GaAs layer 4 Ohmic electrode 5 Insulating film 6 PMMA 7 Dry etching 8 Selective dry etching 9 Gate metal 10 Gate electrode 11 Optical resist

Claims (2)

[Claims] 1. A high-purity GaAs layer that serves as a channel layer and an N-type A that serves as a carrier supply layer on a semi-insulating GaAs substrate.
In the case where an ohmic electrode is formed on a wafer formed by forming an 1 GaAs layer and an N ⁺ -type GaAs layer serving as an ohmic cap layer, a step of forming an insulating film on the entire surface of the wafer including the ohmic electrode; a step PMMA (polymethyl methacrylate) was coated on film, exposed with an electron beam or ion beam, which is open forming a gate opening, the gate opening in the insulating film by dry etching, the N ⁺ Forming a gate opening of the type GaAs layer by selective dry etching, depositing a gate metal on the insulating film and the gate opening, and forming a pattern on a mushroom type gate electrode. And a step of removing unnecessary gate metal on the insulating film. Method. 2. A high-purity GaAs layer that becomes a channel layer and an N-type A that becomes a carrier supply layer on a semi-insulating GaAs substrate.
In the case where an ohmic electrode is formed on a wafer formed by forming an 1 GaAs layer and an N ⁺ -type GaAs layer serving as an ohmic cap layer, a step of forming an insulating film on the entire surface of the wafer including the ohmic electrode; a step PMMA (polymethyl methacrylate) was coated on film, exposed with an electron beam or ion beam, which is open forming a gate opening, the gate opening in the insulating film by dry etching, the N ⁺ -Type GaAs layer gate opening by selective dry etching, using optical resist to form a pattern on the upper part of the mushroom-type gate electrode, and vapor-depositing Ti / Al and using the lift-off method to mushroom-type A method of manufacturing a field effect transistor, including the step of forming a gate electrode. Law.