JPH069239B2 - Solid-state imaging device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a solid-state imaging device, and more specifically, to a solid-state imaging device capable of controlling the value of γ by a substrate bias and having excellent weak light detection sensitivity. It is provided.
It can be applied not only from home video cameras to television cameras for broadcasting stations, but also to video cameras for astronomical observation and still cameras that utilize high sensitivity.

[Conventional technology]

Static Induction Phototra
nsistor; hereinafter referred to as SIPT. 2D solid-state image pickup devices of the gate accumulation type using various types of structures have been proposed and prototyped. Among them, the one having a structure in which all the three main electrodes of the SIPT forming the pixel are connected to either the address line or the signal reading line can form the pixel by the SIPT excellent in the weak light detection sensitivity. FIG. 4 shows an example of a cross-sectional structure of a pixel having this structure.

The conventional technique will be described with reference to FIG. The SIPT having the structure shown in FIG. 4 can operate with either of the n ⁺ regions 41 and 42 as the source, but in the following description, an erecting operation with 41 as the source will be described as an example.

FIG. 4 shows the cross-sectional structure of one pixel, but one pixel has one S
It consists of an IPT and a gate cabinet. SIPT
Is an n-channel SI with n ⁺ region 41 as a source, n ⁺ region 42 as a drain, p ⁺ region 43 as a gate, and n ⁻ region 44 as a channel.
It is PT. On the p ⁺ gate 43, a transparent insulator 43 'such as SiO ₂ and a transparent electrode 48 such as polysilicon are used to form an M
An OS capacitor is formed and serves as the above-mentioned gate capacitor. This SIPT is an n ⁺ region 42 on a p-type Si substrate 45.
After the formation of the, n ^- the region 44 n ^- made layer by epitaxial growth. A region 410 is a region for pixel separation and separates adjacent pixels. In this example, the U groove formed by etching is oxidized to form a SiO ₂ film, and then polysilicon is devoked to form it.

The drain 42 embedded in the substrate is shared by the pixels in the direction perpendicular to the paper surface. A p ⁺ region 45 ″ separates this buried drain 42. In this example, the buried drain 42 has an electrode 42 ′ taken from the substrate surface by the n ⁺ region 42 ″. 42 'is a high conductivity material such as Al-Si, which reduces the resistance of the buried drain (embedded line). The source region 41 is an electrode 49 made of polysilicon or the like.
Is connected to the source line orthogonal to the drain 42. S
The gate 43 of the IPT is connected to the gate address line through the gate capacitor. The electrode of the MOS capacitor on the gate 43 is connected to the gate address line with the same material 48. 48 'is a high conductivity material such as Al-Si, which lowers the resistance of the gate address line.
The gate address line is formed so as to be orthogonal to the signal read line (either the embedded line or the source line).

[Problems to be solved by the invention]

The two-dimensional solid-state imaging device configured as described above is a SIP
Utilizing the features of T such as low noise, high photosensitivity, and high speed, T had excellent features such as high sensitivity and high sensitivity for detecting weak light. As a method of changing the value of γ, which is one of the photoelectric conversion characteristics of the two-dimensional solid-state imaging device, there is a method of changing the value of the pulse applied to the gate address line at the gate address and the value at the gate refresh. This method, however, has a practical problem because the read circuit is complicated in that the read circuit is integrated on the same chip.

[Means for solving problems]

In order to solve the above problems, the present invention provides a structure in which the value of γ can be changed by the bias voltage of the substrate.

The operating principle of the solid-state imaging device of the present invention will be described with reference to FIG.

FIG. 2 (a) shows a schematic structure of a cross section of SIPT that constitutes one pixel. FIG. 2 (b) shows the band diagrams along AA 'and BB' in FIG. 2 (a) in an overlapping manner. The erecting operation will be described below. SIPT source n ⁺ region 21,
An n-channel SIPT in which the n ⁺ region 22 is the drain, the p ⁺ region 23 is the gate, and the n ⁻ region 24 is the channel region, and is formed on the p ⁺ / p ⁻ substrate (25 is p ⁻ , 26 is p ⁺ ) There is. Where p ⁺
Regions 23 are depicted separately but are electrically connected to each other. Similarly, the n ⁺ regions 22 are electrically connected to each other. The n ⁺ region 22 is not only the drain of the n-channel SIPT, but also the gate of a p-channel static induction transistor (hereinafter referred to as p-channel SIT) having the p ⁺ region 23 as the source and the p ⁺ substrate 26 as the drain. Formed to work. That is, the channel between n ⁺ regions 22
28 is depleted by the diffusion potential of the n ⁺ region 22, and the potential height thereof is electrostatically controlled by the potentials of the n ⁺ region 22 and the p ⁺ substrate 26.

The time from the reading of one pixel to the next reading is called the light integration time. During this light integration time, the potential V _SL of the source 21 and the potential V _{BL of the} drain 22 are 0, and the p ⁺ gate 23 is at a potential higher than the built-in potential given in the thermal equilibrium state by the gate refresh, that is, a negative potential. p ⁺ substrate 26 has a negative bias V
^sub is applied. The potential band structure diagram along the lines AA 'and BB' at this time is shown in FIG. 2 (b).
become that way. In the figure, E _CX (X = S, G, G ^* , D, D ^* , sub) indicates the energy potential of the conduction band at x, and E _VX indicates the energy level of the valence band. s is the source 21, G is the gate 23, G ^* is the lowest potential in channel 27, D is the drain 22 and D ^* is the highest potential in channel 28. Light with energy hν enters the pixel from the surface and is larger than the forbidden band energy of hν.
When carriers are excited in the channel 24 by this light, electrons (● in the figure) of the carriers flow to the drain 22 due to the strong electric field in the channel, and holes, ○ in the figure flow to the gate 23. Since the gate 23 is separated from the outside by the gate capacitor C _G , holes due to photoexcitation are directly stored in the p ⁺ gate 23, and the potential of the gate is lowered. In the conventional structure, the holes accumulated in the p ⁺ gate are retained in the gate by a high potential barrier, but in the structure of the present invention, the potential of the channel 28 is higher than that of the n ⁺ region 22. It's getting low. The holes in p ⁺ gate 23 therefore flow through channel 28 to p ⁺ substrate 26.

Although the amount of holes flowing to the p ⁺ substrate 26 is controlled by the potential of the channel 28, this potential is also controlled by the potential of the p ⁺ substrate 26 as described above.

By changing the bias voltage V _sub to the p ⁺ substrate 26,
The potential height of the channel 28 with respect to the holes is controlled, and the accumulation of holes by the photoexcitation in the p ⁺ gate 23 is controlled. The difference in the accumulation of holes in the p ⁺ gate 23 appears as the difference in the value of γ in the photoelectric conversion characteristic. Therefore, the value of γ is controlled by the substrate bias.

In the above description, the case where the n-channel SIPT operates upright has been described, but the energy band diagram at the optical integration time is also shown in FIG. 2 during the inverted operation using the n ⁺ region 21 as the drain and the n ⁺ region 22 as the source. The operation is the same as in (b).

FIG. 3 shows the circuit structure of the above-mentioned one pixel.
It becomes like (a) and (b). (a) shows the time when the SIPT is in the upright motion, and (b) shows the time when it is in the upright motion. SIPT31
And a gate capacitor 32 and a p-channel SIT 33. The explanation starts from (a). 34 is the source of SIPT31, 35 is the drain of SIPT31 and the gate of SIT33, and 36 is the gate of SIPT31 and the source of SIT33. 37 is a drain of SIT, which is a substrate. 36 is connected to the gate terminal 38 through the gate capacitor 32. In (b), 34 'is the drain of SIPT31 and 35' is SIP.
It is the source of T31 and the gate of SIT32.

FIG. 2 (c) shows a schematic view of a cross section of one pixel having another structure of the present invention. (d) is (c) and shows a band diagram along the line indicated by CC ′. Similarly, the erecting operation will be described below.

The static induction phototransistor (SIPT) is shown in Fig. 2 (a).
Similarly, the n ⁺ region 21 is the source, the n region 22 'is the drain,
n with p ⁺ region 23 as the gate and n ⁻ region 24 as the channel region
In channel SIPT, p ⁺ / p ^- Si substrate (25 p ^-, 26 is
p ⁺ ) is formed on. The p ⁺ regions 23 are electrically connected to each other. The n region 22 'is not only the drain of the n-channel SIPT, but also the p ⁺ region 23 is the emitter and the p ⁺ substrate.
It is formed so as to serve as the base of a pnp bipolar transistor (hereinafter referred to as BPT) having 26 as a collector. That is, the thickness of the n ⁻ region and the impurity density are properly designed.

During the light integration time, the potential V _{SL of the} source 21 and the potential V _{BL of the} drain 22 may be considered to be 0, and the p ⁺ gate 23 has a potential higher than the built-in potential between the source and the gate immediately after the gate refresh. A negative bias V _sub is applied to the p ⁺ substrate 26. The band diagram along the line C-C 'at this time is as shown in (d). When light of energy hν is incident on the pixel from the surface and carriers are excited in the channel 24 by this light, electrons of the carriers, ● in the figure, flow to the drain 22 ′ due to the strong electric field in the channel, The hole, ○ in the figure, flows to the gate 23. The gate 23 is a gate capacitor C
Since it is separated from the outside by _G , holes due to photoexcitation are accumulated in the p ⁺ gate 23 as they are, and the potential of the gate is lowered. The holes accumulated in the p ⁺ gate are retained in the gate by the high potential barrier. The potential of the gate becomes lower when the holes excited by light are accumulated in the p ⁺ gate 23.
It is indicated by a one-dot chain line in FIG. When the potential of the gate 23 decreases to some extent, the holes in the gate flow into the n region 22 'having a low potential for the holes. The amount of these holes flowing is controlled by the change in the width of the neutral region of the n base region 22 'due to the bias of the p ⁺ substrate. Therefore, as described above, the bias voltage V _sub of the p ⁺ substrate 26
Controls the accumulation of holes in the p ⁺ gate 23 by photoexcitation, and the value of γ is controlled by the substrate bias.

Although the case where the n-channel SIPT is in the upright operation has been described above, the same applies to the case of the upright operation.

When the structure of one pixel described above is surfaced in terms of a circuit,
It becomes like (c) and (d). (c) shows the SIPT in the upright motion, and (d) shows the inverted motion. SIPT31
And a gate capacitor 32 and a BPT 33 '.
In (c), 34 is the source of SIPT31, 35 is the drain of SIPT31 and the base of BPT33 ', and 36 is the gate of SIPT31 and the emitter of BPT33'. 37 is BP
The collector of T, which is the substrate. 36 is the gate capacitor 32
Through the gate terminal 38. 34 'in (d)
Is the drain of SIPT37, 35 'is the source of SIPT31 and the base of BPT33'.

[Action]

The solid-state imaging layer device according to the present invention is composed of pixels whose γ value can be controlled by the substrate bias without sacrificing the characteristics such as low noise, high photosensitivity, and high speed that the electrostatic induction phototransistor originally has. . It is very useful that the γ value can be controlled only by changing the substrate bias in terms of practical use such as integrating the read circuit on the same chip.

〔Example〕

An embodiment of the solid-state imaging device of the present invention is shown in FIG. The case of using a Si substrate will be described, but this may of course be another semiconductor.

FIG. 1 shows a sectional structure of one pixel. One pixel is composed of an n-channel SIPT, a gate capacitor and a p-channel SIT.

First, FIG. 1 (a) will be described. Hereinafter, the SIPT is upright operation. The SIPT is formed with the n ⁺ region 1 as the source, the n ⁺ region 2 as the drain, the p ⁺ region 3 as the gate, and the n ⁻ region 4 as the channel region. Although the n ⁺ region 2 is drawn separately in the figure, it is electrically common. Further, in the drain region 2, an electrode 2'is taken from the surface of the substrate by the n ⁺ region 2 ". The electrode 2'may be made of a material having high conductivity such as Al-Si. The drain region 2 is perpendicular to the plane of the paper. The pixel 2 is common to adjacent pixels in this direction and serves as a buried line. The electrode 2'also plays a role of reducing the electric resistance of this buried line. Separated by p ⁺ 5 ". The SIPT has p ⁺ / p ^- Si substrate (5 p ^+, 6 is p ^-)
After n ⁺ regions 2 and p ⁺ region 5 'was formed by ion implantation above the channel region 4 n ^-. The layers are made by epitaxial growth further n ⁺ region 2 source p ⁺ region 3, p It is formed so as to act as the gate of the p-channel SIT whose drain is the ⁺ substrate 5. As described above, the value of γ is controlled by the bias voltage to the p ⁺ substrate 5.

The source 1 of the SIPT has an electrode 9 taken by a transparent electrode material such as polysilicon and is led to a source line.
The p ⁺ gate 3 is a gate capacitor in which a MOS capacitor is formed by a transparent insulator 3 ′ such as SiO ₂ and a transparent substance 8 such as polysilicon. Further, the transparent substance 8 is guided to the gate address run-in.
8'is a high conductivity material such as Al-Si, which reduces the resistance of the gate address line. A region 10 is a region for pixel separation, and separates adjacent pixels. The region 10 is formed by oxidizing the U groove formed by etching to form a SiO ₂ film and then depositing non-doped polysilicon. The device surface is protected by a transparent film 7 such as SiO ₂ or PSG.

When light enters the pixel from the surface, that is, from above, and carriers are excited in the channel 4, holes are accumulated in the p ⁺ gate 3 by the strong electric field in the channel. n ⁺
Reference numeral 2 is the gate of the p-channel SIT, but the potential for holes between n ⁺ 2 is electrostatically controlled by the potential of the p ⁺ substrate 5. Therefore, the hole of p ⁺ gate 3 is
It flows to the p ⁺ substrate 5 through the gap of the n ⁺ region. Therefore, as described above, the value of γ can be controlled by the bias to the substrate.

In the following description of another embodiment, the regions having the same numbers as in (a) have the same functions as those described in (a).

FIG. 1 (b) shows another embodiment. The difference from the embodiment shown in (a) is that the n ⁺ region 2 ″ is not connected to the n ⁺ region 2. Even in this case, the p channel SIT of the p ⁺ region 3 hole for the light integration time is also changed. potential height of the channel is controlled by the potential of the p ⁺ substrate 5. during further reading, electrons injected from the source 1 of SIPT flows to the n ⁺ region 2 "from the n ⁺ region 2. That is, the n ⁺ region 2 ″ can also operate in the same manner as the embodiment of (a) in the embodiment of FIG. 1 (b) which is not connected to the n ⁺ region 2.

FIG. 1 (c) shows another embodiment. The difference from the embodiment shown in (a) p ⁺ / p ^- in that is made on the p-type substrate 5 'rather than the Si substrate. In this example, a depletion layer is formed by the diffusion potential of the p substrate 5'and the n ⁺ region 2, and the same operation as that of the embodiment of FIG. 1 (a) is performed.

FIG. 1 (d) shows another embodiment. As in (b), n ⁺ region 2 is
Although it is not connected to the n ⁺ region 2 ″, the operation mechanism is the same as in (a).

FIG. 1 (e) shows another embodiment. In this embodiment, the n ⁺ region is not provided inside with a punching-through portion, but the n ⁺ region 2 is not in contact with the isolation region 5 ″. The hole of the p ⁺ gate 3 is the n ⁺ region. 2 and pixel separation area 10
And n ⁺ region 2 to flow to p ⁺ 5 ″. That is, a channel is formed between the pixel isolation region 10 and n ⁺ region 2, and the potential height of this channel for holes is n ^+.
It is electrostatically induced and controlled by the potential of the region 2 and the potential of the p ⁺ substrate. Therefore, even in the embodiment of FIG. 1 (e) in which part of the n ⁺ region 2 is not punched through, the value of γ is controlled by the bias to the substrate.

FIG. 1 (f) shows another embodiment. In the structure shown in (e), n ⁺
In the region 2, the electrode is not separated by the n ⁺ region 2 ″, but in this example, the same operation as (e) can be performed as in (b).

FIG. 1 (g) shows another embodiment. This is a structure in which the structure shown in (e) is formed on the p substrate 5 ', and the effect of the substrate bias is small, but the same operation as in (e) can be performed.

FIG. 1 (h) shows another embodiment. This is a structure in which the structure shown in (f) is formed on the p substrate 5 ', and the effect of the substrate bias is small, but the same operation as in (f) can be performed.

FIG. 1 (i) shows another embodiment. This is obtained by replacing the pixel isolation region 10 of the structure shown in (a) with the p ⁺ region 11, and the operation is the same as that of the embodiment shown in (a).

FIG. 1 (j) shows another embodiment. This is the structure shown in (i), in which the electrode of n ⁺ region 2 is not taken by n ² region 2 ″, and the same operation as (i) can be performed as in (b). Then, the hole between the p ⁺ gate 3 and the n ⁺ region 2 and the n ⁺ region 2 ″ can be used as a channel.

FIGS. 1 (k) and 1 (l) show other embodiments, but these are the structures shown in (i) and (j), respectively, formed on a p substrate, and the same operation is possible. .

1 (m) and (n) show another embodiment, which are respectively
The pixel isolation region 10 having the structure shown in (f) and (h) is replaced with the p ⁺ region 11, and the same operation can be performed.

FIG. 1 (o) shows another embodiment. The difference from the embodiment shown in (a) is the n region 2. The n region 2 is formed so as to serve as the base of the BPT having the p ⁺ region 3 as an emitter and p ⁺ 5 as a collector. As described above, the holes of the p ⁺ gate 3 pass through the n region 2 to the p ⁺ substrate 5, but the flow of these holes can be controlled by the bias voltage of the p ⁺ substrate 5, and thus the value of γ can be controlled by the substrate. It can be changed by bias.

FIG. 1 (p) shows another embodiment. This is the structure shown in (o), where the n region 2 has no electrode formed by the n ⁺ region 2 ″, and the same operation as in (o) can be performed.

FIGS. 1 (q) and 1 (r) show another embodiment. These are devices (o) and (p) fabricated on a p-type substrate 5 ', respectively. It is made so that the width of the n region 2 can be changed, and operates similarly to (o) and (p).

FIGS. 1 (s) and 1 (t) show other embodiments, which are obtained by replacing the pixel isolation region 10 of the structure shown in (o) and (q) with the p ⁺ region 11, respectively. Are the same as (o) and (q), respectively.

In the embodiment described above, only a single channel is used, but a multi channel may be used. In addition, the conductivity type may be opposite in all regions.

Next, the operation method of this solid-state imaging device will be described by citing an example of a circuit configuration method. The circuit can be operated by the conventional circuit configuration and reading method except that the value of γ can be controlled by the substrate bias.

First, the configuration of the two-dimensional solid-state imaging device will be described with reference to FIG. The p-channel SIT is omitted.

One C _ij of n × m pixels arranged in a two-dimensional matrix is composed of one erect operation SIPT and a gate capacitor. The source of the SIPT of the pixel C _ij is the signal read line SL _i , and the drain is the embedded line BL _j .
The gate is connected to the vertical address line GL _j through a gate capacitor. B _i and BL _j are parallel and orthogonal to SL _i . Signal readout line SL _i is grounded through the reset transistor Q _R, a gate of Q _R are all made to a common reset pulse phi _R is applied. Further, SL _i is connected to the switch transistor Q _S through the transfer transistor Q _T. The gates of Q _T are all made common and a transfer pulse φ _T is applied. Q _T and
Q Suitable Kyapata C _T to the connection portion of the _S is provided, Q _S is grounded further by all Q _S in common to an appropriate load resistance R _L, the load resistor is connected to all the Q _S The point becomes the output terminal V _out . The gate of the switched lunch stannous Q _S him Shirubebi the horizontal shift register 52, a read pulse phi _S is applied. The buried line BL _j is connected to the power supply V _DD through the buried line selection transistor Q _B. The gate of Q _B is connected to the vertical address line GL _j , GL _j is guided to the vertical shift register 51, and the vertical address pulse φ _Gj is applied.

FIG. 5 (b) shows a timing chart of the read pulse.

The vertical shift register has vertical adrel pulses φ G ₁ , ... φ _Gm
Are sequentially output, and in FIG. 5 (b), exactly φ _Gj and the subsequent φ _Gj +1 are shown.

At time t ₁ , the transfer pulse φ _T enters and the transfer transistor Q _T becomes conductive, then time t ₂
Reset pulse φ _R causes reset transistor Q
Signal readout lines through _R becomes the ground potential along with the C _T. At time t ₃ , the vertical address pulse φ _Gj is input, and each pixel C _lj , ..., C _nj on the vertical address line GL _j charges C _T according to the amount of incident light. Φ at the same time as φ _T at time t _4
Gj is cut off, and the optical information of C _lj , ..., C _nj is stored in C _T corresponding to each. After φ _T has expired, the horizontal shift register generates a read pulse φ _S1 , ..., φ _Sn to sequentially turn on the switch transistor Q _S to discharge the electric charge stored in C _T through R _L , C _ij , The output of C _nj is sequentially output as a potential change of V _out . Thus, when the horizontal one-line optical information of C _1j , ..., C _nj is output by time t ₈ , the same procedure is repeated to read the optical information of C _{1J + 1} , ..., C _{nj + 1} next. Be done.

In FIG. 5 (a), all of Q _R , Q _T , Q _B , and Q _S are shown as MOS transistors, but it is not necessary that they are all MOS transistors, and SIT, bipolar transistor, JFET are not required. And so on.

〔The invention's effect〕

In the solid-state imaging device of the present invention, a part of the n ⁺ buried drain is punched through, and the easiness of hole accumulation by photoexcitation to the p ⁺ gate of SIPT is controlled by the bias of the p ⁺ substrate. The value of γ of the photoelectric conversion characteristic is controlled. Therefore, the low noise that SIPT originally has,
It is possible to provide a solid-state imaging device that can easily control the value of γ in addition to characteristics such as high photosensitivity and high speed.

FIG. 6 is a diagram showing the effect of the invention, and FIG. 1 (n) shows an example of photoelectric conversion characteristics when the device having the structure is operated by the method shown in FIG. The size of one pixel is 85μ × 65
μ, with two channels. Power supply voltage V _DD = 2V,
Load resistance R _L = 1 kΩ, optical integration time T _LI = 10 ms, wavelength 65
It irradiates 5 nm (red) light, and the horizontal axis shows the incident light intensity P
_i [μw / cm ² ], the vertical axis represents ΔV _out [mV] below the output voltage V _{ont in} the dark state. It is clearly understood that γ can be changed from 0.42 to 5.7 by changing the substrate bias V _sub from OV to −5V. In other words, it is shown that the amount of holes accumulated in the p ⁺ gate of SIPS (the channel of p channel SIT) is controlled by the substrate bias. This means that by increasing the γ value in the region where the amount of incident light is weak, the weak light sensitivity is reduced, but the contrast of the image is enhanced, and when there is strong incident light, holes that cannot be fully accumulated in the p ⁺ gate are effectively escaped. You can also do it. That is, it is possible to suppress blooming caused by the generated carriers flowing out to the adjacent pixels when there is strong incident light.

[Brief description of drawings]

1 (a) to (t) are diagrams showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the present invention, (a) is a schematic diagram of a cross-sectional structure of one pixel, (b) is its band diagram, (c) is a schematic diagram of a cross-sectional structure of one pixel of another structure, (d) is its band diagram,
Fig. 3 shows an equivalent circuit of one pixel. (A) shows the upright operation of SIPT, (b) shows the upright operation, (c) and (d) have different structures, and (c) shows the SIPT. Is an upright operation (d) is a diagram showing an equivalent circuit in an inverted operation, FIG. 4 is a diagram for explaining a conventional technique, FIG. 5 is a diagram showing an example of a sectional view of a conventional structure, and FIG. 6A and 6B are diagrams for explaining an example of an operating method, FIG. 6A is a circuit configuration method, FIG. 6B is a diagram showing a timing chart of a read pulse, and FIG. 6 is a diagram for explaining the effect of the present invention. 5, 6 ... p ⁺ / p ^- _Si substrate, 5 '... p type Si substrate, 2 ... n ⁺ type buried layer (one of the main electrodes of SIPT), 2 ... n type buried layer (one of the SIPT main electrodes) ) 3 ... SIPT p ⁺ type gate region, 3 '... MOS capacitor insulator, 8 ... MO
Electrode of S capacitor

Claims (9)

[Claims] 1. A drain region is a buried layer of the second conductivity type formed on a substrate of the first conductivity type, and a surface is formed so as to sandwich a low impurity density region of the first conductivity type with respect to the drain region. The first high-impurity-density region of the second conductivity type provided as a source region, and the second high-impurity-density region of the first conductivity type provided so as to surround the source region as a gate region, And an electrostatic induction transistor having the low impurity density region as a channel, and an insulating film provided on the second high impurity density region and a region for separating the individual electrostatic induction transistors. In the solid-state imaging device, the second high impurity density region serves as a source region, the buried layer serves as a gate region, the substrate serves as a drain region, and at least a part of the buried layer serves as a second region. A solid-state imaging device having an electrostatic induction transistor as a channel region, including means for applying a desired voltage to the substrate, and controlling carriers flowing from the second high impurity density region to the substrate. . 2. The solid-state imaging device according to claim 1, wherein the second channel region is formed immediately below the second high impurity density region. 3. The solid-state imaging device according to claim 1, wherein the second channel region is formed between the embedded region and the isolation region. 4. The solid-state image pickup device according to claim 1, wherein the second channel region is a buried layer having a second conductivity type and a low impurity density. 5. The two-layer structure of the first conductivity type substrate having a high impurity density and the first conductivity type low impurity density region formed on the substrate. The solid-state imaging device according to any one of claims 1 to 4. 6. A third high impurity density region of the second conductivity type is provided in at least a part between the isolation region and the second high impurity density region. The solid-state imaging device according to any one of items 1 to 5. 7. The solid-state imaging device according to claim 6, wherein the third high impurity density region is in contact with the embedded region. 8. The solid-state imaging device according to claim 1, wherein the isolation region is an insulating layer. 9. The solid according to any one of claims 1 to 7, wherein the isolation region is a fourth high impurity density region of the first conductivity type. Imaging device.