JPH0697461A - Multifunctional semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] A multifunctional semiconductor device having three vertically stacked channels 12, 14, 16 under a gate electrode 17 is provided. The channels 12, 14, 16 are formed on the wide bandgap buffer layer 11, each channel is coupled to a source / drain electrode 21-26, and these electrodes are connected to the gate electrode 17. It is formed so that it faces each other on both sides. Channel 1 at the top
6 is separated and separated from the gate electrode 17 by a cap layer 18 of wide bandgap semiconductor material. The channels 12, 14, 16 are separated from each other by wide bandgap barrier layers 13, 15.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to semiconductor devices, and more particularly to field effect transistors having a plurality of vertically aligned channels.

[0002]

BACKGROUND OF THE INVENTION Heterostructure devices based on compound semiconductors are expected to offer significant speed and power advantages over silicon devices. Most compound semiconductor-based HFET designs aim to copy most silicon-based structures using compound semiconductor materials. One drawback of this approach is that it does not take full advantage of the beneficial properties of compound semiconductor materials, and that the minimum feature size of the device is not improved over silicon-based ones. As a result, gallium arsenide devices are not much smaller than silicon-based devices and are not cost competitive with conventional CMOS technology. What is needed is a truly compact and high performance complementary heterojunction field effect transistor structure using compound semiconductor materials.

[0003]

Prior art binary logic circuits are based on transistors having one output that is either off or on. Many transistors must be interconnected to provide circuits that perform basic and complex logic functions. The cost of the integrated circuit increases because a significant number of transistors are required for each logic function. Also, interconnecting many transistors is complex and time consuming, further increasing the cost of logic circuits. What is needed is a semiconductor device that provides multiple outputs and is capable of performing complex logical operations even with fewer added components.

[0004]

In summary, the advantages of the present invention are achieved by a multifunction semiconductor device having three vertically stacked channels below the gate electrode. The channels are formed in a wide bandgap buffer layer, each channel being coupled to a source electrode and a drain electrode, the electrodes being formed on opposite sides of a gate electrode. The top channel is separated and separated from the gate electrode by a cap layer of wide bandgap semiconductor material. The channels are separated from each other by a wide bandgap barrier layer.

[0005]

EXAMPLES The structure of the channel region below the gate electrode is a major issue in the design of quantum well field effect transistors because the performance of the channel region largely determines the performance of the entire device. FIG. 1 shows a very simplified sectional view of the channel region of a multifunctional field effect transistor according to the invention. All material layers shown in FIG. 1 as well as subsequent embodiments of the present invention are substantially single crystal epitaxial growth layers. For this purpose, each epitaxial layer must be composed of a material that is crystallographically compatible with the underlying substrate. Therefore, it should be noted that in addition to the electronic material constraints described below with respect to the individual embodiments, the choice of material is also limited by the properties of the crystal. The epitaxial layer of the present invention is a metal-organic vapor phase epitaxy method (MOCV).
D), molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), or the like.

The embodiment shown in FIG. 1 is formed on a supporting crystal substrate 10 and is made of aluminum antimonide (AlSb).
A wide band gap buffer layer 11 composed of a material such as Other wide bandgap materials are also known and used in compound semiconductor devices, but as will be seen below, the preferred embodiment is compatible with other materials used in each overlay layer. ALSb is desirable in order to secure the property.

The first N-type quantum well 12 is formed so as to cover the buffer layer 11. In the preferred embodiment, N-type quantum well 12 is about 5-10 nanometers thick and is constructed of a material such as indium arsenide (InAs). The first barrier layer 13 is formed on the N-type quantum well 12.
Barrier 13 is preferably constructed of a wide band gap material such as AlSb and is about 3 nanometers thick in the preferred embodiment.

The P-type quantum well 14 is composed of the AlSb barrier layer 13
Is formed so as to cover. In a preferred embodiment, P-type quantum well 14 has a thickness in the range of 5-10 nanometers,
It is composed of gallium antimonide (GaSb). This P-type quantum well is covered by a second barrier layer 15, which has a thickness of about 3 nm.
It is made of a material having a wide band gap such as AlSb.

The second N-type quantum well 16 includes the second barrier layer 15
Is formed so as to cover. In the preferred embodiment, N-type quantum well 16 is about 5-10 nanometers thick and is constructed of a material such as indium arsenide (InAs).
The cap layer 18 is formed on the second N-type quantum well 16. The third barrier 18 is also made of a wide band such as AlSb.
Composed of a gap material, about 10 in the preferred embodiment.
It has a thickness of nanometers.

The gate electrode 17 is formed on a portion of the cap 18 and makes a Schottky contact with the cap layer 18. P-type quantum well 14 and N-type quantum well 12,1
Note that 6 is substantially undoped and there is no need to place a charge supply layer in the barrier layer. The electrodes 21 and 26 are formed so as to face each other with the gate electrode 17 interposed therebetween, and can function as a source electrode or a drain electrode for the channel 12.
The electrodes 22 and 25 are formed so as to face each other with the gate electrode 17 sandwiched therebetween, and can function as a source electrode or a drain electrode for the channel 14. Electrode 2
3, 24 are formed so as to face each other with the gate electrode 17 sandwiched therebetween, and can function as a source electrode or a drain electrode for the channel 16. Electrodes 21-2
6 is comprised of surface portions 21a-26a, which are highly conductive and are used to interconnect the device to external or integrated circuits (not shown). Electrodes 21-26 are also formed by diffusing portions 21b-26b, which provide low resistance coupling to channels 12, 14, 16.

P-type quantum well 14 and N-type quantum well 1
Selecting a particular material for 2, 16 is shown in FIG.
~ As shown in Figure 5, self-doping (self-dopin
This is because it is desirable that the P-type quantum well 14 (?) has a larger valence band energy than the conduction band energy of the N-type quantum well 14 in order to provide g).

The conduction band energy (E _c ) and the valence band energy (E _v ) are represented by the band gaps of FIGS.
Shown in the diagram. In the bandgap diagram, the vertical axis represents the relative energy (electron volt),
The horizontal axis represents the thickness or depth of the device structure of FIG. The left side of the figure is the gate electrode side, and the right side is the substrate side.

P-type quantum well 14 and N-type quantum well 1
2, 16 are barriers 11, 13, 15 and cap layer 1
8 formed in a wide band gap host material. The quantization energy level of the first hole state (ε _h14 ) is shown by the line in the P-type quantum well 14. ε _h14 is in an energy state slightly lower than the valence band energy of the P-type quantum well 14. The exact energy of ε _h14 is determined by the thickness of P-type quantum well 14. ε _h is the minimum energy for holes in the P-type quantum well 14.

Similarly, ε _e12 and ε _e16 are N respectively.
2 shows the quantization energy level of the first electronic state in the quantum wells 12 and 16. ε _e12 and ε _e16 are N-type quantum wells 1
It is slightly above the conduction band energies of 2, 16 and is also determined by the thickness of the N-type quantum wells 12, 16. Δε
Is the energy difference between the bulk valence band energy in P-type quantum well 14 and the bulk conduction band energy in N-type quantum wells 12, 16. GaSb and InA
When s is used for the quantum well, Δε is about 0.175e.
It becomes V.

The thickness of the barriers 13 and 15 is the same as that of the N-type quantum well 1.
It is designed so that the electron wave function in 2, 16 and the hole wave function in the P-type quantum well 14 can overlap. That is, the barrier 13 is thin enough to allow charge carriers to couple the two quantum wells. ε _h14 is ε _e12
In the higher energy state, electrons in the valence band of the P-type quantum well 14 have a tendency to move toward the N-type quantum well 12. This produces many free electrons in the N-type quantum well 12 and the same number of free holes in the P-type quantum well 14. Thus, if ε _h14 is greater than ε _e12 , each quantum well will dope the other quantum well with charge carriers so that the quantum well becomes conductive. Also in FIG. 2, the negative gate bias is
It is _shown that ε _h14 is forced to be smaller than ε _e16 so that N-channel 16 is substantially _{depleted of} charge carriers and becomes non-conducting.

FIG. 3 shows a bandgap diagram with a positive gate bias applied to gate 17 (FIG. 1). When ε _h14 has a larger energy state than ε _e16 , the electrons in the valence band of the P-type quantum well 14 are
It has a tendency to move toward the N-type quantum well 16. This produces many free electrons in the N-type quantum well 16 and the same number of free holes in the P-type quantum well 14. Therefore, ε
_{If h14} is greater than ε _e16 , each quantum well will dope the other quantum well with charge carriers so that the quantum well becomes conductive. FIG. 3 also shows that a positive gate bias _forces ε _h14 to be less than ε _e12 , _causing N-channel 12 to be substantially _{depleted of} charge carriers and non-conducting. There is.

As shown in FIG. 4, in the absence of the bias applied by gate 17 (shown in FIG. 1), P-type quantum well 14 and N-type quantum wells 12 and 16 are both undoped and are non-conductive. . However, as shown in FIGS. 2 and 3, when biased, both P-type quantum well 14 and N-type quantum wells 12 and 16 are doped and become conductive. The important thing to note is that
The N-type quantum wells 12, 16 and the P-type quantum well 14 are self-doped with respect to each other, but the three channels remain electrically isolated. N channel 1
The charge conducted at 2 or 16 does not reach the P-channel 14. Barriers 13 and 15 maintain electrical isolation so that the P-type device operates independently of the N-type device.

As mentioned above, ε _e12 , ε _e16 and ε
_h14 changes depending on the thickness of the quantum well. As the P-type quantum well 14 becomes thinner, ε _h14 gradually _{moves away} from E _V. Similarly, as the quantum wells 12 and 16 become thinner,
ε _e12 and ε _e16 are increasingly separated from E _C. Utilizing this aspect of the self-doping structure shown in FIG. 1, an HFET structure having both depletion and enhancement characteristics can be made.

Note some features of the self-doping structure shown in FIG. First, self-doping is done simultaneously. That is, the N-channel and P-channel are simultaneously activated to the same extent by mobile charges. Secondly, a large amount of charge carriers move between the wells as a result of the nature of the materials used and the self-doping process,
If self-doping occurs, the concentration of charge carriers will be very high in each quantum well, and accordingly the conductivity will be high. In addition, quantum wells 12, 14, 16
Is substantially free of impurities, which makes it very close to its inherent mobility. Further, unlike the conventional doped quantum well, if epsilon _h14 is epsilon _e12 and epsilon _e16 smaller,
Charge carriers cannot simply be present in any of the quantum wells. This is because there is a forbidden band energy gap between ε _h14 , ε _e12 and ε _e16 . This bandgap energy gap is expected to produce surprisingly low leakage when the channel is in the non-conducting state.

FIG. 5 shows a first embodiment of a multifunctional field effect transistor structure according to the present invention. The simplified schematic of FIG. 5 shows how to combine the devices shown in FIG.
It shows whether each drain electrode provides a unique logic function. For simplicity and clarity of explanation, this circuit is shown as using a positive power supply V _DD . The logic circuit of FIG. 5 uses a negative voltage to indicate a logic "low" and a positive voltage of the same magnitude to indicate a logic "high", but a similar circuit operating with a single power supply. It is also possible to design

The input A is applied to the gate electrode 1 via the resistor 37.
It is connected to 7. Input B is coupled to gate electrode 17 via resistor 38. Therefore, the gate electrode 1
There are three potential states in 7: logic high when both inputs are high, logic low when both inputs are low, one logic high and another logic low. Is zero. The drain electrodes 24, 25, 26 are coupled to V _DD via resistors 34, 35, 36, respectively. The values of resistors 34, 35 and 36 are selected to make the currents in each channel approximately equal. Source electrodes 21,2
2, 23 are each directly connected to V _EE . V _EE is a power supply of opposite polarity to V _DD and has a magnitude determined by the particular application.

The first output, designated N1, is taken from the drain electrode 26. Output N1 is the first N (shown in FIG. 1)
It is controlled by the current flowing in the channel 12. A second output, designated N2, is taken from the drain electrode 24.
The output N2 is controlled by the current flowing in the second N channel 16 (shown in FIG. 1). A third, also called P1
The output is taken from the drain electrode 25 and is controlled by the current flowing in the P channel 14.

The logic low on gate electrode 17 results in N channel 16 turning off and P channel 14 and N channel 12 conducting. Gate electrode 17 taking a logic high results in N-channel 16 and P-channel 14 being conductive and N-channel 12 being non-conductive. The zero potential of gate electrode 17 results in all three channels being non-conducting. Table 1 is a truth table showing the resulting function of the single device circuit shown in FIG.

[0024]

Table 1 A B N1 (OR) P1 (XOR) N2 (NAND) Low Low Low Low High Low High High High High High Low Low High High High High High High Low Low Low It is clear that the device provides three useful logic functions, significantly reducing the number of active devices required to perform complex logic functions. Also, since the three channels of the multifunctional transistor according to the present invention are electrically independent, it is possible to interconnect these three logic functions to provide other logic functions.

FIG. 6 illustrates another useful embodiment of the present invention which implements the minimum device shape of complementary logic structures. In this example, P-channel 14 (shown in FIG. 1)
Are used only for doping the N channels 12 and 16. Source electrode 21 is coupled to a positive power supply (shown as V ⁺ ). Drain electrode 26 is coupled to drain electrode 24 and output 38. Source electrode 2
3 is coupled to ground potential or negative power supply.

During operation, when the gate electrode 17 takes a logic high, the N-channel 16 becomes conductive resulting in a logic low appearing at the output 38. Similarly, when the gate electrode 17 takes a logic low, the N-channel 12 becomes conductive, resulting in a logic high appearing at the output 38. Thus, the embodiment shown in FIG. 6 provides a complementary inverter using a single multifunction device according to the present invention. Similar to CMOS devices, only the circuit shown in FIG. 6 consumes significant power during switching. However, unlike conventional CMOS devices, faster switching is expected, and the mobility of the materials used is higher than that of conventional CMOS devices.

The embodiment shown in FIG. 6 previously used a single HFET.
It is shown that a pair of coupled complementary HFET devices can be formed using the structure according to the invention in the space required for the device. drain/
Source electrodes are selectively formed in contact with the drain / source regions and can be used to interconnect devices. Alternatively, each device may be internally coupled without the use of electrodes, as is often done in conventional integrated circuits.

By now it should be appreciated that a self-doped multifunctional semiconductor device with improved performance is provided. The multifunctional device according to the present invention makes excellent materials
It allows optimal use in FET technology and enables efficient geometries for high packing densities. The HFET according to the present invention also provides a P-type device and an N-type voltage coupled in a way that has heretofore been impossible, making it less complex than previously possible, simple circuitry and complex. Allows you to perform logical functions.

[Brief description of drawings]

FIG. 1 shows, in a very simplified manner, a sectional view of a part of a multifunctional semiconductor device according to the invention.

FIG. 2 FIG. 1 with a first gate bias applied.
2 shows a band diagram of the structure of FIG.

FIG. 3 FIG. 1 with a second gate bias applied.
Shows a band diagram of the structure of.

FIG. 4 FIG. 1 without gate bias applied.
Shows a band diagram of the structure of.

FIG. 5 shows a first embodiment of a complementary field effect transistor according to the invention.

FIG. 6 shows a second embodiment of a multifunctional transistor according to the present invention.

[Explanation of symbols]

 10 Crystal Substrate 11 Buffer Layer 12 First N-type Quantum Well 13 First Barrier Layer 14 P-type Quantum Well 15 Second Barrier Layer 16 Second N-type Quantum Well 17 Gate Electrode 17 18 Cap Layer 21, 22, 23 Source Electrode 24, 25 , 26 Drain electrodes 34, 35, 36, 37, 38 Resistance

Front Page Continuation (72) Inventor X Theodore Zoo, N Congress Drive 1351, Chandler, Arizona, USA

Claims (4)

[Claims] 1. A multi-function semiconductor device, said device comprising: a multi-layer semiconductor substrate (10-1) having an upper surface.
6, 18); a gate electrode (17) formed on the upper surface; a first channel (16) under the gate electrode (17), a first coupled to the first channel (16) A first field effect transistor (FET) having a source electrode (23) and a first drain electrode (24) coupled to the first channel, the first channel (16) being the gate electrode (17). ) And separated and separated, said first drain electrode (24)
And the first source electrode (23) is formed oppositely on both sides of the gate electrode (17).
A field effect transistor (FET); a second channel (14) below the first channel (16), a second source electrode (22) coupled to the second channel (14),
And a second FET having a second drain electrode (25) coupled to the second channel (14), the second channel (14) being below the first channel (16) and separated. A second FET, which is separated from each other, and the second drain electrode (25) and the second source electrode (22) are opposed to each other across the gate electrode (17); and the second channel. A third channel (12) under (14), said third channel (1
A third FET having a third source electrode (21) coupled to 2) and a third drain electrode (26) coupled to the third channel (12), wherein the third channel (12) is Under the second channel (14) and separated and separated, the third drain electrode (2
6) and the third source electrode (21) are formed opposite to each other with the gate electrode (17) interposed therebetween, and the first channel (16) has a first energy (E _e1 ). Has a first quantized electronic state, the third channel (12) has a first quantized electronic state with energy E _e2, and the second channel (14) has a first quantized positive state with ε _h. With a hole state, E _e1 > ε _h and E _e2 > ε when a zero bias is applied to the gate electrode.
Multifunctional semiconductor devices, characterized in that it is constituted by: first 3FET, characterized in that the _h. 2. E _e1 <ε _h and E _e2 > ε _h when a predetermined positive bias is applied to the gate electrode (17).
The multifunctional semiconductor device according to claim 1, wherein: 3. E _e1 > ε _h and E _e2 <ε _h when a predetermined negative bias is applied to the gate electrode (17).
The multifunctional semiconductor device according to claim 2, wherein 4. A multifunctional semiconductor device, said device comprising: a substrate (10) on which a laminated semiconductor device can be formed; a wide bandgap buffer layer (11) covering said substrate; said buffer layer. A first conductivity type first channel region (12) formed on a portion of (11); a first covering the first channel (12).
Barrier layer (13); second conductivity type second channel region (14) covering the first barrier layer (13); the second
A second barrier layer (15) covering the channel (14); a third channel region (16) of the first conductivity type covering the second barrier layer (15); the third channel (16)
Wide bandgap cap layer (1
8); the first, second and third channels (12,1)
4, 16) and is formed on the cap layer (1
8) A gate electrode (17) separated from the third channel (16) by the first, second and third channels (12, 14, 16), respectively. 17) a gate electrode (17) having a first end on one side and a second end on the other side of the gate electrode (17); the first channel (1)
2) a first source electrode (2) coupled to the first end of
1); a first drain electrode (26) coupled to the second end of the first channel (12); a second source electrode (26) coupled to the first end of the second channel (14). 22); a second drain electrode (25) coupled to the second end of the second channel (14); a third source electrode (25) coupled to the first end of the third channel (16). 23); and the second of the third channel (16)
A multifunctional semiconductor device comprising a third drain electrode (24) coupled to an end.