JPH0697694B2 - Complementary thin film transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a complementary thin film transistor including a non-single crystal silicon film.

<Prior Art> In recent years, research on a technique for forming a thin film transistor on an insulating substrate has been actively conducted. This technology is based on an active matrix panel that realizes a high-quality thin display using an inexpensive transparent insulating substrate, a three-dimensional integrated circuit that forms active elements such as transistors on a normal semiconductor integrated circuit, or an inexpensive and high-performance integrated circuit. Many applications such as high-performance image sensors or high-density memory are expected.

Some of these applications basically use a thin film transistor only as a switching element, but it is desirable that a driving circuit necessary for the switching is simultaneously composed of a thin film transistor. For example, in an active matrix panel, a thin film transistor is arranged in each of the pixels arranged in a matrix to switch display data. At the same time, if the peripheral drive circuit can be integrated with the thin film transistor, the mounting load is reduced and The cost and size of the entire system can be reduced. That is, it is necessary to form a logic circuit with thin film transistors.

In this case, a complementary structure (CMOS) is required more than in the case of a normal semiconductor integrated circuit. This is because, when a logic circuit is composed of thin film transistors, the number of elements is generally large, and power consumption becomes extremely large unless a complementary structure is used. For example, when the peripheral drive circuit of the active matrix panel is built with thin film transistors, the number of shift registers and buffers according to the number of pixels,
Alternatively, an analog switch or the like is required. In general
It must have a shift register of 500 stages or more. Further, it can be easily inferred that a large number of elements are required in the case of a three-dimensional integrated circuit, an image sensor, a high density memory, or the like. When the number of elements is large as described above, it is extremely effective to make the thin film transistors have a complementary structure in order to reduce the power consumption. The complementary thin film transistor is composed of a P-channel thin film transistor and an N-channel thin film transistor. Since one of these thin film transistors is always in the off state, a through current does not flow between the power supplies, and the power consumption can be significantly reduced.

However, the complementary thin film transistor has the following drawbacks, and thus far has not been sufficiently studied.

(1) The manufacturing method is complicated because both the P-channel type and the N-channel type are integrated.

(2) Along with this, the manufacturing cost is high.

(3) The characteristics of the thin film transistor should be well balanced.

(4) It is difficult to match the characteristics of the P-channel type thin film transistor and the characteristics of the N-channel type thin film transistor.

(5) An extra step such as adding an appropriate impurity to the channel portion is required in order to have these characteristics.

Due to these drawbacks, complementary thin film transistors have not reached the level of realization.

<Object of the Invention> The present invention is to eliminate such drawbacks at once.
The object of the invention is to provide a complementary thin film transistor which is composed of P-channel type and N-channel type thin film transistors each having excellent characteristics and a small difference in characteristics.
It is to provide it at a low cost by a simple manufacturing method.

<Summary of the Invention> The present invention provides a complementary thin film transistor including a first conductive type thin film transistor and a second conductive type thin film transistor formed on a substrate, wherein the channel regions of the first and second conductive type thin film transistors are formed of non-similar layers. It is formed of a single crystal silicon film, and the silicon film thickness of each channel region of the first and second conductivity type thin film transistors is formed to be thinner than any of the maximum widths of the depletion layer that can spread in each thin film transistor. Characterize.

Example Hereinafter, a complementary thin film transistor characterized in that a channel region is formed of a non-doped silicon thin film and a P-channel type or an N-channel type thin film transistor is realized depending on the conductivity type of source / drain will be described in detail based on examples. explain.

FIG. 1 is a sectional view showing the structure of a complementary thin film transistor according to the present invention. 101 is an insulating substrate such as a semiconductor integrated circuit substrate including glass, quartz, and a passivation film,
A P-channel type thin film transistor 102 and an N-channel type thin film transistor 103 are formed on it to form a complementary type thin film transistor. 104 is a channel region of a P-channel type thin film transistor made of a non-doped silicon thin film. Reference numeral 105 denotes a source region made of a P-type silicon thin film doped with an acceptor such as boron.
Reference numeral 6 is a similarly configured drain region. 107 is a gate insulating film such as SiO ₂ , 108 is a gate electrode such as another crystalline silicon or metal, and 109 is an interlayer insulating film such as SiO ₂ . 110,1
11 is made of a conductor such as metal, and is a source electrode,
It is a drain electrode. 112 is a channel region of an N-channel type thin film transistor made of a non-doped silicon thin film. Reference numeral 113 is a source region made of an N-type silicon thin film doped with a donor such as phosphorus or arsenic, and 114 is a similarly configured drain region. 115 is a gate insulating film, 1
16 is a gate electrode, 117 is a source electrode, and 118 is a drain electrode.

As is clear from this figure, the present invention is of P-channel type and N-type.
A major feature is that both non-doped silicon thin films are used as the channel region of the channel type thin film transistor, and basically, the P channel type thin film transistor and the N channel type thin film transistor are distinguished only by the conductivity type of the source / drain regions. I am trying.

Hereinafter, the effects of the present invention realized by these features will be described.

First, the effect of using non-doped silicon thin films as the channel regions of P-channel and N-channel thin film transistors will be described. By using a non-doped silicon thin film, that is, a silicon thin film close to an intrinsic semiconductor, as the channel regions of both types of thin film transistors, it is possible to minimize the leak current (hereinafter referred to as OFF current) flowing when the transistor is in the off state. It will be possible. In a normal transistor using single crystal silicon, a P-type substrate for N-channel type and an N-type substrate for P-channel type are used to form an extremely good PN junction to reduce OFF current between source and drain. Although it has been reduced, it is generally impossible to single-crystallize a silicon thin film on an insulating substrate, resulting in a polycrystalline state or an amorphous state, and a good PN junction cannot be formed, thus reducing the OFF current. I can't let you do it. FIG. 2 is data of an experiment conducted by the present applicant and is a graph showing the relationship between the impurity concentration in the silicon thin film in the channel region of the N-channel thin film transistor and the OFF current. The impurity is boron, which is intended to make the channel region P-type. Doping is by ion implantation,
The horizontal axis of the graph is the boron dose amount, and the vertical axis is the OFF current at a gate voltage of 0V. As can be seen from this graph, the OFF current becomes minimum when the dose amount is 0, that is, when a non-doped silicon thin film close to an intrinsic semiconductor is used. This is because the leak current of the PN junction increases as the impurity concentration increases. On the contrary, when the channel region is N-type, it goes without saying that the transistor becomes a depletion type and the OFF current increases. Therefore, it turns off when a non-doped silicon thin film is used.
The current is minimal. That is, in order to reduce the OFF current, it is effective to increase the resistance value of the channel region as much as possible rather than using a PN junction like a transistor using single crystal silicon. Although the above description has been made for the N-channel thin film transistor, the same holds true for the P-channel thin film transistor. Therefore, in both types of thin film transistors, the OFF current can be minimized by using the non-doped silicon thin film in the channel region.

Next, the effect of distinguishing the P-channel type thin film transistor from the N-channel type thin film transistor only by the conductivity type of the source / drain regions will be described. Thereby, the manufacturing process of the complementary thin film transistor can be significantly simplified. Therefore, it is possible to significantly improve the yield and reduce the cost. FIG. 3 is a diagram showing an example of a method of manufacturing the complementary thin film transistor shown in FIG. First, as shown in FIG. 3A, non-doped silicon thin films 302 and 303 are deposited on an insulating substrate 301, and then a desired pattern is formed. A P-channel thin film transistor is formed at 302 and an N-channel thin film transistor is formed at 303. Next, as shown in FIG. 3B, the gate insulating film 304 is formed by thermally oxidizing the non-doped silicon thin films 302 and 303. Alternatively, the gate insulating film may be externally deposited by a vapor phase growth method or the like. Then, the gate electrode 305 is deposited to form a desired pattern. Of course, different gate electrode materials may be used for the P-channel thin film transistor and the N-channel thin film transistor, such as the P-type silicon thin film and the N-type silicon thin film. Next, as shown in FIG. 3C, a mask material 306 such as photoresist is formed in a region to be an N-channel type thin film transistor, and an acceptor element 307 such as boron is ion-implanted in the P-channel type thin film transistor. Doping is performed to form a P-type silicon thin film to be the source region 308 and the drain region 309. Further, as shown in FIG. 3 (d), a mask material 310 such as photoresist is similarly formed in a region to be a P-channel type thin film transistor, and a donor element 31 such as phosphorus or arsenic is formed.
1 is doped into the N-channel type thin film transistor by the ion implantation method to form the source region 312 and the drain region 313.
Then, an N-type silicon thin film is formed. Finally, as shown in FIG. 3 (e), after depositing an interlayer insulating film 314, a contact hole is opened to form a source electrode 315 and a drain electrode 316 of a P-channel thin film transistor, a source electrode 317 and a drain of an N-channel thin film transistor. The electrode 318 is formed, and the complementary thin film transistor is completed.

As can be seen, the complementary thin film transistor according to the present invention can be manufactured by a very simple method. This is because both the P-channel type thin film transistor and the N-channel type thin film transistor use a non-doped silicon thin film as a channel region. Therefore, it is not necessary to use an N-type substrate for the P-channel transistor and a P-type substrate for the N-channel transistor, unlike the conventional complementary transistor. That is, it is not necessary to change the conductivity type of the channel region in the two types of transistors. This makes it possible to omit the step of adding impurities to the channel regions of the respective transistors and forming a pattern required for the impurities. In addition, each transistor is separated into islands on the insulating substrate, and no special element separation process is required. Further, along with this, there is no parasitic MOS effect as in a normal semiconductor integrated circuit, and it is not necessary to form a channel stopper. For these reasons, in the thin film transistor according to the present invention, P-channel type and N-channel type thin film transistors can be realized only by changing the conductivity type of the source / drain regions. Therefore, the manufacturing process thereof is extremely simple as compared with the conventional complementary transistor. For example, the number of pattern forming steps is 10 or more in the conventional complementary transistor, but only 6 in the complementary transistor according to the present invention.
The process is enough. The fact that the manufacturing process can be simplified in this way has a great effect that the manufacturing cost can be reduced and the manufacturing yield can be improved, and a significantly low cost can be achieved as a whole.

Further, according to the present invention, the silicon thin films in the channel regions of both the P-channel type thin film transistor and the N-channel type thin film transistor are formed in the same layer, and the thickness of the silicon thin film is the same as the silicon thin film surface of the two types of thin film transistors. The present invention also provides a complementary thin film transistor characterized by being thinner than the maximum width of any depletion layer that can be formed, which will be described in detail below based on examples.

FIG. 4 is a cross-sectional view showing the vicinity of the channel region of the complementary thin film transistor according to the present invention. FIG. 4A shows a P-channel type thin film transistor, and FIG. 4B shows an N-channel type thin film transistor. Insulation board 40
A thin film transistor having source regions 402 and 408, drain regions 403 and 409, gate insulating films 404 and 410, and gate electrodes 405 and 411 is formed on 1. The non-doped silicon thin films 406 and 412 in the channel region are composed of the same layer and therefore have the same film thickness tsi. The depletion layers 407 and 413 spread on the surface of the silicon thin film as the gate voltage is applied. The width x _P of the depletion layer in the P-channel type thin film transistor and the width x _N of the depletion layer in the N-channel type thin film transistor are respectively expressed by the following equations. Given in.

Where q is the unit charge amount, ε is the dielectric constant of the silicon thin film,
φs is the amount of bending of the energy band on the surface of the silicon thin film, N _D is the trap density equivalently acting as a donor, and N _A is the trap density equivalently acting as an acceptor. As described above, the silicon thin film is in a polycrystalline or amorphous state and has many crystal defects, which act as traps. In the energy band diagram, the trap forming a level between the Fermi level and the conduction band acts as a donor, and the trap forming a level between the Fermi level and the Valence band acts as an acceptor. The level of each trap is determined by the arrangement of silicon atoms, and in general, N _D and N _A are not equal. In Figure 4, N _D is larger than N _A , so x _P
Shows that is smaller than x _N. When the gate voltage is further increased, the spread width of each depletion layer reaches the maximum value, and the inversion layer starts to be formed on the surface of the silicon thin film. The gate voltage at this time is the threshold voltage, and even if the gate voltage is further increased, the depletion layer does not spread anymore, and the carrier density in the inversion layer only increases. P
Maximum width of depletion layer in channel type and N channel type thin film transistors x _P max and x _N max, threshold voltage V th _P and
Vth _N is given by the following equation.

Where φf _P and φf _N are the Fermi energies of P-channel and N-channel thin film transistors, Cox, respectively.
Is the capacitance of the gate insulating film per unit area, and V _FB is the flat band voltage.

In the complementary thin film transistor according to the present invention, the silicon thin film tsi is configured to be smaller than any of the above x _P max and x _N max.

Hereinafter, the effect of the present invention realized by this will be described.

When the thickness (tsi) of the silicon thin film is smaller than the maximum width (x _P max, x _N max) that the depletion layer can spread, the depletion layer cannot spread beyond tsi. Therefore, the depletion layer width is ts
Immediately after reaching i, an inversion layer is formed on the surface of the silicon thin film. That is, the threshold voltage of the transistor is reduced. Normally, since the silicon thin film has extremely high density of traps, the threshold voltage becomes high. However, according to the present invention, the driving voltage of the thin film transistor is lowered by reducing the threshold voltage. Further, the current (ON current) flowing when the transistor is on can be increased. Therefore, the thin film transistor can be easily used and can operate at higher speed.

The threshold voltage at this time is given by the following equation.

In the case of the example in FIG. 4, N _D > N _A and x _P <x _N. Therefore, when tsi is reduced, the threshold voltage of the N-channel thin film transistor starts to decrease earlier than that of the P-channel thin film transistor. However, when tsi is further reduced to fall within the film thickness range provided by the present invention, the difference in threshold voltage between the P-channel thin film transistor and the N-channel thin film transistor becomes small. This is shown in FIG. The horizontal axis is tsi, and the vertical axis is the absolute value of the threshold voltage. 501 is an N-channel thin film transistor, and 502 is a P-channel thin film transistor. As can be seen from this graph, in the region where tsi is smaller than x _P max, the threshold voltages of the two approaches rapidly. This is because in the above equation, N _D is larger than N _A , and thus the tsi dependence of the threshold voltages of the two transistors is different. Therefore, according to the present invention, it becomes possible to bring the threshold voltages of the P-channel type and N-channel type thin film transistors close to each other and reduce the characteristic difference. This has a very large effect in complementary transistors.

Although the above explanation was made assuming N _D > N _A , N _A <
The same is true for N _D.

FIG. 6 shows another embodiment of the present invention. A P-channel type thin film transistor 616 and an N-channel type thin film transistor 617 are formed on an insulating substrate 601, and form a complementary type thin film transistor. 602 is a gate electrode, 603
Is a gate insulating layer. Reference numeral 604 is a channel region of a P-channel type thin film transistor made of a non-doped silicon thin film. 605 is P doped with an acceptor such as boron
606 is a source region made of a silicon thin film, and 606 is a similarly constructed drain region. Reference numeral 607 is an interlayer insulating film, 608 is a source electrode, and 609 is a drain electrode. 61
Reference numeral 0 is a gate electrode, and 611 is a channel region of an N-channel thin film transistor made of a non-doped silicon thin film. Reference numeral 612 is a source region made of an N-type silicon thin film doped with a donor such as phosphorus or arsenic, and 613 is a drain region similarly configured. 614 is a source electrode, 615
Is a drain electrode.

As is apparent from the figure, all the effects of the present invention described above are also established in this embodiment. That is, the channel region is located above the gate electrode, or the source
Even if the silicon thin film in the drain region is composed of a layer different from the silicon thin film in the channel region or the incidental structure is changed, the present invention can be established and the same effect can be obtained.

<Summary of Effects of Examples> As described above, the examples have the following effects.

(1) Since the non-doped silicon thin film is used in the channel region, the OFF current of the thin film transistor can be minimized.

(2) Since a non-doped silicon thin film is used for the channel region, P only depends on the conductivity type of the source / drain regions.
A channel type thin film transistor and an N channel type thin film transistor can be produced separately, and a complementary type thin film transistor can be realized very easily.

(3) Since the thickness of the silicon thin film is smaller than the maximum width in which the depletion layer can spread, the threshold voltage of the thin film transistor can be lowered and the ON current can be increased to enable a higher speed operation. .

(4) Since the thickness of the silicon thin film is smaller than both the maximum width of the depletion layer of the P-channel thin film transistor and the maximum width of the depletion layer of the N-channel thin film transistor, the characteristics of both thin film transistors are It is possible to significantly improve and reduce the difference between the two characteristics.

<Effects of the Invention> As described above, the present invention relates to a complementary thin film transistor including a first conductive type thin film transistor and a second conductive type thin film transistor formed on a substrate, wherein: The channel regions are formed of non-single-crystal silicon films of the same layer, and the silicon film thickness of each of the channel regions of the first and second conductivity type thin film transistors is larger than the maximum width of the depletion layer that can spread in each thin film transistor. By adopting the thin structure, the following remarkable effects can be achieved.

(1) Since the non-single crystal silicon film has poorer quality than the single crystal silicon film, it has a characteristic that a sufficient ON current cannot be obtained and a leak current is generated even when the transistor is OFF. By forming the film thickness of the channel region thinner than the maximum width in which the depletion layer can spread as in the present invention, the threshold voltage of the transistor can be lowered, the ON current can be increased, and at the same time, the transistor Since the channel resistance can be increased, the OFF current can be reduced.

(2) Since the silicon film thickness of each channel region is formed thinner than any of the maximum widths of the depletion layers that can spread in each thin film transistor, the characteristics of both complementary thin film transistors are significantly improved and It is possible to reduce the difference in characteristics.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment showing the structure of a complementary thin film transistor according to the present invention. FIG. 2 is a graph showing the relationship between the impurity concentration in the channel region and the OFF current. 3 (a) to 3 (e) are views showing a method of manufacturing the complementary thin film transistor according to the present invention shown in FIG. FIGS. 4A and 4B are views showing the vicinity of the channel region of the thin film transistor according to the present invention. FIG. 5 is a graph showing the relationship between the thickness of the silicon thin film in the channel region and the threshold voltage. FIG. 6 is a diagram showing a second embodiment showing the structure of a complementary thin film transistor according to the present invention.

Claims (1)

[Claims] 1. A complementary thin film transistor comprising a first conductive type thin film transistor and a second conductive type thin film transistor formed on a substrate, wherein the channel regions of the first and second conductive type thin film transistors are non-single crystal silicon films of the same layer. And the silicon film thickness of each channel region of the first and second conductivity type thin film transistors is
A complementary thin film transistor, which is formed to be thinner than any of the maximum widths of a depletion layer that can spread in each thin film transistor.