JPS6110992B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a threshold value control method for MIS type semiconductor devices.

When configuring various logic circuits using MIS field effect transistors, their threshold voltage (Vth)
control may be required. For example, in a complementary MOS integrated circuit, it is ideal to set the threshold voltages of input signals "1" and "0" to 1/2 of the power supply voltage _VDD , and for this purpose, P-channel transistors This is a case where the absolute values of the threshold voltages Vth and N-channel transistors are made the same.

In order to set the threshold voltage of an MIS field effect transistor to a desired value, conventionally, a substrate material with a specific resistance that provides a predetermined threshold voltage has been selected, or When it is desired to change the threshold value of each element, the channel region of each element is doped with an appropriate amount of impurity using ion implantation or the like.

Particularly in the latter case, the manufacturing process becomes extremely complicated because it is necessary to cover the mask to elements other than those to which impurities are to be implanted.

The present invention is a novel invention that improves the conventional drawbacks as described above, and its purpose is to provide a manufacturing method that can easily control the threshold voltage of an MIS type semiconductor device.

In order to achieve the object, the present invention provides a threshold value of the MIS type semiconductor device by adjusting the thickness of the semiconductor layer in the process of forming an MIS type semiconductor device on a semiconductor layer grown on an insulating substrate. The present invention is characterized in that the voltage is controlled to a predetermined value, and the present invention will be further described in detail below.

When a MIS type semiconductor device is formed on a thin silicon (Si) growth layer epitaxially grown on an insulating substrate such as sapphire or spinel (hereinafter abbreviated as SOS structure), the threshold voltage Vth of the MIS type semiconductor device is , as shown in Figure 1, as the thickness of the silicon growth layer decreases, the threshold voltage decreases.
Vth shifts to the enhancement area. Note that FIG. 1 shows data when the silicon (Si) growth layer is not doped with impurities.

In addition, if the silicon (Si) growth layer is doped with impurities, that is, non-doped silicon (Si)
When the growth layer is doped with a trivalent impurity such as boron (B), both the curve A of the N-channel transistor and the curve B of the P-channel transistor in FIG. 1 have a threshold value of |qN/Cox|. When it is translated in the positive direction of the voltage and doped with a pentavalent impurity such as phosphorus (P), it is also translated in the negative direction by |qN/Cox|. Here, q is the electron charge, and N is silicon (Si).
The dose of impurity into the growth layer, Cox, is the capacitance per unit area of the gate oxide film.

The present invention uses the two phenomena described above to freely control the threshold voltage of an MIS type semiconductor device.

Example 1 FIG. 2 is a cross-sectional view of a complementary MOS semiconductor device formed in an SOS structure. In the figure, 1 is the source region of the sapphire substrate 2, 3 is the drain region, 4 is the non-sapphire substrate,
A doped silicon (Si) growth layer, 5 a gate oxide film, 6 a gate made of silicon, 7 a drain region, 8 a source region, 9 a non-doped silicon (Si) growth layer, 10 a gate oxide film, 11 is a gate made of polysilicon, 12 is an aluminum wiring layer, and 13 is an insulator layer made of PSG. Note that the transistor on the left is an N-channel device, and the transistor on the right is a P-channel device.

In a complementary MOS semiconductor device having such a structure, silicon (Si) growth layers 4 and 9
By controlling the thickness of these N and P-
The threshold voltage of the channel element can be set to a predetermined value. As an example, if the thickness of a non-doped silicon (Si) growth layer is 0.2 [μm], the threshold value of an N-channel device is 3.
[V], and the threshold value of the R-channel element is -2 [V], both of which are in enhancement mode.

Furthermore, as described above, complementary MOS semiconductor devices are often manufactured so that the absolute values of the threshold voltages of the N-channel element and the P-channel element are the same. This requires only one additional doping step for the entire wafer surface.
For example, 0.2 of the thickness of the silicon (Si) growth layer.
[μm], the gate oxide film thickness is 1000 [Å], and if phosphorus (P) is ion-implanted into the growth layer at a doping level of 3×10 ¹¹ [cm ^-2 ], the N-channel element and P
-The threshold voltage of each channel element is 2.5
[V], -2.5 [V].

In this doping step, the entire wafer is doped, so no mask is required. Furthermore, it is of course possible to do doping by other methods without using ion implantation, and furthermore, when stacking a silicon (Si) growth layer on a sapphire substrate, a predetermined amount of impurities may be added in advance. You can dope it.

In some cases, you may want to lower the threshold voltage even further, but in such cases,
It is sufficient to reduce the thickness of the gate oxide film. For example, if the gate oxide film thickness is 500 [Å] and the non-doped silicon (Si) growth layer is 0.5 [μm], the P-channel device, N - The absolute value of the threshold voltage for both channel elements is 0.6 [V].

Example 2 As is clear from Figure 1, when the thickness of the silicon (Si) growth layer is made thinner, the threshold value of the MOS type semiconductor device shifts to the enhancement mode side. multiple
If it is necessary to shift the threshold voltage of some of the MOS semiconductor devices toward the enhancement mode side, the thickness of the silicon (Si) growth layer is reduced only in those MOS semiconductor devices. By doing so, you can achieve your purpose. As an example, as shown in Figure 3,
In a case where the input signal Vin is applied to the gate of the MOS transistor _T3 , a gate electrode protection circuit for the MOS transistor _T3 can be used, which is composed of P-channel MOS transistors _T1 and _T2 and a resistor R.

This protection circuit is constructed as follows: Vin>V _DD + |Vthp|...(1) (where Vthp is a P-channel MOS transistor
(threshold voltages of T ₁ and T ₂ ), the P-channel MOS transistor T ₁ becomes conductive, and when Vin<V-|Vthp|...(2), the P-channel MOS transistor T ₂ becomes conductive. It becomes conductive to prevent a large voltage from being applied to the gate electrode of the MOS transistor _T3 to be protected.

In the circuit shown in FIG. 3, V _DD =5 [V],
Assuming the threshold voltage Vthp of P-channel MOS transistors T ₁ and T ₂ = -1 [V], Vin<-1 [V]......(3) Vin>6 [V]...... (4) For each voltage, P-channel MOS
Transistors T ₁ and T ₂ become conductive.

On the other hand, if the gate oxide film thickness is 1000 [Å],
Since the gate oxide film breakdown voltage is 80 [V] or more, the above-mentioned conditions for making the P-channel MOS transistors T ₁ and T ₂ conductive are more than sufficient.
If the input voltage is at a level that does not damage the gate oxide film, the input signal Vin will be transmitted to the internal circuit faster if the P-channel MOS transistors _T1 and _T2 do not become conductive, so the threshold of these two transistors is It is desirable that the value voltage be superior to the threshold voltage of the MOS transistor _T3 to the enhancement mode side. In this case, the M.O.S.
The thickness of the silicon (Si) growth layer of transistor T ₃ is 0.6 [μm], and the thickness of the silicon (Si) growth layer of P-channel MOS transistors T ₁ and T ₂ is
0.1 [μm], the threshold voltage of MOS transistor T ₃ is -1 [V] (this is -1 [V] for P-channel, +1 [V] for N-channel). ), P-channel
The threshold voltage of MOS transistors T ₁ and T ₂ is -4
It can be made into [V]. Therefore, Vin>9 [V],
P only when the input voltage becomes Vin<-4 [V]
- Channel MOS transistors T ₁ and T ₂ will each become conductive, which can improve the transmission speed of input signals.

Embodiment 3 In order to improve the speed of logic circuits, a so-called enhancement-depletion configuration (hereinafter abbreviated as E/D type) circuit is often used in which a depletion type MOS transistor is used in place of the load resistor of an inverter circuit.

When forming this E/D type inverter circuit with an SOS structure, enhancement type MOS transistors and depletion type transistors were conventionally created by changing the impurity dose by ion implantation into the silicon (Si) growth layer under the gate. If this method has been used, it is quite troublesome to control the dose of impurities, but in the embodiment of the present invention,
As will be explained below, an E/D type inverter circuit can be formed by simply changing the thickness of the silicon (Si) growth layer.

FIG. 4 is an inverter circuit diagram, where _T11 is a load transistor consisting of a depletion type MOS transistor. _T12 is a driver transistor, which is an enhancement type MOS transistor. Both transistors are N-channel type.
Consists of MOS transistors.

FIG. 5 is a cross-sectional view of the circuit shown in FIG. 4 when it is formed with an SOS structure. In the figure, 21 is a sapphire substrate, 22 is a source region, 23 is a drain region, 2
4 is a non-doped silicon (Si) growth layer, 25
2 is a gate oxide film, 26 is a gate made of polysilicon, and the source region 22 to gate 26 constitute a driver transistor _T12 . 27 is a source region, 28 is a drain region, 29 is a non-doped silicon (Si) growth layer, 30 is a gate oxide film,
31 is a gate made of polysilicon, and the source region 27 to gate 31 serve as a load and a transistor.
Configure T ₁₁ . Note that 32 is an aluminum wiring layer, and 33 is an insulating film made of PSG.

In such a configuration, the depletion type
The silicon (Si) growth layer 29 of the load transistor, which is a MOS transistor, has a thickness of 0.2 [μm], and is an enhancement type MOS transistor. The thickness of the silicon (Si) growth layer 24 of the driver transistor is 0.1 [μm]. Then, when phosphorus (P) is implanted at a dose of 3.6×10 ¹² cm ^-2 over the entire surface of the wafer, the threshold voltage of the load transistor T ₁₁ is -3 [V], and the threshold voltage of the driver transistor T ₁₂ is 3 [V]. V].

As explained in detail above, the present invention enables an SOS structure to be formed by simply adjusting the thickness of a silicon growth layer grown on an insulating substrate and/or the dose of impurities to this growth layer. Since the threshold voltage of the MIS type semiconductor device formed above can be freely designed, the practical effect is extremely large.

[Brief explanation of the drawing]

Figure 1 is a characteristic curve diagram showing the relationship between the thickness of the silicon growth layer and threshold voltage of a MIS type transistor formed on an SOS structure, and Figure 2 is a cross-sectional view of a complementary MOS semiconductor device formed on an SOS structure. Figure 3 is
A protection circuit diagram composed of MOS transistors, Figure 4 is an inverter circuit diagram, and Figure 5 is an SOS
FIG. 2 is a cross-sectional view of an inverter circuit formed on the structure. In the figure, 1 and 21 are sapphire substrates, 2, 8,
22 and 27 are source regions, 3, 7, 23 and 28 are drain regions, 4, 9, 24 and 29
is a non-doped silicon growth layer, 5, 10, 2
5 and 30 are gate oxide films, and 6, 11, 26 and 31 are gates.

Claims (1)

[Claims] 1. In the process of forming an MIS type semiconductor integrated circuit on a Si single crystal layer grown on a single crystal insulator substrate such as sapphire or spinel, the layer thickness of a plurality of Si single crystal island regions is made to be different from each other. 1. A method for manufacturing a semiconductor integrated circuit, characterized in that the threshold voltage (Vth) of a MISFET in a shaped region is controlled by layer thickness.