JPH0697864A - State change monitor system - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] The load on the CPU is lightened, and even if the number of units to be monitored and controlled increases, it is not necessary to increase the wiring or registers for monitoring and control. [Structure] The transmission / reception units 1-1 to 1-n are provided with a transmission / reception control unit 11 which adds new and old state information and state change presence / absence information to main data and sends the main data to the bus 5. In the interface unit 3, a 2-port RAM 32 that stores both the old and new state information together with the main data received from each unit, and a state change detection unit 33 that detects state change presence / absence information in the data and outputs a state change detection pulse 33. A unit number output section 35 for outputting the number of the transmitting unit currently being received, and a unit number register 34 for holding the number of the state change unit at the timing of the state change detection pulse and notifying the CPU 4 are provided. The CPU 4 recognizes the unit and knows the status change item from the old and new status information of the corresponding address of the 2-port RAM 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a CP in one device.
In a device in which a plurality of units that perform one-to-multipoint communication between U and the CPU via a data bus are mounted, the CPU changes the state of the units in order to monitor and control the plurality of units. Regarding monitoring method.

[0002]

2. Description of the Related Art A device such as a base station of a digital mobile telephone system is provided with a plurality of wireless transmission / reception units (hereinafter referred to as transmission / reception units) for performing wireless communication with a mobile station and a mobile station via each transmission / reception unit. It is composed of a common control unit that controls connection such as making and receiving calls.

The CPU of the common control unit transmits and receives call control data to and from each transmission / reception unit connected to the data bus by the multi-drop method via the interface unit to control call connection and the like.

Each transmission / reception unit is composed of a printed board package and is connected to a common control section in the same rack via a data bus. Each transmission / reception unit is assigned its own transmission / reception data via the data bus. The data bus is used in a time-sharing manner by sending it to the data bus serially in a time slot.

The interface unit receives the data serially transferred from each transmission / reception package via the data bus, converts the data into parallel data, and writes the parallel data in the 2-port RAM. CPU via the system bus,
I access the 2-port RAM at a time that is convenient for me, fetch the received data, and process it. To this end, the interface section has a data transmission / reception circuit for converting the received data into a form that can be accessed and processed by the CPU, and a 2-port RAM for temporarily buffering the data to be transmitted / received.

On the other hand, in addition to the main processing for call control, the CPU also performs monitoring control processing for operating each package normally, such as failure of each transmission / reception package and power supply state monitoring.

Conventionally, a supervisory control bus for transmitting and receiving a supervisory control signal is provided separately from a data bus for exchanging a main signal between the package and the CPU to exchange supervisory control signals.

[0008]

As described above, according to the prior art, the communication control unit and the plurality of transmission / reception packages are
Two buses were provided, a data bus for transmitting / receiving main data and a supervisory control bus for transmitting / receiving supervisory control information. Then, in order to allow arbitrary access from the system bus on the CPU side to the supervisory control information transmitted / received from each transmission / reception package via the supervisory control bus, a register for temporarily holding state information is interfaced with the package. It was installed in the face section. However, in a mobile radio base station device or the like in which the number of packages to be monitored and controlled is extremely large, there is a problem that the number of registers becomes large and the hardware scale of the interface unit becomes large. For example, if there are 72 packages to be monitored and each requires a status register and a control register of 8 bits each, it is necessary to provide 144 8-bit registers in the interface section.
It was physically impossible.

Further, since the CPU periodically reads the status information from the status register and checks the presence / absence of a state change by software, the software processing for monitoring and control imposes a heavy burden on the CPU.

The present invention has been made in view of the above problems. It reduces the load on the CPU during the supervisory control process, and increases the number of wirings and registers for supervisory control even if the number of units subject to supervisory control increases. An object of the present invention is to provide a state change monitoring method that does not cause the change.

[0011]

FIG. 1 is a block diagram of the state change monitoring system of the present invention. As shown in FIG. 1, the above-mentioned problem is caused by multi-drop connection to the data bus 5 and a plurality of transmission / reception units 1-1 to 1-n for transmitting main data to the CPU 4 via the data bus and from the data bus 5. Of the main data stored in the interface unit 3 and the CPU 4 that takes in the main data stored in the interface unit 3 via the system bus 6 and processes the main data. Each transceiver unit
This is a method for monitoring the abnormal status of 1-1 to 1-n, in which each transmitting / receiving unit 1-1 to 1-n adds the old and new status information of its own unit to the main data and the status information A transmission / reception control unit 11 for sending to the bus 5 is provided, and the interface unit 3
The 2-port RAM 32, which stores both the old and new state information as well as the main data received from each unit, and the condition change presence / absence information in the received data are monitored, and the condition change detection pulse is output when the condition change is detected. The detection unit 33, the unit number output unit 35 that outputs the unit number of the transmission / reception unit that is the transmission source of the currently received reception data, and the unit number that the unit number output unit outputs at the timing of the state change detection pulse. A FIFO unit number register 34 for holding the number of the state change unit by writing and notifying the CPU 4 of an interrupt is provided.
When U4 receives the interrupt notification, it reads the contents of the unit number register 34, recognizes the status change occurrence unit, and
The state change monitoring method of the present invention is characterized in that the state change item is known from the old and new state information of the corresponding address of the port RAM 32.

[0012]

The interface section interrupts the CPU only when it detects a state change in any of the transmitting and receiving units. Therefore, the CPU reads the unit number register by a predetermined interrupt process and determines the unit number in which the state change occurs. By knowing and reading the data of the 2-port RAM corresponding to that number, the status information can be obtained.

Therefore, it is sufficient to hold only the address of the transmission / reception package that has changed as a register, and it is not necessary to provide as many registers as the number of units to be monitored so that all status information can be stored. The number can be reduced. Further, the CPU does not need to read the status information periodically to detect a situation change, and is notified only when there is a situation change, so that the time dedicated to the main data control processing increases and the utilization efficiency improves. . Further, since the data bus is shared by the main data and the supervisory control signal, it is not necessary to provide a dedicated supervisory control bus, and the number of wires can be reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The state monitoring system of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a state change monitoring system of the present invention,
FIG. 2 is an address map of the reception data register on the 2-port RAM.

In FIG. 1, 1-1 to 1-n are a plurality of transmission / reception units, 2 is a common control section, 3 is provided in the common control section, and an interface section for relaying a system bus and a data bus is designated by 4 A CPU and a reference numeral 5 are data buses to which transmission / reception units are connected in a multi-drop manner and through which data transmitted / received between a transmission / reception package and a common control unit passes.

In each of the transmission / reception units 1-1 to 1-n, the transmission / reception control unit 11 changes the current state information of the unit and the old state information of the unit into the main data for call control received from the wireless section. Then, a transmission frame is created by adding the status change presence / absence information indicating whether or not there is such a situation, and the frame is transmitted to the data bus 5 in the time slot assigned to the own unit.

The interface unit 3 includes a transmission / reception control unit 31,
It has a 2-port RAM 32, a state change detector 33, a unit number register 34, and a unit number output unit 35. The transmission / reception control unit 31 of the interface unit converts serial reception data from a plurality of transmission / reception units sequentially transmitted in each time slot through the data bus 5 into serial-to-parallel data and takes out the necessary data and outputs it to the 2 port. The data is written in the reception register provided on the RAM 32 for the transmission / reception unit.

The two-port RAM 32 has two ports capable of write / read access asynchronously and can be read from both ports at the same time. The transmission / reception control unit 31 of the interface unit and the system bus 6 of the CPU are connected to each other. Each can be accessed independently.

FIG. 2 is an address map of the reception data register of the 2-port RAM. For example, an area corresponding to each transmission / reception unit number is provided with an area for supervisory control data following the main data. And supervisory control data is written.

The state change detector 33 constantly monitors state change presence / absence information sent on a specific bit of the received frame, and when the state change is detected in the received data of a certain time slot, the state change occurs. Outputs detection pulse. On the other hand, the unit number output unit 35 outputs unit number data corresponding to the time slot being received (corresponding to the time slot number).
Is always output to the unit number register 34 composed of a FIFO memory. The unit number at that time is written in the unit number register 34 by the state change detection pulse.

The unit number register 34 is, for example, a shift register having an 8-bit width, can hold a predetermined number of number data, is a FIFO memory read from the oldest data by read access, and stores some data. During the period, the empty signal EP of "L" level is output. This signal is CP as an interrupt notification signal
U4 is notified. The CPU 4 monitors this interrupt notification signal. When the CPU 4 detects the interrupt notification signal, it accesses the unit address register 34 via the system bus 6 to read the oldest data and obtain the transmission / reception unit number in which the state change occurred. recognize. Then, the CPU 4 accesses the status information address in the reception register of the transmission / reception unit on the 2-port RAM 32 via the system bus 6 to read the current / old status information and perform predetermined processing.

[0022]

As described above, according to the present invention,
In a system having a plurality of transmission / reception units that perform one-to-many main data communication with a CPU via a serial data bus, monitoring of status information when the CPU performs monitoring control of each unit is performed by a monitoring control bus. It has an effect that it can be performed without providing a monitor control register for each unit and without increasing the load on the CPU. Also,
There is also an effect that it is possible to easily cope with an increase in the number of units to be monitored and controlled and the number of monitored and controlled items simply by increasing the storage capacity of the 2-port RAM.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a state change monitoring system of the present invention.

FIG. 2 Address map of receive data register on 2-port RAM

[Explanation of symbols]

1-1 to 1-n ... Transmission / reception unit, 11 ... Transmission / reception control unit, 2 ...
Common control section, 3 ... Interface section, 31 ... Transmission / reception control section, 32 ... 2-port RAM, 32a ... Reception register, 33 ... Condition change detection section, 34 ... Unit number register, 35 ... Unit number output section, 4 ... CPU 5, ... Data bus, 6 ... System bus

Claims (1)

[Claims] 1. A plurality of transmission / reception units (1-1 to 1-n) connected to a data bus (5) in a multi-drop manner and transmitting main data to a CPU (4) via the data bus, and the data bus.
The interface part (3) that receives the main data from (5) and temporarily stores it in the 2-port RAM, and the main data stored in the interface part (3) is fetched and processed via the system bus (6). In a device having a CPU (4), the C
This is a method in which the PU (4) monitors the status change of each transmission / reception unit (1-1 to 1-n). Transmission / reception control unit (11) that adds status information and status change presence information to the data bus (5)
The interface unit (3) monitors the status information in the received data and the 2-port RAM (32) that stores both the old and new status information as well as the main data received from each unit. State change detector (33) that outputs state change detection pulse when it detects a change
And a unit number output section (35) that outputs the unit number of the transmission / reception unit that is the sender of the currently received data
By writing the unit number output by the unit number output section at the timing of the state change detection pulse, the unit number in the FIFO format for holding the state change occurrence unit number and notifying the CPU (4) of an interrupt register
(34) is provided, the CPU (4) reads the contents of the unit number register (34) when an interrupt notification is received, recognizes the status change occurrence unit, and recognizes the corresponding address of the 2-port RAM (32). A state change monitoring method characterized in that the state change item is known from old and new state information.