JPH0710043B2 - PWM drive circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a PWM (Pulse Width Modulation) drive circuit, and more particularly to generating a pulse signal having a pulse width according to a signal level of a drive signal and switching a load based on the pulse signal. The present invention relates to a driving PWM drive circuit.

BACKGROUND ART A PWM bidirectional switching drive system is known as one system for driving a load such as a motor. The drive system is
It has excellent characteristics of low loss and low power consumption, and is particularly useful for driving a load such as a motor in a vehicle-mounted device, a portable device or the like which uses a battery as a power source.

Conventionally, a PWM drive circuit generates two triangular wave signals a and b in phase with each other as shown in FIG. 13, and one of these triangular wave signals has a higher DC bias level than the other b. By using the upper and lower reference inputs of the comparison circuit 100 and further the drive signal c as the comparison input, a pair of pulse signals d having a pulse width corresponding to the signal level of the drive signal and corresponding to the drive direction of the load, There is a configuration in which e is obtained and the load is switching-driven based on the pair of pulse signals d and e.

In such a configuration, the tip portion of the triangular wave signal is used in the range where the signal level of the drive signal c is small.
However, in the process of generating the triangular wave signal, there is no infinite band in the amplifier, and ringing at the tip of the triangle wave or so-called rounding is unavoidable, so use the tip of the triangle wave signal. The conventional circuit that must be performed has a drawback that the linearity of the input / output characteristics deteriorates especially when the signal level of the drive signal c decreases.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional ones. By using only the linear portion of the triangular wave signal for the generation of the pulse signal, the signal level of the drive signal is particularly reduced. An object of the present invention is to provide a PWM drive circuit capable of improving the linearity of the input / output characteristics at the time.

The PWM drive circuit according to the present invention generates two-phase triangular wave signals having substantially equal peak values and opposite phases to each other, and the two-phase triangular wave signals are used as reference inputs of the upper limit and the lower limit of the comparison circuit, respectively. The pulse signal is generated according to the signal level of.

Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In FIG. 1, the first constant current source 1 is a transistor.
Is formed by Q _1, Q ₂ and resistors R _1, consisting of R ₂ current mirror circuit. The second constant current source 2 connected in series with the first constant current source 1 includes transistors Q ₃ and Q ₄ which are connected in parallel to each other, and a base via the transistors Q ₃ and Q ₄ and a resistor R _3. Is composed of a current mirror circuit composed of a transistor Q ₅ connected in common and emitter resistances R ₄ and R _{5 of} each transistor, and a constant current value of the first constant current source 1
It is designed to draw in a current value 2I ₀ that is twice as large as I ₀ . A storage means is provided between the common connection point of the first and second constant current sources 1 and 2, that is, the common connection point of the collectors of the transistor Q ₂ and the transistors Q ₃ and Q ₄ and the ground, which is the reference potential point. Capacitor C ₁ is connected.

The voltage across the capacitor C ₁ is the comparator COMP ₁ , COMP ₂
And becomes the comparison input of the comparison circuit 3 for monitoring the voltage level, that is, the inverting input of the comparator COMP ₁ and the non-inverting input of COMP ₂ . The upper and lower comparison reference levels V _U and V _L of the comparison circuit 3 have four resistors R ₅ to R ₅ connected in series.
It is set by dividing the reference power supply voltage Vref by R ₈ . The resistors R _{5 to} R ₈ further divide the reference power supply voltage Vref into about 1/2, and the voltage is divided into 1/2 via the operational amplifier OP ₁ of the voltage follower circuit configuration.
Vref. The two comparison outputs of the comparison circuit 3, that is, the respective outputs of the comparators COMP ₁ and COMP ₂ are RS-flip-flops 4.
Set (S) and reset (R) inputs. The output of the flip-flop (hereinafter simply referred to as FF) 4 is supplied to a control circuit 5 which is composed of a transistor Q ₆ and resistors R ₉ and R ₁₀ and which controls activation / deactivation of the second constant current source 2. It The control circuit 5 deactivates the second constant current source 2 by turning on the transistor Q ₆ in response to the output of FF ₄ and turning off the transistors Q ₃ and Q _4. .

The voltage across the emitter resistor R ₅ in the second constant current source 2 serves as the inverting input of the operational amplifier OP _{2 having} the voltage follower circuit configuration. The comparison reference level of the operational amplifier OP ₂ is set by dividing the reference power supply voltage Vref by the resistors R ₁₁ and R ₁₂ , and the first and second constant current sources 1 and 2 are set by the comparison output.
The current value setting circuit 6 for setting the constant current value of is constructed.

The voltage across the capacitor C ₁ becomes the first-phase triangular wave signal φa via the operational amplifier OP ₃ having the voltage follower circuit configuration, and is phase-inverted by the inverter 7 composed of the operational amplifier OP ₄ and the resistors R ₁₃ and R ₁₄ to generate the first phase triangular signal φa. The triangular wave signal φa of the second phase is the opposite phase of the triangular wave signal φa of the phase. These triangular wave signals φ
A direct current bias of 1/2 Vref is applied to a and φb.

As described above, the triangular wave generating circuit 8 for generating two-phase triangular wave signals φa and φb having substantially the same peak value and opposite phases to each other is configured. In the triangular wave generation circuit 8, the constant current value I _O
The first constant current source 1 and the second constant current source 2 having a constant current value 2 I _O are provided, and the capacitor C ₁ is charged and discharged with a constant current by the on / off control of the second constant current source 2. By
Since it is configured to generate a triangular wave,
When integrated into an IC (integrated circuit), there is an advantage that only one terminal pin (terminal 8a in FIG. 1) is required for the capacitor C ₁ .

Two-phase triangular wave signals φa and φb are used as comparators COMP ₃ and COMP ₄
And the upper and lower comparison reference inputs of the comparator circuit 9, that is, the inverting inputs of the comparators COMP ₃ and COMP ₄ . As a comparison input of the comparison circuit 9, that is, a non-inverting input of each of the comparators COMP ₃ and COMP ₄ , a drive signal of, for example, the motor M which is a load is supplied via the resistor R ₁₅ . Comparator COMP ₃ , CO
Each non-inverting input of MP ₄ and the reference power source voltage Vref is applied via a resistor _{R 16 (R 15 = R 16} ), that the resistance values of the resistors R _15, R ₁₆ are set to be equal Then, the drive signal is biased to 1/2 Vref when it becomes the comparison input of the window comparator 9. That is, the signal reference level of the drive signal becomes 1/2 Vref.

As a result, the circuit reference level of the triangular wave generation circuit 8, that is, the comparison reference level of the comparison circuit 3 and the DC bias level (signal reference level) of the drive signal are both the same reference power supply voltage.
It will be set by the resistance voltage division of Vref. Therefore, even if the power supply voltage fluctuates, two-phase triangular wave signals φa and φ
Since the relative signal level between b and the drive signal is always kept constant, stable circuit operation is always performed regardless of fluctuations in the power supply voltage.

The comparison output of the comparator COMP ₃ becomes one input of the AND gate 10 and the NOR gate 11, and the comparison output of the comparator COMP ₄ becomes each input of the AND gate 10 and the NOR gate 11. As a result, the first and second pulse signals corresponding to the driving direction of the motor M are derived from the respective output terminals of the AND gate 10 and the NOR gate 11.

The above-mentioned drive signal is applied to the comparator COMP ₅ via the resistor R _15.
It is also the non-inverting input of. Comparator COMP ₅ is 1/2
By making Vref an inverting input, a polarity determining means for determining the polarity of the drive signal with respect to the signal reference level is configured. The discrimination output of the comparator COMP ₅ becomes the data (D) input of D-FF12. D-FF12 is in the triangular wave generation circuit 8
The Q output of RS-FF4 is used as a trigger (T) input, and its Q and output are input to AND gates 13 and 14, respectively. AND gates 13 and 14
The outputs of the AND gate 10 and the NOR gate 11, that is, the first and second pulse signals are respectively input to the other inputs, and the D-FF12's
The gate means is configured to output only one of the first and second pulse signals based on Q and the output.

Each output pulse of the AND gates 13 and 14 is a compensating circuit 1 for compensating for the energy loss due to the counter electromotive force of the counter electromotive force absorbing diodes D ₁ and D ₂ in the motor drive circuit 18 described later.
Supplied to 5,16. In the compensation circuit 15, the AND gate 13
Output pulses through the resistor R ₁₇ is the base input of the transistor Q ₇ of the transistor Q ₇ is connected in parallel with the capacitor C _2. The capacitor C ₂ is short-circuited at both ends when the transistor Q ₇ is turned on, the charge is instantaneously discharged, and when the transistor Q ₇ is turned off, that is, when the output pulse of the AND gate 13 disappears, the constant current source Ia is used. Charging starts. The voltage across capacitor C ₂ is the comparator
Inverted input for COMP ₆ . Comparator COMP ₆ is the reference voltage
When E _O is a non-inverting input, a high-level pulse signal is generated when the voltage across capacitor C ₂ is lower than the reference voltage E _O. As a result, the compensating circuit 15 outputs a pulse signal in which a pulse having a substantially constant pulse width is added to the output pulse of the AND gate 13.

Similarly to the compensation circuit 15, the compensation circuit 16 has a resistor R ₁₈ , a transistor Q ₈ , a capacitor C ₃ , a constant current source Ib and a comparator CO.
It is composed of MP ₇ , and its operation is exactly the same as that of the compensation circuit 15.

Each output pulse of the compensation circuits 15 and 16 is
Is supplied to the motor drive circuit 18 via. In the motor drive circuit 18, the motor M is a PNP transistor Q
₉ and NPN transistor Q ₁₀ and PNP transistor Q ₁₁ and N
It is connected between the common connection points of each collector of the PN transistor Q ₁₂ . Transistors _{Q 9, Q 10, Q 11} , Q 12 is a power transistor. The emitters of the transistors Q ₉ and Q ₁₁ are directly connected to the power supply V _CC , and the bases are connected to the resistor R
It is connected to the power supply V _CC via ₁₉ and R ₂₀ . On the other hand, the emitters of the transistors Q ₁₀ and Q ₁₂ are both grounded, the bases thereof are grounded via the resistors R ₂₁ and R ₂₂ , respectively, and are connected to the collectors thereof via the zener diodes ZD ₁ and ZD ₂ . . Both ends of the motor M are diodes for absorbing back electromotive force.
It is connected to the power supply V _CC via D ₁ and D ₂ .

In the pre-drive circuit 17, the pulse signal supplied from the compensation circuit 15 drives the power transistor Q ₉ via the pre-drive stage composed of the resistors R ₂₃ , R ₂₄ and the transistor Q _13, and after being inverted by the inverter 19, Resistance R ₂₅ ~ R
Power transistor Q ₁₂ is driven through a pre-drive stage consisting of ₂₇ and transistor Q ₁₄ . As a result, a current flows in the direction of the arrow indicated by the solid line in the motor M, and the motor M is rotationally driven in the positive direction. The pulse signal from the compensating circuit 15 is also supplied to the transistor Q ₁₅ via the inverter 20 to turn on the transistor Q ₁₅ when the forward driving of the motor M is stopped. As a result, the base and emitter of the power transistor Q ₁₂ are short-circuited by the transistor Q ₁₅ , and the power transistor Q ₁₂ is instantly turned off. This transistor Q
_The reason for providing ₁₅ will be described in detail later. The base of transistor Q ₁₅ is connected to power supply V _CC through resistor R ₂₈ .

On the other hand, the pulse signal supplied from the compensation circuit 16 is a resistance
The power transistor Q ₁₁ is driven through a pre-drive stage including R ₂₉ , R ₃₀ and a transistor Q _16, and the power transistor Q ₁₁ is inverted through an inverter 21 and a pre-drive stage including resistors R _{31 to} R ₃₃ and a transistor Q _17. Drive the power transistor Q ₁₀ . As a result, a current flows in the direction of the arrow indicated by the broken line in the motor M, and the motor M is rotationally driven in the opposite direction. The pulse signal from the compensating circuit 16 is also supplied to the transistor Q ₁₈ via the inverter 22 and turns on the transistor Q ₁₈ when the reverse driving of the motor M is stopped. As a result, the base and emitter of the power transistor Q ₁₀ are short-circuited by the transistor Q ₁₈ , and the power transistor Q ₁₀ is instantly turned off. The base of transistor Q ₁₈ is connected to power supply V _CC through resistor R ₃₄ .

Next, the circuit operation of the PWM drive circuit according to the present invention will be described.

First, the circuit operation of the triangular wave generation circuit 8 will be described with reference to the waveform diagram of FIG. In the triangular wave generation circuit 8, the second
When the constant current source 2 of 1 is in the inactive state, that is, when the transistors Q ₃ and Q ₄ are in the off state due to the turning on of the transistor Q ₆ , the capacitor C ₁ receives the constant current supplied from the first constant current source 1. As a result, as shown in FIG. 2 (a), the battery is charged with a constant inclination angle. When the voltage across the capacitor C ₁ reaches the upper limit reference level V _U of the comparison circuit 3, the comparator COMP
₁ generates a low level pulse (b), and in response to this pulse (b), the output (d) of RS-FF4 transits to a low level. As a result, the transistor Q ₆ is turned off, so that the second constant current source 2 is activated, that is, the transistors Q ₃ and Q ₄ are turned on, and the constant current of the first constant current source 1 is doubled. The current of is absorbed.

As a result, the capacitor C _{1 which} has been in the charged state until then shifts to the discharged state, and as shown in FIG. 2A, the capacitor C ₁ is discharged with the same inclination angle as that in the charging. Then, when the voltage across the capacitor C ₁ reaches the lower limit reference level V _L of the comparison circuit 3, the comparator COMP ₂ generates a low level pulse (c), and in response to this pulse (c), the RS-FF 4 The output (d) transits to the high level. That is, the RS-FF 14 constitutes an inverting means that outputs an inverted signal for each peak of the triangular wave. As a result, the transistor Q ₆ is turned on and the second constant current source 2 is deactivated, so that the capacitor C ₁ is turned on again.
Will be charged with a constant inclination angle by the constant current supplied from the first constant current source 1.

In this way, the voltage across the capacitor C ₁ is shown by the solid line in FIG. 2 (a) by repeating the charging / discharging operation of the capacitor C ₁ with the constant currents of the first and second constant current sources 1 and 2. As shown by, changes into a triangular wave and is output as a first-phase triangular wave signal φa via the operational amplifier OP ₃ and the inverter 7
As a result of the phase inversion at, the signal is output as the second-phase triangular-wave signal φb having the same peak value and the opposite phase to the first-phase triangular-wave signal φa as shown by the broken line in FIG. The two-phase triangular wave signals φa and φb serve as reference inputs to the comparison circuit 9.

As a comparison input of the comparison circuit 9, a drive signal of the motor M having a signal reference level of 1/2 Vref is supplied. Here, when the motor M is, for example, a spindle motor that rotationally drives a compact disc, an error signal obtained by comparing a reproduction synchronization signal from the disc and a reference synchronization signal becomes the drive signal, and based on this error signal Drive control of the spindle motor is performed. This is the so-called spindle servo.

In FIG. 3, the cross points of the two-phase triangular wave signals φa and φb are at 1/2 Vref level, and PW when the signal level of the drive signal is high and low with respect to this 1/2 Vref level.
The M operation will be described below.

In the comparison circuit 9, first, when the signal level of the drive signal is higher than the 1/2 Vref level as shown by the dashed line in FIG. 7A, the output (b) of the comparator COMP ₃ is At the time t ₁ when the signal level of the one-phase triangular wave signal φa becomes low, the low-level transits to the high-level,
The high level is maintained until time t ₄ when the signal level of the triangular wave signal φa exceeds the signal level of the drive signal. The output (c) of the comparator COMP ₄ transits from the high level to the low level at time t ₂ when the signal level of the second-phase triangular wave signal φb exceeds the signal level of the drive signal, When it becomes low, it transits to the high level again at t ₃ .

On the other hand, when the signal level of the drive signal is lower than the 1/2 Vref level as shown by the chain double-dashed line in FIG.
The output (d) of MP ₃ changes from the low level to the high level at time t ₂ when the signal level of the first-phase triangular wave signal φa exceeds the signal level of the drive signal, and the signal level of the triangular wave signal φa changes to that of the drive signal. Maintains high level until time t ₃ when signal level is exceeded. The output (e) of the comparator COMP ₄ is the second
In time t ₁ in which the signal level of the triangular wave signal φb phase exceeds the signal level of the drive signal transitions from high to low, it goes high again at time t ₄ when becomes lower than the signal level of the drive signal.

The outputs of the comparators COMP ₃ and COMP ₄ are AND gates 10 and N.
It has two inputs to the OR gate 11, and the AND gate 10 has a high level when both inputs are high, that is, the signal level of the drive signal is
When it is higher than 1/2 Vref level, it outputs a high level pulse (f), and NOR gate 11 outputs low level when both inputs are low.
That is, when the signal level of the drive signal is lower than the 1/2 Vref level, a high level pulse (g) is output. Therefore, the AND gate 10 and the NOR gate 11 output the pulse signals (f) and (g) corresponding to the driving direction of the motor M. Since the case where the signal level of the drive signal is constant has been described here, the pulse widths of the pulses (f) and (g) are constant, but this pulse width changes according to the signal level of the drive signal. It is easy to understand what to do.

In this way, two-phase triangular wave signals φa and φb having the same peak value and opposite phases are generated, and the two-phase triangular wave signals φa and φb are generated.
By performing PWM operation using the straight line part of a and φb, ringing may occur at the tip of the triangular wave,
Even if so-called blunting occurs, there is no deterioration in linearity when the signal level of the drive signal becomes small.

Here, when the reference power supply voltage Vref changes, the pulse width of the pulse signal generated by the PWM changes, and the driving power by this pulse signal changes according to the change of the power supply voltage. That is, as shown in FIG. 4A, when the pulse width of the pulse signal when the drive signal has a certain signal level is T _O , the drive power by this pulse signal is the pulse width T _O and the drive voltage V _{O. D} (Reference power supply voltage Vr
ef), it means that if the drive voltage V _D becomes, for example, 1/2 due to the fluctuation of the power supply voltage, the drive power will also become 1/2 as shown by the shaded area.

However, in the triangular wave generation circuit 8, the first and second
Current value setting circuit 6 that sets the constant current value of the constant current sources 1 and 2
The reference level for comparison is the reference power supply voltage Vr due to the resistors R ₁₁ and R _12.
Since the reference level is set according to the fluctuation of the power supply voltage, the current value setting circuit 6 sets the first and second constant current sources according to the fluctuation of the power supply voltage. The constant current value of 1 and 2 can be controlled. As a result, the inclination angle of the triangular wave changes as shown in FIG. 4 (B). On the other hand, the upper and lower comparison reference levels V _U and V _{L of} the comparison circuit 3 are also the reference power supply voltage Vr due to the resistors R _{5 to} R _8.
Since it is set by the voltage division of ef, the reference power supply voltage Vr
If ef becomes 1/2, the upper and lower comparison reference levels V _U , V
_L also becomes 1/2, and as a result, the peak value V _P of the triangular wave becomes 1/2 before the power supply fluctuation as shown in FIG. 4 (B). Therefore, by setting the inclination angle of the triangular wave so that the repetition cycle of the triangular wave is the same before and after the power supply change,
Since a pulse signal having a doubled pulse width (2T _O ) is generated, even if the drive voltage V _D becomes 1/2, the drive power by the pulse signal becomes the same as before the power supply change.

That is, in the triangular wave generation circuit 8, by controlling the peak value and the gradient of the triangular wave according to the fluctuation of the power supply voltage, the driving power by the pulse signal is changed to the reference power supply voltage Vref.
It is possible to always keep constant regardless of the fluctuation of. The inclination angle of the triangular wave is determined by the constant current values of the first and second constant current sources 1 and 2 and the capacitance of the capacitor C ₁ .

Referring again to FIG. 1, the signal level of the drive signal is now the fifth level.
If it changes as shown by the one-dot chain line in FIG. 5A, two pulse signals (b) and (c) having a pulse width corresponding to the polarity and signal level of the drive signal are output from the AND gate 10 and the NOR gate 11. And each becomes one input of the AND gates 13 and 14, respectively. The drive signal also serves as a comparison input of the comparator COMP _{5, and} the polarity with respect to the signal reference level 1/2 Vref is determined. The D-FF 12 that receives the comparison output (d) of the comparator COMP ₅ as a data input is an RS-F in the triangular wave generation circuit 8.
The F4 Q output (e) is used as the trigger input, and Q, output (f), and Q are output at the falling timing of the Q output (e).
(G) is generated. The Q, outputs (f) and (g) are supplied to the AND gates 13 and 14 as gate control signals.

In the above embodiment, the Q output (e) of RS-FF4 is directly fed to D-
Although it is used as the trigger input of the FF12, it can be used as the trigger input of the D-FF12 via a pulse generator that generates a pulse at the rising and falling timings of the Q output (e). According to this, the cycle of polarity determination is halved, and the resolution can be doubled.

The Q, outputs (f), and (g) of the D-FF12 are control signals that determine the driving direction of the motor M. For example, at a timing when the signal level of the driving signal is low and the polarity changes from positive to negative.
As for the reverse drive pulse signal (first pulse) instantaneously generated from the NOR gate 11 as shown in FIG. 5 (c), the output (g) is at a low level at the time of generation, The AND gate 14 operates to prohibit its output.
The reason for prohibiting this will be described below.

Now, consider the case where the reverse drive pulse signal is instantaneously generated from the NOR gate 11 as shown in FIG. 5C at the timing when the signal level of the drive signal is low and the polarity changes from positive to negative. In the motor drive circuit 18, the fifth
Transistor Q ₉ , in response to the pulse signal shown in FIG.
Although Q ₁₂ is in the ON state and the motor M is being driven in the forward direction, the transistor Q ₉ and Q ₁₂ are in the OFF state due to the generation of the reverse drive pulse signal shown in FIG. 5 (c). Therefore, the transistors Q ₁₁ and Q ₁₀ are turned on, and the motor M tries to drive in the reverse direction.

Here, as shown in FIG. 6, the transistor generally has a capacitance C _O between the base and the emitter, so that the transistor in the on-state in response to the drive pulse (a) disappears when the pulse (a) disappears. From transition to off state
It has the characteristic of requiring a delay time of t _OFF . Therefore, as described above, when the reverse driving pulse signal shown in FIG. 5C is generated, the transistors Q ₉ and Q ₁₂ should be turned off, and the transistors Q ₁₁ and Q ₁₀ should be turned on. such of the but rather can become transistor Q ₁₂ is turned off to momentarily by the delay time t _oFF, since temporarily so that the transistor Q ₁₁ periods which is turned at the same time occurs, the transistor Q _11, Q ₁₂ A large current may flow and the transistor may be destroyed.

However, in this PWM drive circuit, AND gates 13 and 14 are provided, and these gates 13 and 14 are controlled based on the polarity determination result with respect to the signal reference level of the drive signal, so in the case of the above example, The output of the reverse driving pulse signal shown in FIG. 5 (c) can be prohibited by the AND gate 14 in response to the output (g) of the D-FF 12, so that the transistor Q ₁₂ is turned on at the same time as the transistor Q _11. There is no such thing.

In addition, the delay time t _{OFF of} power transistors Q ₁₂ and Q ₁₀
In order to reduce the above, the pre-drive circuit 17 is provided with the transistors Q ₁₅ and Q ₁₈ . These transistors
Q ₁₅ and Q ₁₈ are instantly turned on in response to the disappearance of the drive pulse of power transistors Q ₁₂ and Q ₁₀ , and the delay time t _{OFF is set} by short-circuiting the base and emitter of these transistors Q ₁₂ and Q _10. Can be short-circuited. The delay time t _{OFF of the} transistor is generally about 1 to 2 μsec, but it is reduced by the provision of the transistors Q ₁₅ and Q _18.
It can be shortened to 1/10, that is, about 100 nsec. here,
Consider the case where the two triangular wave signals φa and φb are out of phase. In such a case, the AND circuit 10 or N
The OR circuit 11 may output an unnecessary pulse signal that should not be output in the normal phase state.However, the polarity is discriminated by the comparator COMP5, and depending on the discrimination result and the trigger signal which is a triangular polarity inversion signal. D-FF12
Output of the unnecessary pulse signal is prohibited from the AND circuits 13 and 14.

In this way, even if the two triangular wave signals φa and φb are out of phase with each other, the drive currents corresponding to the normal forward and reverse directions are supplied to the motor drive circuit 18.

Another embodiment for preventing the above-mentioned power transistors from turning on at the same time is shown in FIG. In the figure, as described above, the first and second pulse signals (a) corresponding to the driving direction of the motor M are output from the AND gate 10 and the NOR gate 11, and these pulse signals are predetermined by the delay circuits 23 and 24, respectively. Time τ _O
Only delayed. These delayed outputs (b) are supplied to the 3-state buffers 25 and 26, respectively. The first and second pulse signals (a) are also supplied to the one-shot multivibrators 27 and 28, respectively. The one-shot multi-vibrator 27, 28 is a delay circuit 23, 2 for a certain period of time after the disappearance of the first and second pulse signals.
The low level output (c) is generated until the time (2τ _O ) which is twice the delay time τ _O of 4 passes, and the buffers 26, 25 are generated.
And the second output from the delay circuits 24 and 23
The pulse signal of is prohibited from being supplied to the next stage.

FIG. 8 is an operation waveform diagram of the circuit of FIG. 7, (a) in the figure.
7A to 7C respectively show waveforms of signals (a) to (c) of FIG. 7 correspondingly. If explaining the circuit operation of FIG. 7 with reference to the waveform diagram for example with respect to an AND gate 10, a pulse signal (a) driving pulse is delayed by the time tau _O by the delay circuit 23 the motor M (b) At this time, in response to the low level inhibit signal (c) output from the one-shot multivibrator 27, the buffer 26 cuts off the output line of the other drive pulse. Thus, the output of the other drive pulses during a predetermined period before and after the occurrence generation of the drive pulse (b) (time tau _O) is to be inhibited, the power transistors Q ₁₂ previously described time tau _O, By setting the delay time t _OFF longer than Q ₁₀ , the power transistors Q ₉ and Q ₁₀ (or Q
₁₁ and Q ₁₂ ) are never on at the same time.

As mentioned above, the delay time t of the transistor is
_{Since OFF} is generally about 1 to 2 μsec, time τ _O is 5 μs
It is desirable to set it to about ec.

In FIG. 1, the first and second pulse signals corresponding to the driving direction of the motor M output from the AND gates 13 and 14 are supplied to the compensation circuits 15 and 16, respectively. These compensation circuits 15,
Reference numeral 16 is for compensating for the energy loss in the back electromotive force absorption diodes D ₁ and D ₂ in the motor drive circuit 18. The energy loss in the counter electromotive force absorption diodes D ₁ and D ₂ is almost constant and can be ignored when the pulse width of the pulse signal is large, but when the pulse width is small, the loss ratio is large. Is coming. Therefore, as indicated by the broken line in FIG. 9, the gain is reduced in the region where the pulse width of the pulse signal is small, so that when the pulse width is small, the reverse electromotive force absorption diodes D ₁ and D ₂ You just have to compensate for the energy loss.

Here, if the circuit operation of the compensation circuit 15 is described with reference to the waveform diagram of FIG. 10, the capacitor C ₂ is a constant current source.
Charged with a constant current by Ia, input pulse (a)
Transistor Q ₇ in response the charging electric charge of the capacitor C ₂ by the ON state is instantaneously discharged, the capacitor C ₂ again from the time the input pulse (a) ceases to exist is charged at a constant current to. Therefore, the voltage across capacitor C ₂
It changes as shown in Fig. 10 (b). This voltage across both ends (b) is compared with the reference voltage E _O by the comparator COMP8, and as a result, at the output end of the comparator COMP8, the pulse of the time from when the input pulse (a) is generated until a certain time Ta elapses after its disappearance. A pulse signal (c) having a width will be obtained. That is, a fixed pulse width Ta is added to the input pulse (a), and the energy in the counter electromotive force absorption diodes D ₁ and D ₂ is changed by the energy corresponding to the added pulse width Ta. The loss can be compensated.

FIG. 11 shows the input / output characteristics of the compensation circuits 15 and 16, that is, the relationship between the pulse width of the input pulse and the added pulse width. The voltage across the capacitor C ₂ is the reference voltage E _{O of the} comparator COMP8. No additional pulse width is added in the pulse width area of the input pulse that cannot be reduced to 0, and the additional pulse width changes proportionally in the area until reaching the zero level below the reference voltage E _O , and after reaching the zero level. In the area of, the added pulse width is a fixed width. That is, in the region where the pulse width of the input pulse is extremely small, no additional pulse width is added or the additional pulse width changes proportionally. This is because the rising and falling edges of the input pulse are not steep and are actually gentle. As a result, the gain can be improved in the range of the region as shown by the solid line in FIG.

The compensating circuits 15 and 16 are not limited to those of the configuration of the above embodiment, and for example, as shown in FIG. 12, a pulse signal having a constant pulse width Tb in response to the rising edge of the input pulse is used. It may be configured by a pulse generating circuit 29 for generating and an OR gate 30 which takes the logical sum of the output pulse and the input pulse of the pulse generating circuit 29. In such a configuration, when the pulse width of the input pulse is smaller than the pulse width Tb, a pulse signal having the pulse width Tb is always output from the OR gate 30,
When the pulse width of the input pulse is small, the energy loss in the back electromotive force absorption diodes D ₁ and D ₂ is compensated. When the pulse width of the input pulse is larger than the pulse width Tb, the pulse width for the input pulse is increased. Is not changed.

In the above embodiment, the case where the present invention is applied to the drive circuit of the spindle motor that rotationally drives the compact disc has been described. However, the present invention is not limited to this, and the carriage motor that drives the pickup and the focus of information reading light in the pickup. The present invention can be applied to a drive circuit of a focus actuator or a tracking actuator that controls tracking and tracking, and can be widely applied to a drive circuit of various loads in various devices as well as a compact disc player.

As described above, according to the PWM drive circuit of the present invention, only the linear portion of the triangular wave signal is used to generate the pulse signal for driving the load. Even if there is a drop or a rounding, these effects are not affected at all, and the linearity of the input / output characteristics can be improved especially when the signal level of the drive signal is low. Further, even when the phases of the two-phase triangular wave signals are deviated, the polarity discriminating means and the drive pulse generating means can prevent the generation of unnecessary drive pulse signals. It is effective for a driving circuit to be driven.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 4 is a waveform chart of each part for explaining the circuit operation of the triangular wave generation circuit in the figure, and FIG. 3 is a waveform diagram of each part for explaining the operation of generating two pulse signals corresponding to the drive direction of the load by the PWM operation, FIG. (A) and (B) are waveform charts for explaining the operation of changing the inclination angle and the peak value of the triangular wave in response to the fluctuation of the power supply voltage, and FIG.
Waveform diagram of each part for explaining the circuit operation of the simultaneous ON prevention circuit of the power transistors in the drive stage due to the _OFF delay time, FIG. 6 is a diagram for explaining the t _OFF delay time of the transistor, and FIG. FIG. 8 is a block diagram showing another embodiment of the ON prevention circuit, FIG. 8 is a waveform chart of each part for explaining the circuit operation of FIG. 7, and FIG. 9 is energy loss due to counter electromotive force in the counter electromotive force absorption diode. Fig. 10 shows the change in gain caused by the above, Fig. 10 is a waveform diagram for explaining the circuit operation of the compensation circuit that compensates the energy loss due to back electromotive force in the back electromotive force absorption diode, and Fig. 11 is such FIG. 12 is a diagram showing input / output characteristics of the compensation circuit, FIG. 12 is a block diagram showing another embodiment of the compensation circuit, and FIG. 13 is a diagram for explaining a conventional example and its operation. Explanation of symbols of main part 1 …… First constant current source 2 …… Second constant current source 3,9 …… Comparison circuit 8 …… Triangular wave generation circuit 15,16 …… Compensation circuit 17 …… Predrive circuit 18: Motor drive circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kimito Kobayashi 25 Nishimachi, Yamada, Kawagoe City, Saitama 1 Pioneer Co., Ltd. Kawagoe Factory (72) Inventor Akio Namiki 25, Nishimachi, Yamada, Kawagoe, Saitama Prefecture Address 1 Pioneer Co., Ltd. Kawagoe factory collegiate body Judgment chief Teruo Itomi Judge Jiro Akira Suzuki Judge Isao Tachikawa (56) Reference JP-A-60-153219 (JP, A)

Claims (1)

[Claims] 1. A load generating means for generating a drive pulse signal having a pulse width according to a drive signal signal level, and a drive current supplying means for supplying a drive current in positive and reverse directions to a load. Driving PWM that switches in forward and reverse directions
(Pulse width modulation) drive circuit, wherein the pulse generating means has two mutually opposite phases centered on a predetermined reference level and having predetermined maximum and minimum values as peak values.
(8) for generating a three-phase triangular wave signal, and outputs a first signal when the drive signal is greater than any of the two-phase triangular wave signals, and when the drive signal is less than any of the two-phase triangular wave signals Comparing means (9) for outputting a second signal, and determining the polarity of the drive signal with respect to a predetermined reference level,
Polarity discrimination means (12) for generating a forward direction permission signal or a backward direction permission signal after the triangular wave peak by the signal of the inversion means (4) which outputs an inverted signal for each peak of the triangular wave signal.
And each output signal from the comparison unit and the polarity determination unit as an input, and outputs the first signal as a drive pulse signal corresponding to the positive direction of the load when the forward direction permission signal is generated, Drive pulse generation means (13, 14) for outputting the second signal as a drive pulse signal corresponding to the reverse direction of the load when the reverse direction permission signal is generated, the drive current supply means A PWM drive circuit which supplies drive currents in positive and reverse directions according to the two drive pulse signals.