JPH0469449B2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a PWM (pulse width modulation) drive circuit, and in particular to a circuit that generates a pulse signal with a pulse width that corresponds to the signal level of a drive signal and switches a load based on this pulse signal. This invention relates to a single power supply PWM drive circuit.

Background technology As a method for driving loads such as motors,
A PWM bidirectional switching drive system is known. This drive method has excellent features of low loss and reduced power consumption, and is particularly useful for driving loads such as motors in vehicle-mounted devices, portable devices, etc. that use batteries as power sources.

Conventionally, as shown in FIG. 13, a PWM drive circuit uses two triangular wave signals a and b that are in phase with each other.
These triangular wave signals are used as reference inputs for the upper and lower limits of the comparator circuit 100 in a state where one of them a has a higher DC bias level than the other b, and the drive signal c is used as a comparison input. Obtaining a pair of pulse signals d and e with a pulse width corresponding to the signal level of the signal and corresponding to the driving direction of the load,
There was a structure in which the load was switched and driven based on the pair of pulse signals d and e.

In such a configuration, the tip portion of the triangular wave signal is used in a range where the signal level of the drive signal c is small. However, in the process of generating triangular wave signals, no amplifier has an infinite bandwidth;
It is unavoidable that ringing occurs at the tip of the triangular wave, or that so-called dulling occurs, so in conventional circuits that must use the tip of the triangular wave signal, it is difficult to avoid the input signal when the signal level of drive signal c is low. The disadvantage was that the linearity of the characteristics deteriorated.

Furthermore, when a PWM drive circuit is used to drive a load such as a motor in an in-vehicle device or a portable device, a battery is used as the power source for these devices, which is a so-called single power source, so the power supply voltage V _CC is /2, and the circuit is generally constructed using this 1/2V _CC as the circuit reference level. However, when a battery is used as a power source, the power supply voltage V _CC fluctuates rapidly, and the circuit reference level also fluctuates due to fluctuations in the power supply voltage. Therefore, countermeasures against fluctuations in the power supply voltage are desired.

Summary of the invention The present invention has been made in view of the above points, and
By using only the linear portion of the triangular wave signal to generate the pulse signal, the linearity of the input/output characteristics can be improved, especially when the signal level of the drive signal is small, and furthermore, stable operation can be achieved even with fluctuations in the power supply voltage. The purpose is to provide a PWM drive circuit that is capable of

The PWM drive circuit according to the present invention generates two-phase triangular wave signals having substantially equal peak values and opposite phases, and uses these two-phase triangular wave signals as reference inputs for the upper and lower limits of a comparison circuit, respectively. The circuit reference level and the DC bias level of the drive signal are set by dividing the same power supply voltage.

Embodiments Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

In FIG. 1, a first constant current source 1 is constituted by a current mirror circuit consisting of transistors Q ₁ and Q ₂ and resistors R ₁ and R ₂ . A second constant current source 2 connected in series with the first constant current source 1 is connected to the base via transistors Q ₃ and Q ₄ connected in parallel with each other, and these transistors Q ₃ and Q ₄ and a resistor R ₃ . It is constituted by a current mirror circuit consisting of a commonly connected transistor Q ₅ and emitter resistors R ₄ and R ₅ of each transistor, and the current is twice the constant current value I _O of the first constant current source 1. It is designed to suck in the value 2I _O. first and second constant current sources 1,
A capacitor C ₁ serving as a power storage means is connected between the common connection point of the two transistors, that is, the common connection point of the collectors of the transistor Q ₂ and the transistors Q ₃ and Q ₄ and the ground, which is a reference potential point.

The voltage across capacitor _C1 is the comparator
Comparison input of comparator circuit 3 which consists of COMP ₁ and COMP ₂ and monitors the voltage level, that is, comparator
Becomes the inverting input of COMP ₁ and the non-inverting input of COMP ₂ . Upper and lower comparison reference levels of comparison circuit 3
V _U and V _L are four resistors connected in series with each other
It is set by dividing the reference power supply voltage Vref by _R5 to _R8 . The resistors R ₅ to _{R 8} further divide the reference power supply voltage Vref into approximately 1/2, and output the voltage to 1/2 Vref via an operational amplifier OP ₁ having a voltage follower circuit configuration. Two comparison outputs of comparison circuit 3, i.e. comparator
The respective outputs of COMP ₁ and COMP ₂ become the set S and reset R inputs of the RS-flip-flop 4. The output of the flip-flop (hereinafter simply referred to as FF) 4 is supplied to a control circuit 5 comprising a transistor Q ₆ and resistors R ₉ and R ₁₀ and controlling activation/deactivation of the second constant current source 2. . This control circuit 5 is
The transistor Q ₆ turns on in response to the output of the FF 4 and turns the transistors Q ₃ and Q ₄ off, thereby deactivating the second constant current source 2.

The voltage across the emitter resistor _R5 in the second constant current source 2 is determined by the voltage follower circuit configuration operational amplifier _OP2.
This is the inverted input. In the operational amplifier OP ₂ , a comparison reference level is set by dividing the reference power supply voltage Vref by resistors R ₁₁ and R ₁₂ , and the comparison output is used to control the first and second constant current sources 1 and 2. It constitutes a current value setting circuit 6 that sets a constant current value.

The voltage across the capacitor C ₁ becomes the first phase triangular wave signal φa via the operational amplifier OP ₃ having a voltage follower circuit configuration, and is also transmitted to the operational amplifier OP ₄ and the resistor R ₁₃ ,
The phase of the _first
The second phase triangular wave signal φb is opposite in phase to the phase triangular wave signal φa. These triangular wave signals φa and φb have 1/
A DC bias of 2Vref is applied.

As described above, a triangular wave generation circuit 8 is configured which generates two-phase triangular wave signals φa and φb having substantially equal peak values and mutually opposite phases. This triangular wave generation circuit 8 is provided with a first constant current source 1 having a constant current value I _O and a second constant current source 2 having a constant current value 2I _O.
The circuit 8 is configured to generate a triangular wave by charging and discharging the capacitor _C1 with a constant current through on/off control of the constant current source 2.
When converting into an IC (integrated circuit), capacitor C ₁
One terminal pin (terminal 8 in Figure 1)
There is an advantage that a) is sufficient.

Two-phase triangular wave signals φa and φb are comparators
The comparison reference input of the upper and lower limits of the comparator circuit 9 consisting of COMP ₃ and COMP ₄ , that is, the comparator COMP ₃ ,
Becomes each inverted input of COMP ₄ . A drive signal for a load, such as a motor M, is supplied via a resistor _R15 as a comparison input of the comparison circuit 9, that is, as each non-inverting input of the comparators _COMP3 and _COMP4 . A resistor is installed at each non-inverting input terminal of comparators COMP ₃ and COMP ₄ .
The reference power supply voltage Vref is applied via R ₁₆ (R ₁₅ = R ₁₆ ), and the resistance values of resistors R ₁₅ and R ₁₆ are set equal, so that the drive signal is applied to the comparison input of the window comparator 9. At the point in time, it will be biased to 1/2Vref. That is, the signal reference level of the drive signal becomes 1/2Vref.

As a result, the circuit reference level of the triangular wave generation circuit 8, that is, the comparison reference level of the comparator circuit 3 and the DC bias level (signal reference level) of the drive signal are both set by the resistor division of the same reference power supply voltage Vref. That will happen. Therefore, even if the power supply voltage fluctuates, the relative signal level between the two-phase triangular wave signals φa and φb and the drive signal will always remain constant, so it will always be stable regardless of the power supply voltage fluctuation. The circuit operation will be performed accordingly.

The comparison output of comparator COMP ₃ becomes one input each of AND gate 10 and NOR gate 11, and the comparison output of comparator COMP ₄ becomes AND gate 10.
and the other inputs of the NOR gate 11. As a result, each output terminal of the AND gate 10 and the NOR gate 11 has a first output terminal corresponding to the driving direction of the motor M.
and a second pulse signal will be derived.

The aforementioned drive signal also serves as a non-inverting input of the comparator _COMP5 via the resistor _R15 . The comparator COMP ₅ has 1/2Vref as its inverted input, thereby forming a polarity determining means for determining the polarity of the drive signal with respect to the signal reference level. The judgment output of comparator COMP ₅ is the data D of D-FF12.
Use as input. D-FF12 uses the Q output of RS-FF4 in the triangular wave generation circuit 8 as a trigger T input,
Its Q output becomes one input each of AND gates 13 and 14. AND gates 13 and 14 correspond to the respective outputs of AND gate 10 and NOR gate 11, that is, the first
and a second pulse signal as other inputs, and constitute a gate means that outputs only one of the first and second pulse signals based on the Q and output of the D-FF 12.

Each output pulse of the AND gates 13 and 14 is supplied to compensation circuits 15 and 16 that compensate for energy loss due to back electromotive force of back electromotive force absorbing diodes D ₁ and D ₂ in a motor drive circuit 18 to be described later. In the compensation circuit 15, the output pulse of the AND gate 13 becomes the base input of the transistor _Q7 via the resistor _R17 , and this transistor _Q7
is connected in parallel with capacitor C ₂ . Capacitor _C2 is short-circuited at both ends when transistor _Q7 is turned on, and the charged charge is instantly discharged, causing the transistor
Charging is started by the constant current source Ia from the time when _Q7 is turned off, that is, from the time when the output pulse of the AND gate 13 disappears. The voltage across capacitor _C2 becomes the inverting input of comparator _COMP6 . The comparator COMP ₆ takes the reference voltage E _O as a non-inverting input and generates a high level pulse signal when the voltage across the capacitor C ₂ is lower than the reference voltage E _O. As a result, the compensation circuit 15 outputs a pulse signal in which a pulse with a substantially constant pulse width is added to the output pulse of the AND gate 13.

Similar to the compensation circuit 15, the compensation circuit 16 also has a resistor.
R ₁₈ , transistor Q ₈ , capacitor C ₃ , constant current source
Ib and a comparator COMP ₇ , and its operation is exactly the same as that of the compensation circuit 15.

Each output pulse of the compensation circuits 15 and 16 is sent to the motor drive circuit 18 via the predrive circuit 17.
is supplied to In the motor drive circuit 18, the motor M is connected to a PNP transistor _Q9 , an NPN transistor _Q10 , and a PNP transistor _Q11.
It is connected between the common connection points of the collectors of the NPN transistors _Q12 . Transistors Q ₉ , Q ₁₀ ,
Q ₁₁ and Q ₁₂ are power transistors. The emitters of transistors Q ₉ and Q ₁₁ are directly connected to voltage V _CC , and the bases of transistors Q 9 and Q 11 are connected to power supply V _CC through resistors R ₁₉ and R ₂₀ , respectively. On the other hand, the emitters of transistors Q ₁₀ and Q ₁₂ are both grounded, and the bases of each transistor are grounded via resistors R ₂₁ and R ₂₂ , respectively, and are connected to their collectors via Zener diodes ZD ₁ and ZD ₂ . . Both ends of the motor M are connected to a power supply V _CC via back electromotive force absorbing diodes D ₁ and D ₂ .

In the predrive circuit 17, the compensation circuit 15
The pulse signal supplied from the input terminal drives the power transistor Q ₉ through a predrive stage consisting of resistors R ₂₃ and R ₂₄ and a transistor Q ₁₃ , and after being inverted by an inverter 19, the pulse signal is sent to the resistors R ₂₅ to R ₂₇ and the transistor Q. The power transistor _Q12 is driven through a predrive stage consisting of ₁₄ . As a result, a current flows through the motor M in the direction of the arrow shown by the solid line in the figure, and the motor M is driven to rotate in the forward direction. Further, the pulse signal from the compensation circuit 15 is also supplied to the transistor _Q15 via the inverter 20, and turns on the transistor _Q15 when the motor M stops driving in the forward direction. As a result, the base and emitter of the power transistor _Q12 are short-circuited by the transistor _Q15 , so that the power transistor _Q12 is instantly turned off. The reason for providing this transistor _Q15 will be explained in detail later. The base of transistor Q ₁₅ is connected to the power supply V _CC through a resistor R ₂₈ .

On the other hand, the pulse signal supplied from the compensation circuit 16 drives the power transistor Q ₁₁ via a pre-drive stage consisting of resistors R ₂₉ and R ₃₀ and a transistor Q ₁₆ , and after being inverted by the inverter 21, the pulse signal is sent to the resistors R ₃₁ - Power transistor Q ₁₀ is driven through a predrive stage consisting of R ₃₃ and transistor Q ₁₇ . As a result, a current flows through the motor M in the direction of the arrow shown by the broken line in the figure, and the motor M is driven to rotate in the opposite direction. Further, the pulse signal from the compensation circuit 16 is also supplied to the transistor Q ₁₈ via the inverter 22, and turns on the transistor Q ₁₈ when the reverse direction drive of the motor M is stopped. As a result, the base and emitter of the power transistor _Q10 are short-circuited by the transistor _Q18 , so that the power transistor _Q10 is instantly turned off. The base of transistor Q ₁₈ is a resistor
Connected to power supply V _CC via R ₃₄ .

Next, the circuit operation of the PWM drive circuit according to the present invention will be explained.

First, the circuit operation of the triangular wave generation circuit 8 will be explained with reference to the waveform diagram of FIG. Triangular wave generation circuit 8
When the second constant current source 2 is in an inactive state, that is, when the transistor Q ₆ is on and the transistors Q ₃ and Q ₄ are off, the capacitor C ₁ is connected to the first constant current source 1. Due to the supplied constant current, the battery is charged with a constant tilt angle, as shown in FIG. 2a. When the voltage across capacitor C ₁ reaches the upper limit reference level V _U of comparator circuit 3, comparator COMP ₁ generates a low-level pulse b, and in response to this pulse b, the output d of RS-FF4 transitions to low level. do. As a result, the transistor Q ₆ is turned off, so the second constant current source 2 is activated, that is, the transistors Q ₃ and Q ₄ are turned on, and the constant current of the first constant current source 1 is twice as high. The current is absorbed.

As a result, the capacitor _C1 , which had been in a charging state until then, shifts to a discharging state, and as shown in FIG. 2a, the capacitor C1 is discharged at the same angle of inclination as during charging. Subsequently, when the voltage across the capacitor _C1 reaches the lower limit reference level _VL of the comparator circuit 3, the comparator _COMP2 generates a low level pulse c, and in response to this pulse c, the output d of the RS-FF4 goes high. Transition to level. This makes transistor _Q6
is turned on and the second constant current source 2 is deactivated, so that the capacitor _C1 is charged again with a constant slope angle by the constant current supplied from the first constant current source 1. It turns out.

In this way, by repeating the charging and discharging operation of the capacitor _C1 with the constant current from the first and second constant current sources 1 and 2, the voltage across the capacitor _C1 is increased as shown by the solid line in Figure 2b. The signal changes into _a triangular waveform as shown in FIG. It is output as a second phase triangular wave signal φb which has the same peak value as φa and has an opposite phase. These two-phase triangular wave signals φa and φb serve as reference inputs to the comparator circuit 9.

As a comparison input of the comparison circuit 9, a drive signal for the motor M having a signal reference level of 1/2Vref is supplied. Here, if the motor M is, for example, a spindle motor that rotationally drives a compact disk, the error signal obtained by comparing the reproduction synchronization signal from the disk with the reference synchronization signal becomes the drive signal, and this error signal The drive control of the spindle motor is performed based on this. This is the so-called spindle servo.

In Figure 3, the cross point of the two-phase triangular wave signals φa and φb is at the 1/2Vref level, and this 1/2
The PWM operation when the signal level of the drive signal is higher and lower than the 2Vref level will be described below.

In the comparator circuit 9, first, when the signal level of the drive signal is higher than the 1/2Vref level as shown by the dashed line in Figure a, the output b of the comparator COMP ₃ is a first phase triangular wave with respect to the signal level of the drive signal. At time t ₁ when the signal level of the signal φa becomes low, it transitions from a low level to a high level, and maintains the high level until time t ₄ when the signal level of the triangular wave signal φa exceeds the signal level of the drive signal. Also, the comparator
The output c of COMP ₄ is obtained at the time t ₂ when the signal level of the second phase triangular wave signal φb exceeds the signal level of the drive signal.
It changes from high level to low level at t3, and changes to high level again at time _t3 when it becomes lower than the signal level of the drive signal.

On the other hand, when the signal level of the drive signal is lower than the 1/2Vref level as shown by the two-dot chain line in Figure a and has the same absolute value level as in the above case, the output d of the comparator COMP ₃ is the first phase The signal level of the triangular wave signal φa transitions from low level to high level at time t ₂ when it exceeds the signal level of the drive signal, and the signal level remains high until time t ₃ when the signal level of the triangular wave signal φa exceeds the signal level of the drive signal. maintain. Furthermore, the output e of the comparator COMP ₄ transitions from high level to low level at time t ₁ when the signal level of the second phase triangular wave signal φb exceeds the signal level of the drive signal, and becomes lower than the signal level of the drive signal. At time t ₄ , it transitions to a high level again.

Each output of comparator COMP ₃ and COMP ₄ is
It has two inputs, an AND gate 10 and a NOR gate 11, and when both inputs of the AND gate 10 are at high level, that is, the signal level of the drive signal is 1/2.
When higher than the Vref level, the NOR gate 11 outputs a high-level pulse f, and when both of the two inputs are low level, that is, the signal level of the drive signal is 1/2Vref.
When it is lower than the level, a high level pulse g is output. Therefore, AND gate 10 and NOR gate 1
1 outputs pulse signals f and g corresponding to the driving direction of the motor M. Note that since we have explained here the case where the signal level of the drive signal is constant, the pulse width of the pulse signals f and g is constant, but it is not possible for this pulse width to change depending on the signal level of the drive signal. Easy to understand.

In this way, two-phase triangular wave signals φa and φb with equal peak values and opposite phases are generated, and the linear portions of these two-phase triangular wave signals φa and φb are used to perform PWM.
By performing this operation, even if ringing or so-called rounding occurs at the tip of the triangular wave, the linearity will not deteriorate at all when the signal level of the drive signal is small.

Here, if the reference power supply voltage Vref fluctuates,
The pulse width of the pulse signal generated by PWM changes, and the driving power generated by this pulse signal changes in accordance with fluctuations in the power supply voltage.
That is, as shown in Figure 4A, the pulse width of the pulse signal when the drive signal is at a certain signal level is
Assuming T _O , the driving power due to this pulse signal is
Its pulse width T _O and drive voltage V _D (reference power supply voltage
Vref), so if the drive voltage V _D is reduced to, for example, 1/2 due to fluctuations in the power supply voltage, the drive power will also be reduced to 1/2 as shown by the diagonal line.

However, in the triangular wave generation circuit 8, the first
and the comparison reference level of the current value setting circuit 6 that sets the constant current values of the second constant current sources 1 and 2 is the resistance R ₁₁ ,
The current value setting circuit 6 is set by dividing the reference power supply voltage Vref by _R12 , and the reference level also changes according to fluctuations in the power supply voltage. This means that the constant current values of the first and second constant current sources 1 and 2 can be controlled.
As a result, the inclination angle of the triangular wave changes as shown in FIG. 4B. On the other hand, the upper and lower comparison reference levels V _U and V _L of the comparator circuit 3 are also connected to the resistors R ₅ ~
Since it is set by dividing the reference power supply voltage Vref by _R8 , if the reference power supply voltage Vref becomes 1/2, the upper and lower limit comparison reference levels V _U and V _L will also be halved.
As a result, the peak value V _P of the triangular wave becomes 1/2 of the value before the power supply fluctuation, as shown in FIG. 4B. Therefore,
By setting the slope angle of the triangular wave so that the repetition period of the triangular wave is the same before and after the power fluctuation, a pulse signal with twice the pulse width (2T _O ) as before the fluctuation will be generated. Therefore, even if the drive voltage V _D is halved, the drive power generated by the pulse signal remains the same as before the power supply fluctuation.

That is, in the triangular wave generation circuit 8, by controlling the peak value and slope angle of the triangular wave according to fluctuations in the power supply voltage, the drive power generated by the pulse signal can always be kept constant regardless of fluctuations in the reference power supply voltage Vref. . Note that the slope angle of the triangular wave is the first
It is determined by the constant current values of the second constant current sources 1 and 2 and the capacitance of the capacitor _C1 .

Referring again to FIG. 1, if the signal level of the drive signal now changes as shown by the dashed line in FIG. are output from the AND gate 10 and the NOR gate 11, and become one input to each of the AND gates 13 and 14, respectively.
The drive signal also serves as a comparison input of the comparator COMP ₅ , and its polarity with respect to the signal reference level 1/2Vref is determined. The D-FF12, which uses the comparison output d of the comparator COMP ₅ as a data input, uses the Q output e of the RS-FF4 in the triangular wave generation circuit 8 as a trigger input. , g. This Q, outputs f and g are ANDed as gate control signals.
It is supplied to gates 13 and 14.

In addition, in the above embodiment, the Q output e of RS-FF4
was used as the direct trigger input for D-FF12, but
D-FF12 via a pulse generator that generates pulses at the rising and falling timings of the Q output e.
It is also possible to use it as a trigger input. According to this, the cycle of polarity discrimination is halved, and the resolution is reduced by 2.
You will be able to double it.

The Q and outputs f and g of the D-FF12 become control signals that determine the drive direction of the motor M. For example, when the signal level of the drive signal is small and its polarity changes from positive to negative, the output from the NOR gate 11 to the fifth
As shown in Figure c, for the reverse drive pulse signal (first pulse) that occurs instantaneously, the output g is at a low level at the time of generation, so
AND gate 14 operates to inhibit its output. The reason for this prohibition will be explained below.

Now, considering the case where the signal level of the drive signal is small and the polarity changes from positive to negative, a reverse drive pulse signal is instantaneously generated from the NOR gate 11 as shown in Fig. 5c. In the circuit 18, transistors Q ₉ and Q ₁₂ are turned on in response to the pulse signal shown in FIG. 5b, and drive the motor M in the forward direction, but the motor M is driven in the forward direction as shown in FIG. 5c. When the pulse signal is generated, transistors Q ₉ and Q ₁₂ are turned off, transistors Q ₁₁ and Q ₁₀ are turned on, and the motor M is driven in the opposite direction.

Generally, a transistor has a capacitance C _O between its base and emitter as shown in Fig. 6, so that the transistor that is in an on state in response to a driving pulse a is turned off from the time when the pulse a disappears. It has a characteristic that a delay time of t _OFF is required before the transition occurs. Therefore, as mentioned above,
By generating the reverse drive pulse signal shown in FIG. 5c, transistors Q ₉ and Q ₁₂ should be turned off and transistors Q ₁₁ and Q ₁₀ should be turned _on . _{Due to _ _} This may lead to destruction.

However, in this PWM drive circuit, AND gates 13 and 14 are provided, and these gates 13 and 14 are controlled based on the polarity determination result with respect to the signal reference level of the drive signal, so in the case of the above example, In response to the output g of the D-FF12, the output of the pulse signal of the reverse direction drive shown in Fig. 5c is
Since this can be inhibited by the AND gate 14, the transistor _Q12 will not be turned on at the same time as the transistor _Q11 .

Further, in order to reduce the delay time t _OFF of the power transistors Q ₁₂ and Q ₁₀ , the predrive circuit 17 is provided with transistors Q ₁₅ and Q ₁₈ . These transistors Q ₁₅ and Q ₁₈ are instantaneously turned on in response to the disappearance of the drive pulses of power transistors Q ₁₂ and Q ₁₀ , and by short-circuiting the bases and emitters of these transistors Q ₁₂ and Q ₁₀ , the above delay time is reduced. This makes it possible to shorten _tOFF . The delay time t _OFF of a transistor is generally about 1 to 2 μsec, but for transistors Q ₁₅ and Q ₁₈
By providing this, it is possible to shorten the time to about 1/10, that is, about 100 nsec.

Another embodiment for preventing the above-mentioned power transistors from turning on simultaneously is shown in FIG. In this figure, as mentioned earlier, the first and second pulse signals a corresponding to the driving direction of the motor M are sent to the AND gate 10.
and NOR gate 11, and these pulse signals are delayed by a predetermined time τ _O in delay circuits 23 and 24, respectively. These delayed outputs b are supplied to three-state buffers 25 and 26, respectively. Further, the first and second pulse signals a are also supplied to one-shot multivibrators 27 and 28, respectively. Oneshot Ramchi Vibrator 27,
28 is a delay circuit 23 for a certain period of time from the generation of the first and second pulse signals until their disappearance;
A low level output c is generated until a time (2τ _O ) twice the delay time τ _O of 24 has elapsed, and is supplied to the buffers 26 and 25 to output the second and second outputs from the delay circuits 24 and 23. Prohibits supply of the first pulse signal to the next stage.

FIG. 8 is an operational waveform diagram of the circuit of FIG. 7, and symbols a to c in the figure respectively indicate waveforms of signals a to c of FIG. 7, respectively. Referring to this waveform diagram, the circuit operation in FIG. 7 will be explained with respect to the AND gate 10 side, for example. Pulse signal a is delayed by time τ _O in delay circuit 23 and becomes drive pulse b for motor M. However, at this time, in response to the low-level inhibition signal c output from the one-shot multivibrator 27, the buffer 26 cuts off the output line of the other drive pulse. As a result, the output of the other drive pulse is prohibited for a certain period (time τ _O ) before and after the generation of drive pulse b, so that the time τ _O is determined by the power transistors Q ₁₂ and Q ₁₀ described above. By setting the delay time t longer than _OFF , the power transistor
Q ₉ and Q ₁₀ (or Q ₁₁ and Q ₁₂ ) are never in the on state at the same time.

Note that, as described above, since the delay time t _OFF of a transistor is generally about 1 to 2 μsec, it is desirable to set the time τ _O to about 5 μsec.

In FIG. 1, first and second pulse signals corresponding to the drive direction of motor M output from AND gates 13 and 14 are supplied to compensation circuits 15 and 16, respectively. These compensation circuits 15 and 16 are for compensating for energy loss in the back electromotive force absorbing diodes D ₁ and D ₂ in the motor drive circuit 18 . Diode for absorbing back electromotive force
The energy loss in D ₁ and D ₂ is almost constant,
When the pulse width of the pulse signal is large, the loss can be ignored, but when the pulse width is small, the loss ratio becomes large. Therefore, as shown by the broken line in Figure 9, the gain decreases in the region where the pulse width of the pulse signal is small, so when the pulse width is small, the back electromotive force absorbing diode is
All that is required is to compensate for the energy loss in D ₁ and D ₂ .

Here, regarding the circuit operation of the compensation circuit 15, the first
To explain with reference to the waveform diagram in Figure 0, the capacitor _C2 is charged with a constant current by the constant current source Ia, and the transistor C2 is charged in response to the input pulse a.
By turning on Q ₇ , capacitor C ₂
The stored charge is instantaneously discharged, and from the time when the input pulse a disappears, the capacitor _C2 is charged again with a constant current. Therefore, the voltage across capacitor _C2 changes as shown in FIG. 10b. This voltage b at both ends is compared with the reference voltage E _O by the comparator COMP ₆ , and as a result, the voltage at the output terminal of the comparator COMP ₇ is displayed for a certain period of time from the generation of the input pulse a to its extinction.
A pulse signal c having a pulse width of time until Ta elapses is obtained. That is,
A constant pulse width Ta is added to the input pulse a, and this added pulse width Ta
The energy loss in the back electromotive force absorbing diodes D ₁ and D ₂ can be compensated by the energy equivalent to the amount of energy.

FIG. 11 shows the input/output characteristics of the compensation circuits 15 and 16, that is, the relationship between the pulse width of the input _pulse and _the added pulse width. In the pulse width region where the input pulse cannot drop to _O , there is no additional pulse width, but in the region where the input pulse falls below the reference voltage E _O , the additional pulse width changes proportionally and reaches the zero level. In the subsequent areas, the added pulse width becomes a fixed width. In other words, in a region where the pulse width of the input pulse is extremely small, there is no additional pulse width, or the additional pulse width changes proportionally, but this is because the rise and fall of the input pulse are not steep but are actually gentle. As a result, the gain can be improved within the range as shown by the solid line in FIG.

The compensation circuits 15 and 16 are not limited to the configurations of the above embodiments, but, for example, as shown in FIG. It may be configured to include a pulse generation circuit 29 that generates a pulse, and an OR gate 30 that takes the logical sum of the output pulse of the pulse generation circuit 29 and the input pulse. In such a configuration, when the pulse width of the input pulse is smaller than the above pulse width Tb,
By constantly outputting a pulse signal having the pulse width Tb from the OR gate 30, compensation for energy loss in the back electromotive force absorption diodes D ₁ and D ₂ when the pulse width of the input pulse is small is performed. , the pulse width of the input pulse is the above pulse width Tb
When it is larger, no change in pulse width is made to the input pulse.

In the above embodiment, the case where the application is applied to a drive circuit of a spindle motor that rotationally drives a compact disc has been described, but the invention is not limited to this, and it is applicable to a carriage motor that drives a pickup, a focus of information reading light in a pickup, etc. It can also be applied to drive circuits for focus actuators and tracking actuators that control tracking, and can be widely applied not only to compact disc players but also to drive circuits for various loads in various devices. .

Effects of the Invention As explained above, according to the PWM drive circuit according to the present invention, only the linear portion of the triangular wave signal is used to generate the pulse signal that drives the load. Even if the signal level is delayed or rounded, the linearity of the input/output characteristics can be improved, especially when the signal level of the drive signal is small, without being affected by these effects at all.

In addition, since the circuit reference level and the DC bias level of the drive signal are set by dividing the same power supply voltage, even if the power supply voltage fluctuates in one power supply,
In the pulse signal generation stage, the relative signal level of the triangular wave signal and the drive signal is always kept constant, so that stable circuit operation is always performed regardless of fluctuations in the power supply voltage.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a waveform diagram of each part to explain the circuit operation of the triangular wave generation circuit in Figure 1. Figure 3 is a waveform diagram of each part to explain the operation of generating two pulse signals corresponding to the drive direction of the load by PWM operation. , 4th
Figures A and B are waveform diagrams to explain the operation of changing the slope angle and peak value of the triangular wave in response to fluctuations in the power _supply voltage. Figure 6 is a diagram to explain the t _OFF delay time of the transistor, and Figure 7 is a block diagram showing another embodiment of the simultaneous ON prevention circuit. 8 is a waveform diagram of each part to explain the circuit operation of FIG. 7, FIG. 9 is a diagram showing changes in gain due to energy loss due to back electromotive force of the back electromotive force absorption diode, and FIG. The figure is a waveform diagram for explaining the circuit operation of a compensation circuit that compensates for energy loss due to back electromotive force in a back electromotive force absorption diode, Figure 11 is a diagram showing the input/output characteristics of such a compensation circuit, and Figure 12 The figure is a block diagram showing another embodiment of such a compensation circuit, and FIG. 13 is a diagram for explaining a conventional example and its operation. Explanation of symbols of main parts, 1...first constant current source, 2...second constant current source, 3, 9...comparison circuit, 8...triangular wave generation circuit, 15, 16...compensation circuit, 17... Predrive circuit, 18... Motor drive circuit.

Claims (1)

[Claims] 1 A PWM (Pulse Width Width) system in which a predetermined reference power supply voltage is supplied by one power source, a pulse signal with a pulse width corresponding to the signal level of a drive signal is generated, and a load is switched and driven based on this pulse signal. a triangular wave generation circuit that generates two-phase triangular wave signals having substantially equal peak values and opposite phases; the two-phase triangular wave signals are used as upper and lower limit reference inputs, respectively; a first comparator circuit serving as a comparison input, the pulse signal is generated based on the output of the comparator circuit, and the circuit reference level of the triangular wave generation circuit and the DC bias level of the drive signal are both connected to the reference power supply. PWM characterized by being set by voltage division
drive circuit. 2. The triangular wave generation circuit includes a first constant current source;
connected in series with the first constant current source and the first
a second constant current source that draws twice as much current as the constant current source; a power storage means connected between a common connection point of the first and second constant current sources and a reference potential point; a second comparison circuit for monitoring the output level of the means; and a control means for controlling activation/deactivation of the second constant current source based on the output of the second comparison circuit; 2. The PWM drive circuit according to claim 1, wherein the comparison reference level of the second comparison circuit is the circuit reference level.