JPH0710065B2 - Digital exchange system - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Outline Industrial field of application Conventional technology Problems to be solved by the invention Means for solving problems Action Example I. Correspondence between example and FIG. II. Configuration of the embodiment III. Operation of the embodiment IV. Summary of the embodiment V. Modified embodiment of the invention [Effect of the invention] [Outline] Regarding the digital switching system, prevent out-of-synchronization even if the system is switched. For the purpose of the above, the data based on the second transmission rate (different from the first transmission rate) is applied to the relay line by the processing means to which the digital exchange means of the two systems for receiving the data based on the first transmission rate are connected in common. In the digital exchange system for outputting the data, the processing means switches the data of the two systems and outputs the data input signal, and the processing means switches the clock based on the first transmission rate corresponding to the two systems. A selection unit that outputs a clock signal, a timing generation unit that outputs a write clock and a clock divided signal based on the first clock signal, and a read clock that corresponds to the second transmission rate based on the clock divided signal. The read clock generating means and the data storing means for writing the data by the write clock and reading the data by the read clock are provided.

[Industrial application field]

 The present invention relates to a digital switching system.

[Conventional technology]

The bit rate in the known PCM-24 system digital transmission line is
It is 1.544 Mbit / s (hereinafter simply referred to as 1.5 Mbit / s). By the way, the internal processing is based on the PCM-30 system and the processing speed is 8.192 Mbit / s (hereinafter simply referred to as 8 Mbit / s). When relaying with a station, it is necessary to convert the bit rate.

As such an example, consider a digital exchange that relays with other stations, as shown in FIG. As an example of this digital exchange, a plurality of subscribers 311 are accommodated in a concentrating stage 313, in which DSM (Digital Switch Module) 315 ₀ and “1” of “0” system (indicated by # 0) independent from each other are provided.
Two DSM315s of the "system" (shown by # 1) DSM315 ₁ are connected. In addition, DTC (Digital Termi) corresponding to DSM315
nal Common) 317 ₀ and DTC 317 ₁ are connected respectively.

Here, for each DTC317, 8Mbit / from each DSM315
s data and clock etc. are supplied. 8Mbit / s
The frequency corresponding to the transmission speed of 8MHz (actually 8.192MHz
3MHz (actually 3.088MHz)
Is a phase-locked loop circuit (PLL) 319 (PLL319 ₀ and PLL319 ₁ ) for generating the clock.
The data transmitted at the clock of 3 MHz and the data of 8 MHz are commonly supplied to, for example, five DTs (Digital Terminals) 321. However, here one DT
Only 321 is shown.

As mentioned above, in the digital transmission line of the PCM-24 system, since the bit rate is different, 8M from DSM315
It is necessary to convert bit / s to 1.5 Mbit / s x 5. Such bit rate conversion is performed in the DT321.

In other words, DT321 has Elastic Store Memory (ES) 3
23 is provided, and 8 Mbit / s data is written in this ES 323 as needed according to a clock of 8 MHz. After that, the data written in the ES323 is read according to the clock of 1.5 MHz (the clock obtained based on the clock of 3 MHz). As a result, each channel is output as a PCM signal in a synchronized state. This output P
The CM signal is transmitted to other stations (other digital exchanges, etc.) by the PCM-24 link.

FIG. 5 shows the details of the DT321 that performs the bit rate conversion operation from 8 Mbit / s to 1.5 Mbit / s as described above. FIG. 6 shows the operation.

In both figures, a multi-frame clock (defined by an 8 MHz clock) supplied from two DSM315s of "0 series" DSM315 ₀ (shown as # 0) and "1 series" DSM315 ₁ (shown as # 1). 16 frames of frames) are selectors
Introduced at 411 _K. Here, 1 multiframe is 1.5ms
Equivalent to the time width of. Also, the voice data (8 Mbit / s) from the "0 system" DSM 315 ₀ and the "1 system" DSM 315 ₁ is introduced to another selector 411 _D.

One of the multi-frame clocks selected by the selector 411 _K is supplied to the timing generator 413. The timing generator 413 is a counter that sequentially counts the introduced multi-frame clocks, and the count value is “12”.
Then, a sync signal indicating one multi-frame is generated. In response to this synchronization signal, the frame synchronization pattern generation unit 415 at the next stage generates a "frame synchronization pattern", and the frame synchronization pattern is the synchronization pattern insertion unit.
Supplied to 417. The synchronization pattern insertion unit 417 is a selector
"0 system" or "1" obtained by selecting by 411 _D
The frame synchronization pattern is inserted into the data from one of the "systems".

In the PCM-24 system, all 24 channels are used for voice, there is no dedicated channel for "individual signal", and each "individual signal" is set to the 8th bit of each channel of frame 6 and frame 12. "Insert. Therefore, the audio data has 7 bits.

The DTC unit in such a PCM-24 terminal device has a PLL and a counter for 12 frames, and the DTC has a frame 6,
"Individual signal" to the 8th bit of each channel of frame 12
Was being inserted. Therefore, it is necessary to send the multi-frame clock in order to recognize the frame number to the DT that performs processing such as synchronization pattern insertion.

By the way, when a digital exchange is installed in a transmission system based on the PCM-30 system to perform relay with other stations, if the transmission speed on the digital transmission line is 8.192 Mbit / s, the DSM side in the digital exchange will receive Among the 8 Mbit / s data (128 channels), there are channels that include "individual signals" indicating the state of each channel in addition to audio data (120 channels).

Therefore, when based on the PCM-24 system, "individual signal"
And it is necessary to insert the synchronization pattern.

[Problems to be solved by the invention]

By the way, in the above-mentioned conventional system, the bit rate conversion is performed by the "single" DTC 321 according to the "duplex" DTC 317.

That is, as described above, in the known digital transmission system
In a PCM-24 digital exchange, it is necessary to convert the bit rate from 8 Mbit / s to 1.5 Mbit / s. Therefore, the DTC321 uses the 3 MHz clock obtained from the PLL319 included in the DTC317.

By the way, frame synchronization is caught between the DTC317 ₁ of the "duplex" is "0 system" and DTC317 ₀ of "1 system", not necessarily the synchronization is taken of the multi-frame.

If the multi-frames from the two DTC317 are not synchronized, the clock will be switched for some reason (switching from the "0 system" DTC317 to the "1 system" DTC317 ₁ or vice versa). When you do
Loss of synchronization occurs in the PCM link based on the PCM-24 system. That is, as shown in FIG. 6, when the multi-frames in the "0 system" and the multi-frames in the "1 system" are shifted from each other, when the "0 system" is switched to the "1 system", The counter of the timing generation unit 413, which has been counting based on the multi-frame clock in the “0 system” until then, continues counting based on the multi-frame clock in the “1 system”. The counter will have its count value jumped. Therefore, the timing of generation of the synchronization signal from the timing generation unit 413 is shifted based on the count of the counter, and the "frame synchronization pattern" insertion time in the synchronization pattern insertion unit 417 is different every 12 frames. . Therefore, as a result, due to the deviation of the transmission timing from DT321, the input P
There was a problem that out-of-sync occurred in the CM signal, a warning to that effect was generated, and normal data transmission could not be performed.

The present invention has been made in view of such a point, and an object thereof is to provide a digital exchange system in which out-of-synchronization does not occur even when two systems are switched.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the digital exchange system of the present invention.

In the figure, in the digital exchange system according to the present invention, the digital exchange means 111 of two systems for receiving data based on the first transmission rate transmitted from the outside is processed by the processing means 113 connected in common. The data based on the second transmission rate is output to the relay line connected to the processing unit 113, and the first transmission rate and the second transmission rate are different from each other.

Processing means 113 in such a digital exchange system
Is a selection means 123, a selection means 127, a timing generation means 13
3, read clock generation means 137, data storage means 139
It is equipped with

The selection means 123 switches the data introduced from the digital exchange means 111 of the two systems and outputs the data input signal 121.

The selection means 127 switches the first clock based on the first transmission rate corresponding to the digital exchange means 111 of the two systems and outputs the first clock signal 125.

The timing creating means 133 divides the write clock signal 129 and the first clock signal 125 having the repetition frequency corresponding to the first clock and outputs the clock divided signal 131.

The read clock creating means 137 uses the clock divided signal 131
, And outputs the read clock signal 135 based on the second transmission rate in a desired frequency ratio relationship.

The data storage means 139 writes data by the data input signal 121 by the write clock signal 129 and reads by the read clock signal 135.

The data read by the read clock signal 135 is the data output to the relay line.

Therefore, as a whole, in the processing means 113, the data transmission rate is configured to be converted from the first transmission rate to the second transmission rate.

[Action]

In the digital exchange system of the present invention, the first clock based on the first transmission rate corresponding to the digital exchange means 111 of the two systems is switched to obtain the first clock signal 125, which corresponds to the first clock. The write clock signal 129 and the first clock signal 125 having the repetition frequency are divided to obtain the clock divided signal 131.

The read clock signal 135 based on the second transmission speed is obtained in phase-lock with the clock divided signal 131 and in a desired frequency ratio relationship.

In the data storage means 139, data is written by the write clock signal 129 and data is read by the read clock signal 135. The data read by the read creating means 137 is the data output to the relay line.

In the present invention, since the data transmission rate is converted from the first transmission rate to the second transmission rate in the processing means 113, the synchronization is not lost even when the system is switched.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the configuration of the digital exchange system in one embodiment of the present invention. FIG. 4 shows a digital exchange which interfaces with a digital transmission line of the PCM-24 system. FIG. 5 shows a configuration for converting the bit rate to the PCM-24 system.

I. Correspondence between Embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be described.

The digital exchange means 111 includes DSM315 ₀ , DSM315 ₁ , DTC317 ₀ , D
Equivalent to TC317 ₁ .

The processing means 113 corresponds to DT321.

The data input signal 121 is switched by the selector 211 and ES
This corresponds to audio data input to 223.

The selection means 123 corresponds to the selector 211.

The first clock signal 125 corresponds to the 8 MHz clock switched by the selector 211 and input to the first timing generator 233.

The selection means 127 corresponds to the selector 211.

The write clock signal 129 is the write clock signal 2
Equivalent to 31.

The clock divided signal 131 corresponds to the clock divided output signal 232.

The timing generation unit 133 corresponds to the first timing generation unit 233.

The read clock signal 135 is the frequency conversion clock signal 2
Equivalent to 39.

The read clock creating means 137 corresponds to the PLL 237 and the second timing generator 241.

The data storage unit 139 corresponds to ES223.

An embodiment of the present invention will be described below on the basis of the above correspondence.

II. Configuration of Embodiments The embodiments of the present invention also relate to a portion for converting the bit rate from 8 Mbit / s to 1.5 Mbit / s in the digital exchange that interfaces with the above-described known PCM-24 digital transmission line. In other words, in the digital exchange
It is DT321. Since other parts are the same, detailed description thereof will be omitted. However, PLL319 is not necessary in DTC317.

In Figure 2, the "duplex""0" DTC3
17 ₀ and two DTC317 of "1 series" DTC317 ₁ (see Fig. 3)
Receives audio data (8Mbit / s), frame clock signal and 8Mbit / s clock signal supplied from
Selector 211 for switching and selecting either "system" or "1 system", elastic store memory (ES) 223 in which the data obtained by switching and selecting by the selector 211 is written, and selector 211 for switching and selecting The write clock signal 231 (8MH
z) and a first timing generator 233 that generates a clock divided output signal 232 (8 kHz), and a clock divided output signal 232.
Phase locked output signal 235 (1.5MH
z), a second timing generator 241 for generating a frequency-converted clock signal 239 for reading data in the ES223 based on the phase-locked output signal 235, and a frequency And a processing unit 243 that puts data on the PCM-24 link according to the converted clock signal 239. The processing unit 243 corresponds to the frame synchronization pattern generation unit 415 and the synchronization pattern insertion unit 417 shown in FIG.

The second timing generator 241 outputs 251 of 8 kHz and feeds back to the PCM 237.

III. Operation of Embodiment Next, the operation of the above-described configuration will be described.

In FIG. 2, voice data (8 Mbit / s) in a digital exchange interfaced with a PCM-24 digital transmission line is supplied from "redundant""0system" and "1 system". .

Now, it is assumed that the selector 211 selects "0 system". Then, the "0" audio data, the 8 MHz clock and the frame clock are selected together.

Therefore, the audio data of "0 system" (8Mbit / s) is the first
Write clock signal 231 from the timing generator 233
Written according to (8MHz). Further, the data written in the ES 223 in this way is read according to the frequency conversion clock signal 239 from the second timing generator 241. Thereafter, the processing unit 243 performs necessary processing such as inserting a synchronization pattern.

In addition, by selector 211, "1 system" voice data, 8MHz
When both the clock and the frame clock are selected, the writing and reading of data in the ES 223 and the desired processing in the processing unit 243 are still performed according to them.

By the way, regarding the ES223, since the audio data of 8 Mbit / s is written and the read data is 1.5 Mbit / s, the data transmission rate is converted in the meantime. As a result, the bit rate is being converted. The circuit portion for obtaining the frequency-converted clock signal 239 for performing the bit rate conversion is characterized by the embodiment of the present invention.

That is, the first timing generation unit 23 is operated according to the 8 MHz clock and the frame clock of the "0 system" or "1 system".
In 3, the clock frequency division output signal 232 of 8 kHz is obtained. Here, the 8.192 MHz clock is divided into 8.000 KHz, and the rectangular wave is output as the clock divided output signal 232.

Also, the 251 fed back from the second timing generation unit 241 is also 8k.
It has a square wave at Hz.

These clock division output signals 232 and 251 are introduced.
The PLL 237 naturally includes an oscillator whose oscillation frequency changes according to the phase difference between the clock divided output signals 232 and 251. The frequency of the oscillation output is 1.
It becomes 5MHz. Phase locked output signal output at that frequency
235 is supplied to the second timing generator 241 in the next stage.

In the second timing generator 241 to which the phase lock output signal 235 is introduced, the input 1.5 MHz signal has the same frequency as the input frequency and has the desired synchronization timing with respect to the ES 223 and the processor 243. Then, the frequency conversion clock signal 239 is generated. Also, the phase-locked output signal 235 is frequency-divided to output an 8 kHz feedback signal 251, which is supplied to the PLL 237.

The PLL 237 automatically changes the phase difference so that the phase is locked based on the clock divided output signal 232 and the feedback signal 251.

In this way, the frequency conversion clock signal 239 required for bit rate conversion is obtained by the PLL 237 based on the 8 MHz clock and the frame clock.

In this way, the bit rate is converted, and the processing unit 243 places the voice data on the PCM-24 link and transmits it to the opposite station.

As a result, as shown in FIG. 3, even when the act system is switched from “# 0” to “# 1”, the frequency conversion clock signal 239 is generated based on the switched 8 MHz clock and frame clock. As a result, the data is read out and inserted in the synchronization pattern in a synchronized manner.

IV. Summary of Embodiments As described above, the PLL for generating the 3 MHz clock and the multi-frame clock in the PCM-24 system has the D in the “single” part.
Since it is installed in the T321, even if the DSM315 (DTC317) is switched, the PCM-24 system multi-frame clock does not shift.

Therefore, the generation timing of the synchronization signal from the timing generation unit 413 (second timing generation unit 241) does not shift on the basis of the count in the counter, and the synchronization pattern insertion unit 417 (processing unit 243) performs the operation every 12 frames. The "frame synchronization pattern" of is generated and the transmission timing from the DT321 does not shift. In the opposite station, out-of-sync does not occur in the input PCM signal, and normal data transmission can be performed.

V. Modified Embodiment of the Invention Although the correspondence between the present invention and the embodiments has been described in “I. Correspondence between Embodiments and FIG. 1”, the present invention is not limited to this. However, it will be easily understood by those skilled in the art that there are various modifications.

〔The invention's effect〕

As described above, according to the present invention, since the data transmission rate is converted from the first transmission rate to the second transmission rate in the processing means after the system is switched, the synchronization is lost even when the system is switched. It is extremely useful in practice because it never happens.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the digital switching system of the present invention, FIG. 2 is a block diagram of the configuration of the digital switching system according to one embodiment of the present invention, and FIG. 3 is a system switching in the digital switching system shown in FIG. FIG. 4 is an explanatory diagram of a digital exchange in the PCM-24 system, FIG. 5 is an explanatory diagram of a configuration for performing bit rate conversion in the PCM-24 system, and FIG. FIG. 7 is an explanatory diagram showing an operation when system switching is performed in the conventional digital exchange system. In the figure, 111 is a digital exchange means, 113 is a processing means, 121 is a data input signal, 123 is a selection means, 125 is a first clock signal,
127 is a selection unit, 129 is a write clock signal, 131 is a clock frequency division signal, 133 is a timing generation unit, 135 is a read clock signal, 137 is a read clock generation unit, 1
39 is a data storage means, 211 is a selector, 223 and 323 are elastic store memories (ES), 231 is a write clock signal, 233 is a first timing generator, 237 and 319 are phase locked loop circuits (PLL), and 239 is a frequency conversion clock. Signal, 241 is the second timing generation unit, 243 is the processing unit, 311 is the subscriber, 313 is the concentrating stage, 315 is DSM, 317 is DTC, 321 is DT,
Reference numeral 415 is a frame synchronization pattern generation unit, and 417 is a synchronization pattern insertion unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Sonoda 1-5-1 Hakataekimae, Hakata-ku, Fukuoka-shi, Fukuoka Prefecture Fujitsu Kyushu Communication Systems Limited (72) Hideo Fujita Hakata-ekimae, Hakata-ku, Fukuoka-shi, Fukuoka 1-5-1 Fujitsu Kyushu Communication Systems Co., Ltd. (56) Reference JP-A-63-9247 (JP, A) JP-A-62-262539 (JP, A) JP-A-61-214698 (JP, A) )

Claims (1)

[Claims] 1. A two-system digital exchange means for receiving data based on a first transmission rate transmitted from the outside.
The processing means (113) connected in common to (1) outputs data based on the second transmission rate to the relay line connected to the processing means (113), and the first transmission rate and the second transmission rate. In the digital exchange system in which the and are different from each other, the processing means (113) selects the data input signal (121) by switching the data introduced from the digital exchange means (111) of the two systems. (123), a selection means (127) for switching a first clock based on a first transmission rate corresponding to the digital exchange means (111) of the two systems and outputting a first clock signal (125), A write clock signal (129) having a repetition frequency corresponding to one clock and the first clock signal (12
5) timing generation means (133) for frequency-dividing and outputting a clock frequency-divided signal (131), and the second transmission in phase-lock with the clock frequency-divided signal (131) and in a desired frequency ratio relationship. A read clock generation means (137) for outputting a read clock signal (135) based on the speed, and data written by the data input signal (121) is written by the write clock signal (129) and by the read clock signal (135). A data storage means (139) for reading, and the read clock signal (13
A digital exchange system, wherein the data read by 5) is data output to the relay line.