JPH07101773B2 - Semiconductor device mounting method - Google Patents
Semiconductor device mounting methodInfo
- Publication number
- JPH07101773B2 JPH07101773B2 JP1196845A JP19684589A JPH07101773B2 JP H07101773 B2 JPH07101773 B2 JP H07101773B2 JP 1196845 A JP1196845 A JP 1196845A JP 19684589 A JP19684589 A JP 19684589A JP H07101773 B2 JPH07101773 B2 JP H07101773B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor devices
- terminals
- solder resist
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、プリント基板に対する半導体装置の実装方法
に関するものである。The present invention relates to a method for mounting a semiconductor device on a printed circuit board.
[従来の技術] 従来、半導体装置が実装されるプリント基板は、導電パ
ターンが施された合成樹脂製の基板の全両面に、防湿、
防塵、導電パターンの剥離防止などのためアクリル樹脂
からなるソルダレジストを塗布してあり、半導体装置や
電気部品を実装する場合は、導電パターン上のソルダレ
ジストを除去して露出させ、この部分に半導体装置その
他の電気部品の端子をはんだ付けしていた。[Prior Art] Conventionally, a printed circuit board on which a semiconductor device is mounted has moisture-proof,
Acrylic resin solder resist is applied to prevent dust and peel off of the conductive pattern.When mounting semiconductor devices or electrical parts, remove the solder resist on the conductive pattern to expose the semiconductor The terminals of the device and other electrical parts were soldered.
この場合、半導体装置の多数の端子をボンディングツー
ルで同時に導電パターンに接続することもある。In this case, a large number of terminals of the semiconductor device may be simultaneously connected to the conductive pattern by a bonding tool.
上記のような従来のプリント基板においては、半導体装
置の実装にあたって半導体装置の端子が接続される導電
パターン上のソルダレジストを除去して露出させなけれ
ばならないので、除去作業がきわめて面倒で、多くの工
数を要するばかりでなく、ソルダレジストの除去が不完
全な場合は、接続不良を生ずることもある。In the conventional printed circuit board as described above, when the semiconductor device is mounted, the solder resist on the conductive pattern to which the terminals of the semiconductor device are connected must be removed and exposed. Not only the number of steps is required, but incomplete removal of the solder resist may result in connection failure.
このような問題を解決するために、例えば、特開昭63−
299397号公報には、プリント基板の表面に、端子を含む
半導体装置の表面積より若干広い範囲を除いてソルダレ
ジストを塗布し、ソルダレジストが塗布されていない領
域に半導体装置を載置して領域内に露出している導電パ
ターンに端子を接続するようにした半導体集積回路の実
装基板が開示されている。In order to solve such a problem, for example, Japanese Patent Laid-Open No. 63-
In the 299397 publication, a solder resist is applied on the surface of a printed circuit board except a region slightly larger than the surface area of a semiconductor device including terminals, and the semiconductor device is placed in an area where the solder resist is not applied and There is disclosed a mounting board of a semiconductor integrated circuit in which a terminal is connected to a conductive pattern exposed on the substrate.
[発明が解決しようとする課題] 上記のような半導体集積回路の実装基板は、半導体装置
の実装にあたってソルダレジストの除去作業を省略でき
るので、その分工数を節減することができる。[Problems to be Solved by the Invention] Since the solder resist removing operation can be omitted when mounting the semiconductor device on the semiconductor integrated circuit mounting substrate as described above, the number of steps can be reduced.
しかしながら、プリント基板には、通常、第4図及び第
5図に示すように、プリント基板1上に複数の半導体装
置4,4a,4b,4cがランダムに実装されるため、ボンディン
グツールで導電パターン2に半導体装置4〜4cの端子5
を接続する場合に位置決めが面倒であり、その上半導体
装置4〜4cの大きさが異なる場合は、その都度ボンディ
ングツールを交換しなければならないので、きめわめて
面倒である。However, as shown in FIGS. 4 and 5, a plurality of semiconductor devices 4, 4a, 4b, 4c are normally randomly mounted on the printed circuit board 1 on the printed circuit board. 2 to terminals 5 of semiconductor devices 4 to 4c
However, if the semiconductor devices 4 to 4c have different sizes, the bonding tool has to be replaced each time, which is very troublesome.
また、ソルダレジストの非塗布部分6は各半導体装置4
〜4cごとにそれぞれ独立して設けられているので、隣接
する半導体装置との間に設けられたソルダレジストの塗
布部分がボンディングツールの妨げになり、導電パター
ンと半導体装置の端子とを確実に接続できないことがあ
る。In addition, the non-coated portion 6 of the solder resist is used for each semiconductor device 4
Since each ~ 4c is provided independently, the solder resist application part provided between adjacent semiconductor devices interferes with the bonding tool, and the conductive pattern and the terminals of the semiconductor device are securely connected. There are things you can't do.
本発明は、上記の課題を解決すべくなされたもので、プ
リント基板上に複数の半導体装置を一列に並べて実装す
るにあたり、ソルダレジストを除去する作業を省略し、
その上導電パターンと半導体装置の端子との接続不良を
生ずるおそれがなく、ボンディングツールによるボンデ
ィングも容易な半導体装置の実装方法を得ることを目的
としたものである。The present invention has been made to solve the above problems, in mounting a plurality of semiconductor devices arranged in a line on a printed circuit board, omitting the work of removing the solder resist,
Moreover, it is an object of the present invention to provide a method for mounting a semiconductor device that does not cause a connection failure between the conductive pattern and a terminal of the semiconductor device and can be easily bonded by a bonding tool.
[課題を解決するための手段] 本発明に係る半導体装置の実装方法は、対向する第1及
び第2の方向にそれぞれ群をなして端子が突出した複数
の半導体装置を、導電パターンが設けられたプリント基
板に実装する半導体装置の実装方法において、複数の半
導体装置の第1の方向に突出した第1端子群の全表面積
よりも若干広く接続した第1領域と、複数の半導体装置
の第2の方向に突出した第2端子群の全表面積よりも若
干広く連続した第2領域とを、端子の突出部間の長さと
ほぼ等しい間隔を隔ててプリント基板の表面にそれぞれ
設け、プリント基板の第1及び第2領域を除く表面にソ
ルダレジストを塗布し、第1領域と第2領域との間に複
数の半導体装置を一列に配設し、かつ端子を第1及び第
2領域内に露出している導電パターンにそれぞれ接続す
るようにしたものである。[Means for Solving the Problems] In the method for mounting a semiconductor device according to the present invention, a plurality of semiconductor devices each having a terminal protruding in a group in the opposing first and second directions are provided with a conductive pattern. In a method of mounting a semiconductor device mounted on a printed circuit board, a first region connected to the semiconductor device slightly larger than a total surface area of a first terminal group protruding in a first direction of the plurality of semiconductor devices, and a second region of the plurality of semiconductor devices. A second region that is slightly wider than the total surface area of the second terminal group and that extends in the direction of the second terminal group is provided on the surface of the printed circuit board at a distance substantially equal to the length between the protruding portions of the terminals. Solder resist is applied to the surface excluding the first and second regions, a plurality of semiconductor devices are arranged in a line between the first and second regions, and terminals are exposed in the first and second regions. The conductive pattern They are connected to each other.
[作 用] 本発明によれば、導電パターンの接続部にはソルダレジ
ストが塗布されていないので、ソルダレジストを除去す
る必要がない。[Operation] According to the present invention, since the solder resist is not applied to the connection portion of the conductive pattern, it is not necessary to remove the solder resist.
また、複数の半導体装置を一列に並べて実装するにあた
り、1台のボンディングツールによりこれら半導体装置
の端子を同時に導電パターンに接続することができる。Further, when mounting a plurality of semiconductor devices arranged in a line, the terminals of these semiconductor devices can be simultaneously connected to the conductive pattern by one bonding tool.
[実施例] 第1図は本発明実施例を模式的に示した平面図、第2図
はこれに半導体装置を実装した状態を示す第1図のA−
A拡大断面図である。なお、第4図、第5図の従来例と
同じ部分にはこれと同じ符号を付し、説明を省略する。[Embodiment] FIG. 1 is a plan view schematically showing an embodiment of the present invention, and FIG. 2 is a view showing a state in which a semiconductor device is mounted thereon.
It is an A expanded sectional view. The same parts as those in the conventional example shown in FIGS. 4 and 5 are designated by the same reference numerals, and the description thereof will be omitted.
本発明は、対向する第1の方向と第2の方向である2辺
にそれぞれ群をなして端子5,5aが突出した複数の半導体
装置4〜4bを、所定の間隔で一列に配設し、端子5,5aを
プリント基板1に設けた導電パターンに接続して実装す
るようにしたものである。According to the present invention, a plurality of semiconductor devices 4 to 4b, each of which has terminals 5 and 5a projecting in groups, are arranged in a row at predetermined intervals on opposite sides of a first direction and a second direction. The terminals 5 and 5a are connected to a conductive pattern provided on the printed board 1 for mounting.
実装にあたっては、先ず、一列に配設される半導体装置
4〜4bの第1の方向に突出した第1の端子群51,51,51の
全面積より若干広くかつ連続した第1の領域6と、第2
の方向に突出した第2の端子群51a,51a,51aの全面積よ
り若干広くかつ接続した第2の領域とを、半導体装置4
〜4bの端子5,5aの突出部間の長さ(幅)Wとほぼ等しい
間隔を隔ててそれぞれプリント基板1上に設け、これら
第1、第2の領域6,6aを除いてプリント基板1の表面に
ソルダレジスト3を塗布し、第1、第2の領域6,6a内の
導電パターン2,2aを露出させる。In mounting, first, a continuous first region 6 which is slightly wider than the entire area of the first terminal groups 51, 51, 51 protruding in the first direction of the semiconductor devices 4 to 4b arranged in a row is formed. , Second
A second region that is slightly wider than the entire area of the second terminal groups 51a, 51a, 51a and is connected to the semiconductor device 4
To 4b are provided on the printed circuit board 1 at intervals substantially equal to the length (width) W between the protruding portions of the terminals 5 and 5a, and the printed circuit board 1 except for the first and second regions 6 and 6a. A solder resist 3 is applied to the surface of the above to expose the conductive patterns 2, 2a in the first and second regions 6, 6a.
そして、第3図に示すように、ボンディングツール7に
より、複数個の半導体装置4〜4bを一列に並べてその各
端子5,5aを、第1、第2の領域6,6a内に露出している導
電パターン2,2aに個別的又は同時に接続する。Then, as shown in FIG. 3, a plurality of semiconductor devices 4 to 4b are arranged in a line by the bonding tool 7 and their respective terminals 5 and 5a are exposed in the first and second regions 6 and 6a. The conductive patterns 2 and 2a are connected individually or simultaneously.
なお、ボンディングツール7の先端部に突出部8,8aを設
け、これを導電パターン2,2aに当接して予熱すれば、よ
り確実にハンダ付けを行うことができる。If the protrusions 8 and 8a are provided at the tip of the bonding tool 7 and the protrusions 8 and 8a are brought into contact with the conductive patterns 2 and 2a and preheated, soldering can be performed more reliably.
上記の実施例によれば、半導体装置4〜4bを一列に配設
したので、ボンディングツール7によりボンディングす
る際の位置決めが容易であり、また、導電パターン2,2a
が一列に並んでいるので、導電パターン2に対するフラ
ックスの転写も同時に行なうことができる。According to the above-mentioned embodiment, since the semiconductor devices 4 to 4b are arranged in a line, the positioning at the time of bonding by the bonding tool 7 is easy, and the conductive patterns 2, 2a are also arranged.
Are arranged in a line, the flux can be transferred to the conductive pattern 2 at the same time.
さらに、従来のように、1個の半導体装置ごとにそれぞ
れ独立してソルダレジストの非塗布部が設けられている
場合は、ボンディングツールによる個々の半導体装置の
端子のボンディングに際して、隣接する半導体装置との
間に存在するソルダレジストがボンディングの妨げにな
り、端子の確実な接続ができないことがあるが、本発明
においては、ソルダレジストを塗布しない領域が一列に
並べられた半導体装置の長さ方向に接続して設けられて
いるので、ボンディングツールにより確実に端子を接続
することができる。Further, as in the conventional case, when the solder resist non-coated portions are provided independently for each semiconductor device, when the terminals of the individual semiconductor devices are bonded by the bonding tool, the adjacent semiconductor devices are not bonded. In some cases, the solder resist existing between the terminals interferes with the bonding, and the terminals cannot be surely connected. However, in the present invention, regions in which the solder resist is not applied are arranged in a line in the length direction of the semiconductor device. Since the terminals are connected to each other, the terminals can be surely connected by the bonding tool.
[発明の効果] 以上の説明から明らかなように、本発明は、対抗する第
1及び第2の方向にそれぞれ群をなして端子が突出した
複数の半導体装置を、導電パターンが設けられたプリン
ト基板に実装した半導体装置の実装方法において、複数
の半導体装置の第1の方向に突出した第1端子群の全表
面積よりも若干広く連続した第1領域と、複数の半導体
装置の第2の方向に突出した第2端子群の全表面積より
も若干広く連続した第2領域とを、端子の突出部間の長
さとほぼ等しい距離を隔ててプリント基板の表面にそれ
ぞれ設け、プリント基板の第1及び第2領域を除く表面
にソルダレジストを塗布し、第1領域と第2領域との間
に複数の半導体装置を一列に配設し、かつ端子を第1及
び第2領域内に露出している導電パターンにそれぞれ接
続するようにしたので、次のような効果を得ることがで
きる。EFFECTS OF THE INVENTION As is apparent from the above description, according to the present invention, a plurality of semiconductor devices each having a terminal protruding in a group in the opposing first and second directions are printed with a conductive pattern. In a method of mounting a semiconductor device mounted on a substrate, a first region that is slightly wider than a total surface area of a first terminal group protruding in a first direction of the plurality of semiconductor devices, and a second direction of the plurality of semiconductor devices. Continuous second regions slightly wider than the total surface area of the second terminal group protruding on the printed circuit board at a distance substantially equal to the length between the projecting portions of the terminals. Solder resist is applied to the surface excluding the second region, a plurality of semiconductor devices are arranged in a line between the first region and the second region, and terminals are exposed in the first and second regions. Connect to each conductive pattern By doing so, the following effects can be obtained.
(1)ボンディングツールによる半導体装置の位置決め
は、従来、上下左右の4方向の精度が要求されていた
が、本発明では端子の長さ方向(第1図の上下方向)の
精度のみが要求され、端子の並列方向(第1図の左右方
向)の精度は要求されないように半導体装置を一列に並
べて実装するので、ボンディングツールの位置決めが容
易であり、特に、1台のボンディングツールで複数個の
半導体装置を同時にボンディングできるため、工数を大
幅に節減できる。(1) Positioning of a semiconductor device by a bonding tool has conventionally been required to have accuracy in four directions, up, down, left and right, but in the present invention, only accuracy in the terminal length direction (vertical direction in FIG. 1) is required. Since the semiconductor devices are mounted side by side so that the accuracy of the terminals in the parallel direction (horizontal direction in FIG. 1) is not required, it is easy to position the bonding tool, and in particular, one bonding tool can be used to position multiple semiconductor devices. Since semiconductor devices can be bonded at the same time, man-hours can be significantly reduced.
(2)従来のように、ソルダレジストの非塗布部が1個
の半導体装置に対応してそれぞれ独立して設けられてい
ると、隣接する半導体装置間のレジスト塗布部がボンデ
ィングツールの妨げになり、端子と導電パターンとの接
続が確実に行われにくくなるが、本発明は、ソルダレジ
ストの非塗布部を一列に並べた複数個の半導体装置の長
さ方向に連続して設けたので、このような問題を解決す
ることができる。(2) If the solder resist non-coating portions are provided independently corresponding to one semiconductor device as in the prior art, the resist coating portions between the adjacent semiconductor devices interfere with the bonding tool. , The connection between the terminal and the conductive pattern is difficult to be surely made, but in the present invention, since the non-coated portions of the solder resist are continuously provided in the length direction of the plurality of semiconductor devices arranged in a line, Such problems can be solved.
(3)フラックスの転写や導電パターンの予熱が容易で
ある。(3) It is easy to transfer the flux and preheat the conductive pattern.
(4)ソルダレジストを塗布してない領域(非塗布部)
の間にはソルダレジストが存在するので、この位置に導
電パターンを設けることができるため配線の自由度が高
い。さらに、この上に半導体装置を載置するようにして
いるので、半導体装置の能動面をプリント基板に対向し
て配設しても絶縁やハンダの流入などの問題が生じるこ
とがなく、このため、半導体装置の実装の自由度を増す
ことができる。(4) Area where solder resist is not applied (non-application area)
Since there is a solder resist between them, a conductive pattern can be provided at this position, so that the degree of freedom of wiring is high. Further, since the semiconductor device is mounted on this, even if the active surface of the semiconductor device is arranged to face the printed circuit board, problems such as insulation and inflow of solder do not occur, and therefore, The degree of freedom in mounting the semiconductor device can be increased.
(5)ソルダレジストを除去する手間が省けるので、工
数を節減することができる。(5) Since the labor of removing the solder resist can be omitted, the number of steps can be reduced.
第1図は本発明の実施例を模式的に示した平面図、第2
図はそのA−A拡大断面図、第3図は本発明によるボン
ディング状態を示す模式図、第4図は従来の半導体装置
の実施例を模式的に示した平面図、第5図はそのB−A
断面図である。 1:プリント基板、2,2a:導電パターン、3:ソルダレジス
ト、4,4a,4b:半導体装置、5,5a:端子、51,51a:端子群、
6:第1の領域、6a:第2の領域。FIG. 1 is a plan view schematically showing an embodiment of the present invention, and FIG.
FIG. 4 is an enlarged sectional view taken along line AA, FIG. 3 is a schematic view showing a bonding state according to the present invention, FIG. 4 is a plan view schematically showing an embodiment of a conventional semiconductor device, and FIG. -A
FIG. 1: Printed circuit board, 2, 2a: Conductive pattern, 3: Solder resist, 4, 4a, 4b: Semiconductor device, 5, 5a: Terminal, 51, 51a: Terminal group,
6: 1st area, 6a: 2nd area.
Claims (1)
をなして端子が突出した複数の半導体装置を、導電パタ
ーンが設けられたプリト基板に実装する半導体装置の実
装方法において、 前記複数の半導体装置の前記第1の方向に突出した第1
端子群の全表面積よりも若干広く接続した第1領域と、
前記複数の半導体装置の前記第2の方向に突出した第2
端子群の全表面積よりも若干広く接続した第2領域と
を、前記端子の突出部間の長さとほぼ等しい間隔を隔て
て前記プリント基板の表面にそれぞれ設け、 前記プリント基板の前記第1及び第2領域を除く表面に
ソルダレジストを塗布し、前記第1領域と前記第2領域
との間に複数の半導体装置を一列に配設し、かつ前記端
子を前記第1及び第2領域内に露出している前記導電パ
ターンにそれぞれ接続することを特徴とする半導体装置
の実装方法。1. A method for mounting a semiconductor device, comprising: mounting a plurality of semiconductor devices, each of which has a terminal protruding in a group in opposite first and second directions, on a printed board provided with a conductive pattern. Of the semiconductor device of the first projecting in the first direction
A first area connected slightly wider than the total surface area of the terminal group,
A second protrusion of the plurality of semiconductor devices in the second direction
A second region connected to the terminal group, which is slightly wider than the total surface area, is provided on the surface of the printed circuit board with a distance substantially equal to the length between the protruding portions of the terminals, and the first and second regions of the printed circuit board are provided. Solder resist is applied to the surface excluding two regions, a plurality of semiconductor devices are arranged in a line between the first region and the second region, and the terminals are exposed in the first and second regions. A method for mounting a semiconductor device, wherein the semiconductor device is connected to each of the conductive patterns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1196845A JPH07101773B2 (en) | 1989-07-31 | 1989-07-31 | Semiconductor device mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1196845A JPH07101773B2 (en) | 1989-07-31 | 1989-07-31 | Semiconductor device mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0362589A JPH0362589A (en) | 1991-03-18 |
| JPH07101773B2 true JPH07101773B2 (en) | 1995-11-01 |
Family
ID=16364620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1196845A Expired - Fee Related JPH07101773B2 (en) | 1989-07-31 | 1989-07-31 | Semiconductor device mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07101773B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS639996A (en) * | 1986-06-30 | 1988-01-16 | 関西日本電気株式会社 | Method of forming solder resist layer |
| JPS63299397A (en) * | 1987-05-29 | 1988-12-06 | Sony Corp | Substrate mounted with semiconductor integrated circuit |
| JPS6453493A (en) * | 1987-08-24 | 1989-03-01 | Ibiden Co Ltd | Wiring board for surface packaging |
-
1989
- 1989-07-31 JP JP1196845A patent/JPH07101773B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0362589A (en) | 1991-03-18 |
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