JPS639996A - Method of forming solder resist layer - Google Patents
Method of forming solder resist layerInfo
- Publication number
- JPS639996A JPS639996A JP15368086A JP15368086A JPS639996A JP S639996 A JPS639996 A JP S639996A JP 15368086 A JP15368086 A JP 15368086A JP 15368086 A JP15368086 A JP 15368086A JP S639996 A JPS639996 A JP S639996A
- Authority
- JP
- Japan
- Prior art keywords
- solder resist
- resist layer
- conductive pattern
- printed circuit
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 title claims description 26
- 238000000034 method Methods 0.000 title claims description 3
- 239000000758 substrate Substances 0.000 claims description 12
- 238000007650 screen-printing Methods 0.000 claims description 6
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010011732 Cyst Diseases 0.000 description 1
- 241000282414 Homo sapiens Species 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
一二一の1
本発明はプリント基板の導電パターン上で不要部分に半
田が付着するのを防止するためのソルダレジスト層を形
成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION 1-21 The present invention relates to a method for forming a solder resist layer for preventing solder from adhering to unnecessary portions on a conductive pattern of a printed circuit board.
附泉Δ皮肛
電子回路装置は一般的に電子部品をプリント基板上にマ
ウントし、各電子部品間を導電パターンにて電気的に接
続し回路を構成するようにしている。An electronic circuit device generally has electronic components mounted on a printed circuit board, and the electronic components are electrically connected using conductive patterns to form a circuit.
第3図はプリント基板の一例を示す。図中、1は樹脂な
どの絶縁基板、2は絶縁基板1上に積層した銅箔をエツ
チングして形成した導電パターン、3は導電パターン2
上の要部で基板1を貫通した透孔を示す。FIG. 3 shows an example of a printed circuit board. In the figure, 1 is an insulating substrate such as resin, 2 is a conductive pattern formed by etching copper foil laminated on the insulating substrate 1, and 3 is a conductive pattern 2.
A through hole penetrating the substrate 1 is shown in the upper main part.
このプリント基板は導電パターン2が露出しているため
、半田槽を用いて半田すると導電パターン2全面に半田
が付着し、半田の使用量が多く、また接近する導電パタ
ーン2,2間で半田ブリッジを生じるという問題があっ
て、一般的には導電パターン2の必要部分だけ露出する
ように第4図に示すようにソルダレジスト層4を形成し
ている。Since the conductive pattern 2 of this printed circuit board is exposed, when it is soldered using a solder bath, the solder adheres to the entire surface of the conductive pattern 2, resulting in a large amount of solder being used. Generally, a solder resist layer 4 is formed as shown in FIG. 4 so that only necessary portions of the conductive pattern 2 are exposed.
このソルダレジストは耐熱性の樹脂が一般的に用いられ
、液状のソルダレジスト材を所望部分のみ窓あけしたマ
スクを用いスクリーン印刷法により形成している。Heat-resistant resin is generally used for this solder resist, and it is formed by screen printing using a mask with apertures in only desired areas of liquid solder resist material.
[1,(’、−c!占
ところで、このレジスト層4の形成は従来、1つのマス
クを用い一括して形成していた。[1, (', -c! By the way, the resist layer 4 has conventionally been formed all at once using one mask.
ところが、電子部品の実装密度をあげるために導電パタ
ーン2の中を狭くすると共に間隔を狭くしてゆくと次の
ような問題があった。However, when the inside of the conductive pattern 2 is narrowed and the distance between the conductive patterns 2 is narrowed in order to increase the mounting density of electronic components, the following problems occur.
即ち、スクリーン印刷する際にスキージの進行方向に沿
って形成された導電パターン、例えは第3図導電パター
ン2aに対しては第5図に示すように導電パターン2a
上にも導電パターン2at2a間にも良好なソルダーレ
ジスト層4が形成されるが、スキージの進行方向と直交
する導電パターン、(第3図導電パターン2b)に対し
てはレジスト層の厚みが導電パターン2bの厚みとほぼ
同じかそれより薄いと第6図に示すように導電パターン
2bの断面エツジ部分でレジスト層の厚みが薄くなり、
極端な場合には導電パターン2bが露出してソルダレジ
ストの作用をしな(なるという問題があった。That is, the conductive pattern formed along the advancing direction of the squeegee during screen printing, for example, the conductive pattern 2a shown in FIG.
A good solder resist layer 4 is formed both above and between the conductive patterns 2at2a, but the thickness of the resist layer is smaller than that of the conductive pattern (conductive pattern 2b in FIG. 3) that is perpendicular to the advancing direction of the squeegee. If the thickness of the resist layer is approximately the same as or thinner than the conductive pattern 2b, the thickness of the resist layer becomes thinner at the cross-sectional edge portion of the conductive pattern 2b, as shown in FIG.
In extreme cases, there is a problem that the conductive pattern 2b is exposed and does not function as a solder resist.
。 占 ゛ −の
本発明は上記問題点に鑑み提案されたもので、基板の導
電パターン面を導電パターンの引きまわし方向が略同−
な部分に区分し、各区分毎の引きまわし方向に沿ってス
クリーン印刷することにより、上記問題を解決したもの
である。. The present invention has been proposed in view of the above-mentioned problems, and is based on the fact that the conductive patterns are drawn in substantially the same direction on the conductive pattern surface of the substrate.
The above problem is solved by dividing the paper into sections and screen printing along the drawing direction for each section.
災胤肚
以下に本発明の実施例を第3図プリント基板に適用し第
1図から説明する。Embodiments of the present invention will now be described with reference to FIG. 1 by applying them to the printed circuit board shown in FIG.
先ず第1図に示すスクリーン印刷用のマスク5,6を用
意する。First, masks 5 and 6 for screen printing shown in FIG. 1 are prepared.
実際にはプリント基板1は作業性を良くするために複数
枚分連結され、外周に電子部品の実装時あるいは半田付
けの際にキャリアに保持する部分が連結されたものを用
い、第1.第2のマスク5,6も上述の基板より大きく
、周縁がフレーム(図示せず)に張設されるが、説明を
而単にするために1枚の基板1とそれに対応するマスク
部分とを図示している。In actual practice, a plurality of printed circuit boards 1 are connected to improve workability, and a portion to be held in a carrier during mounting or soldering of electronic components is connected to the outer periphery of the printed circuit board 1. The second masks 5 and 6 are also larger than the above-mentioned substrates, and their peripheral edges are stretched over a frame (not shown), but for the sake of simplicity, one substrate 1 and its corresponding mask portion are shown in the figure. It shows.
このマスク5,6はシルクメツシュ等のスクリーンに感
光性樹脂を塗布して、所望部分を露光し、ソルダレジス
ト層を形成したくない部分に樹脂7を残してメンシュの
目をつぶしたもので、第1のマスク5はプリント基板1
のX方向に沿う導電パターン2aが形成された領域Aに
対応して図示斜線を付した部分aのメツシュが開口され
、第2のマスク6はプリント基板1のY方向に沿う導電
パターン2bが形成された領域Bに対応して図示斜線を
付した部分すのメツシュが開口されている。These masks 5 and 6 are made by coating a photosensitive resin on a screen such as a silk mesh, exposing the desired area to light, and closing the eyes of the mensch by leaving the resin 7 on the area where you do not want to form a solder resist layer. 1 mask 5 is printed circuit board 1
The mesh in the shaded area a in the figure is opened corresponding to the area A where the conductive pattern 2a along the X direction of the printed circuit board 1 is formed, and the second mask 6 forms the conductive pattern 2b along the Y direction of the printed circuit board 1. The mesh in the shaded area in the figure is opened corresponding to the area B that has been removed.
このような第1・第2のマスク5,6を用い、先ず、第
1のマスク5を基板1上に配置して図示しないが、マス
ク5上にソルダレジストを供給してスキージにてX方向
に延ばし、基板1上の領域Aにソルダレジスト層を形成
する。Using such first and second masks 5 and 6, first, the first mask 5 is placed on the substrate 1, and although not shown, a solder resist is supplied onto the mask 5 and the solder resist is applied in the X direction with a squeegee. Then, a solder resist layer is formed in area A on the substrate 1.
次いで、第2のマスク6を用い、ソルダレジストをY方
向に延ばして基板1上の領域Bにソルダレジスト層を形
成する。Next, using the second mask 6, the solder resist is extended in the Y direction to form a solder resist layer in region B on the substrate 1.
尚、図示例では説明を簡単にするため、導電パターン2
a + 2 bは直交方向にしか形成されていない
が、複雑な形状の場合にはスキージの移動方向に対して
第1・第2のマスク5,6のいずれかでツルダレジスl
jを形成すればよく、第1図には図示しないが領域Cの
パターン形状によって第1、第2のマスク5,6の領域
C1C“のパターン形状を決めればよい
このようにして、導電パターン2as2bに対しいずれ
も第2図に示すように、ソルダレジスト層4を均一の厚
さで被覆できる。In addition, in the illustrated example, in order to simplify the explanation, the conductive pattern 2
a + 2 b is formed only in the orthogonal direction, but in the case of a complicated shape, either the first or second mask 5 or 6 can be used to create a squeegee resist l in the direction of movement of the squeegee.
In this way, the pattern shape of the region C1C" of the first and second masks 5, 6 can be determined based on the pattern shape of the region C (not shown in FIG. 1). However, as shown in FIG. 2, the solder resist layer 4 can be coated with a uniform thickness.
この後、基板1に穿孔し、所定寸法に切断されプリント
基板が製造される。Thereafter, the substrate 1 is perforated and cut into predetermined dimensions to produce a printed circuit board.
尚、上記説明は片面プリント基板について説明したが、
両面プリント基板にも適用できることは言うまでもない
。The above explanation was about a single-sided printed circuit board, but
Needless to say, it can also be applied to double-sided printed circuit boards.
肱敦
以上のように本発明によれば、導電パターンの引きまわ
し方向にかかわりなく、ソルダレジストの厚みを均一に
でき、導電パターン断面エツジ部でのソルダレジストが
薄くなったり、極端な場合にはエツジ韻で導電パターン
が露出するという問題がなくなり、導電パターン間で半
田ブリッジするといった問題がなくなる。According to the present invention, the thickness of the solder resist can be made uniform regardless of the direction in which the conductive pattern is drawn, and in extreme cases, the thickness of the solder resist can be made uniform at the edges of the cross-section of the conductive pattern. This eliminates the problem of conductive patterns being exposed due to edge overlapping, and eliminates the problem of solder bridging between conductive patterns.
従って導電パターン間隔をより小さくでき、また導電パ
ターンの厚みに比してソルダシストを薄くできる。Therefore, the distance between the conductive patterns can be made smaller, and the solder cyst can be made thinner than the thickness of the conductive patterns.
第1図は本発明を説明するためのプリント基板とマスク
の斜視図、第2図は本発明を実施したプリント基板の断
面図、第3図はプリント基板の斜視図、第4図乃至第6
図はソルダレジスト層を形成したプリント基板の斜視図
を示す。
1・・・基板、2a12b・・・導電パターン、4・・
・ソルダレジスト層。
l・
特許用 願 人 関西日本電気株式会社 (・第1図
第 2 図FIG. 1 is a perspective view of a printed circuit board and a mask for explaining the present invention, FIG. 2 is a sectional view of a printed circuit board embodying the present invention, FIG. 3 is a perspective view of the printed circuit board, and FIGS. 4 to 6
The figure shows a perspective view of a printed circuit board on which a solder resist layer is formed. 1... Substrate, 2a12b... Conductive pattern, 4...
・Solder resist layer. l. Patent applicant: Kansai NEC Corporation (Fig. 1, Fig. 2)
Claims (1)
ーン印刷によりソルダレジスト層を形成するに当り、上
記導電パターンの引きまわし方向を区分し、各区分毎の
引きまわし方向に沿ってスクリーン印刷することを特徴
とするソルダレジスト層の形成方法。When forming a solder resist layer by screen printing on a printed circuit board on which a conductive pattern is formed on the substrate, the drawing direction of the conductive pattern is divided and screen printing is performed along the drawing direction for each section. A method for forming a solder resist layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15368086A JPS639996A (en) | 1986-06-30 | 1986-06-30 | Method of forming solder resist layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15368086A JPS639996A (en) | 1986-06-30 | 1986-06-30 | Method of forming solder resist layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639996A true JPS639996A (en) | 1988-01-16 |
Family
ID=15567813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15368086A Pending JPS639996A (en) | 1986-06-30 | 1986-06-30 | Method of forming solder resist layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639996A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0362589A (en) * | 1989-07-31 | 1991-03-18 | Seiko Epson Corp | Mounting of semiconductor device |
-
1986
- 1986-06-30 JP JP15368086A patent/JPS639996A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0362589A (en) * | 1989-07-31 | 1991-03-18 | Seiko Epson Corp | Mounting of semiconductor device |
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