JPH07105397B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] In a semiconductor integrated circuit device in which a high breakdown voltage element and a low breakdown voltage element coexist, both elements are formed on a substrate (specific resistance etc.) matched with the high breakdown voltage element. Low voltage device performance is sacrificed. Therefore, the substrate concentration in the low voltage portion is made high by means of implantation, etc., and both are formed simultaneously.

[Conventional technology]

Conventionally, when a high breakdown voltage element and a low breakdown voltage element are formed on the same semiconductor substrate, the impurity concentration and specific resistance of the substrate are selected according to the high breakdown voltage element, so that the low breakdown voltage element is turned on. In many cases, electrical resistance is sacrificed due to increased resistance.

Therefore, for example, as shown in Japanese Patent Publication No. 61-26232, a high breakdown voltage element and a low breakdown voltage element are formed in separate processes, and the performance of the low breakdown voltage element is covered by devising the structure and dimensions. Is proposed.

For example, when a high breakdown voltage npn transistor and a low breakdown voltage npn transistor having a large current amplification factor and a small collector resistance are formed on a common substrate, as shown in FIG. Deep, on the other hand, low breakdown voltage,
The junction of the npn transistor II, which has a large current amplification factor, is made shallow to satisfy each performance.

[Problems to be solved by the invention]

Conventionally, as described above, when forming a high-voltage element and a low-voltage element on the same substrate, in order to satisfy the required performance of each, a substrate suitable for a high-voltage element is used and the high-voltage element and low-voltage element are used. The element and the element are formed by separate processes.

However, since the substrate resistance is matched to that of the high breakdown voltage element, it is difficult to further improve the performance of the npn transistor for the low breakdown voltage element. In particular, when a large current is passed through the low breakdown voltage element, there arises a problem that the ON resistance or the collector resistance is large due to the large resistance of the substrate.

Further, since the high breakdown voltage junction and the low breakdown voltage junction are formed in separate processes, the manufacturing process is lengthened, and the manufacturing efficiency is lowered.

[Means for solving problems]

In order to eliminate the above-mentioned drawbacks, the present invention increases the impurity concentration of the substrate compared to the high breakdown voltage element formation region by subjecting the low breakdown voltage element formation region of the common substrate to ion implantation or selective diffusion. The joint is formed at the same time to improve the performance of the low breakdown voltage element and to simplify the manufacturing process.

[Action]

By setting the impurity concentration of the low breakdown voltage element formation region higher than that of the high breakdown voltage element formation region, even if PN junctions are formed in each region by the same diffusion process after that, the junction depth of the low breakdown voltage element formation region is increased. Can be made shallower than that in the high breakdown voltage element forming region, so that the current amplification factor of the low breakdown voltage element can be increased to improve the performance.

〔Example〕

 An embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1 (a), a region 10 in which a low breakdown voltage element of the dielectric isolation substrate 1 mainly composed of N-type silicon is formed.
Then, an N type impurity 2 is introduced by a method such as ion implantation, and an N type layer 3 is formed by a thermal diffusion method [FIG. 1 (b)]. At this time, the depth of the N-type layer 3 is P
It is important to be deeper than the base layer 5 [Fig. 1 (c)].

After that, using a normal diffusion technique, P
The base layer 4 and the P base layer 5 of the low breakdown voltage element portion 10 are diffused at the same time. At this time, as shown in FIG. 1 (c), due to the difference in impurity concentration between the high breakdown voltage element portion 20 and the low breakdown voltage element portion 10, the high breakdown voltage element portion 20 is deeply joined,
The junction of 10 is formed shallower than this.

Further, N emitter layers 6 and 7 and N ⁺ layers 8 and 8'as collector contact portions are formed by the same diffusion process [FIG. 1 (c)]. Finally, the wiring for electrical drawer E, B, C, e, b,
If c is formed, two types of transistors, a high breakdown voltage and a low breakdown voltage, can be formed on the same substrate [FIG. 1 (d)].

As a result of an experiment conducted by the present inventor while changing the implantation amount of the N-type impurity 2 in the process of FIG. 1 (a), the results of FIGS. 2 and 3 were obtained.

FIG. 2 shows N formed by the ion implantation of FIG.
3 shows an I _c (horizontal axis) -h _FE (vertical axis) curve of a transistor with the impurity concentration of the shaping layer 3 as a parameter.

11 in the figure is a high breakdown voltage element (impurity concentration 2 × 10 ¹⁴ cm ^-3 ).
In addition, 12 to 14 have impurity concentrations of 7 × 10 ¹⁶ , 2 × 10 ¹⁷ , 5 × 10.
Shows the I _c -h _FE curve of the low breakdown voltage element when changing the ¹⁷ cm ^-3. In addition, points A to D in the figure represent inflection points of h _FE , and this point is tentatively defined as the maximum collector current I _cmax .

The chain line and the solid line in FIG. 3 indicate the impurity concentration of the substrate (horizontal axis) and I _cmax and the element (junction) defined in FIG. 2, respectively.
The relationship of breakdown voltage is shown.

As can be seen from this figure, as the impurity concentration of the substrate, that is, the N-type layer 3 in FIG. 1, increases, the breakdown voltage of the device junction gradually decreases, while the maximum collector of the transistor formed there is increased. The current I _cmax increases rapidly.

From the above results, it is understood that according to the present invention, by appropriately setting the impurity concentration of the N-type layer 3, high breakdown voltage and low breakdown voltage transistors having different performances can be formed by the same diffusion process.

Although an example in which the impurity concentration of the N-type layer 3 is increased by ion implantation has been described above, it will be easily understood that it can be achieved by selective diffusion.

〔The invention's effect〕

According to the present invention, a high breakdown voltage element and a high performance low breakdown voltage transistor can be easily formed on the same substrate by the same process, and the performance and manufacturing of an integrated circuit device (low breakdown voltage element) can be improved and manufactured. It can be expected to simplify the process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the manufacturing method of the present invention, FIGS. 2 and 3 are graphs showing the performance of a low breakdown voltage transistor manufactured according to the present invention, and FIG. 4 is a conventional semiconductor integrated circuit device. It is a figure which shows the cross-section. 1 ... Dielectric insulating substrate, 2 ... N type impurity, 3 ... High impurity concentration N type layer, 4 ... High voltage part P base layer, 5 ... Low voltage part P base layer, 6 ... High voltage part N emitter Layer, 7 ... low voltage N emitter layer, 8, 8 '... collector contact layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 29/73 (72) Inventor Eisutoshi Okubo 3-1-1 Sachimachi, Hitachi City, Ibaraki Stock Association (56) Reference JP-A-57-72345 (JP, A) JP-A-62-14468 (JP, A) JP-A-60-58655 (JP, A) JP-A-59-10258 (JP, A)

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device in which a high breakdown voltage element and a low breakdown voltage element are formed adjacent to each other on the same semiconductor substrate, wherein a dielectric film is formed on the surface of a first conductivity type semiconductor substrate. A step of forming semiconductor islands that are mutually insulated from the semiconductor substrate; and a step of removing impurities of the first conductivity type from the exposed surface of the semiconductor island in which the low breakdown voltage element is formed among the dielectric-isolated semiconductor islands. A method of manufacturing a semiconductor device, comprising: a step of selectively introducing the impurities; and a step of subsequently performing the same impurity introducing step on the high breakdown voltage element formation region and the low breakdown voltage element formation region.