JPH07105406B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH07105406B2 JPH07105406B2 JP58241304A JP24130483A JPH07105406B2 JP H07105406 B2 JPH07105406 B2 JP H07105406B2 JP 58241304 A JP58241304 A JP 58241304A JP 24130483 A JP24130483 A JP 24130483A JP H07105406 B2 JPH07105406 B2 JP H07105406B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- optical
- integrated circuit
- optical component
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
Landscapes
- Die Bonding (AREA)
Description
【発明の詳細な説明】 (1) 発明の技術分野 本発明は光半導体チップをヒートシンクや基板にボンデ
ングする時、所定の位置に高精度でボンデングする方法
に関する。1. Technical Field of the Invention The present invention relates to a method for bonding an optical semiconductor chip to a heat sink or a substrate at a predetermined position with high accuracy.
(2) 技術の背景 光集積回路など、光半導体チップ上にはPINやLDなどの
光部品がモノリシックに集積化される。これら光部品と
外部にいる光ファイバーなどとを効率よく結合するには
前記光部品と光ファイバーなどの相対的位置を正確に調
整する必要がある。電気におけるLSIでは信号の入力・
出力は金線をチップにボンデングして外部と結合できる
が光集積回路への光の入出力は光ファイバーなどをチッ
プ上の光部品へ直接近づける必要があり、高位置精度の
チップボンデングは非常に重要な技術となる。(2) Background of technology Optical components such as PINs and LDs are monolithically integrated on optical semiconductor chips such as optical integrated circuits. In order to efficiently couple these optical components and the optical fiber or the like outside, it is necessary to accurately adjust the relative positions of the optical component and the optical fiber or the like. In the electrical LSI, signal input
The output can be bonded to the outside by bonding a gold wire to the chip, but for the input and output of light to the optical integrated circuit, it is necessary to bring the optical fiber etc. directly close to the optical components on the chip, so chip bonding with high position accuracy is very It will be an important technology.
(3) 従来技術と問題点 従来、光集積回路の集積度は低く、また量産状態にな
い。(3) Conventional Technology and Problems Conventionally, the degree of integration of optical integrated circuits is low, and they are not in mass production.
したがって、このようなチップはヒートシンクなどにボ
ンデングされた後、外部の光ファイバーの位置などを治
具上で調整後実装している。Therefore, after such a chip is bonded to a heat sink or the like, the position of an external optical fiber is adjusted on a jig and then mounted.
光集積回路チップをウエハーより切り出す場合、切りだ
し面はかならずしもチップ上の光部品と一定の位置関係
に置くことはできない。(チップ切出し精度は本質的に
よくない) チップの切り出し精度が悪いため、かならずしも集積回
路上の光部品であるPINやLDが切り出し面より所定の位
置にあるとはかぎらず数+μmの誤差はまぬがれない。
一方チップ上の光部品の位置を正確に決定するのは小形
・集積化されていることと、プローブ光としてレーザ光
をあてると劣化する可能性があることなどよりきわめて
困難である。When an optical integrated circuit chip is cut out from a wafer, the cut-out surface cannot always be placed in a fixed positional relationship with the optical components on the chip. (The chip cutting accuracy is not good in principle.) Because the chip cutting accuracy is poor, the PIN + LD, which are optical components on the integrated circuit, are not always in the specified position from the cutting surface, and an error of several + μm must be avoided. Absent.
On the other hand, it is extremely difficult to accurately determine the position of the optical component on the chip because it is small and integrated, and there is a possibility that it deteriorates when irradiated with laser light as the probe light.
第1図は段差をつけずに従来通り切り出されたものであ
り、たとえば切り出された光半導体チップ1の切り出し
面2と、PIN,LD等の光部品3の部品列及び集積回路3′
とが平行でもない。自動制御によって部品実装やチップ
ボンデングを行なおうとしたとき、この切り出し面2に
レーザ光などをあて参照信号を取り出せば光部品3位置
に対して誤差を生じる。FIG. 1 shows a conventional cutout without steps. For example, a cutout surface 2 of the cutout optical semiconductor chip 1, a component row of optical components 3 such as PIN and LD, and an integrated circuit 3 '.
And are not parallel. When component mounting or chip bonding is attempted by automatic control, if a reference signal is taken out by applying a laser beam or the like to the cutout surface 2, an error occurs with respect to the position of the optical component 3.
(4) 発明の目的 本発明はチップ周囲に光部品との位置関係が正確に、示
された段差をエッチングによって作りこれをチップボン
デングにおいて利用する光集積回路チップの高位置精度
ボンデング法を提供するものである。(4) Object of the Invention The present invention provides a high-position-accuracy bonding method for an optical integrated circuit chip in which a positional relationship with an optical component is accurately formed around the chip by etching and the step is used in chip bonding. To do.
(5) 発明の構成 本発明は、光部品,光集積回路が形成されるチップ上の
当該光部品,光集積回路以外の領域に、当該光部品,光
集積回路の作成プロセスと同じフォリソグラフィプロセ
スで決定されたチップボンディング位置決めパターンを
形成する工程と、次いで、該位置決めパターンを含むよ
うにチップを切りだす工程と、次いで、該パターンを基
準位置としてチップボンディングする工程とを有するこ
とを特徴とする。(5) Structure of the Invention The present invention is the same photolithography process as the manufacturing process of the optical component and the optical integrated circuit in a region other than the optical component and the optical integrated circuit on the chip on which the optical component and the optical integrated circuit are formed. A step of forming a chip bonding positioning pattern determined by 1., a step of cutting a chip so as to include the positioning pattern, and a step of chip bonding using the pattern as a reference position. .
本発明は、プラズマエッチング(RIE)又はケミカルエ
ッチングによってチップ周囲に段差をつける。段差の光
部品からの位置精度は集積回路作成プロセスと同じフォ
トソングラフィプロセスで決定され、切り出し精度とは
関係なく、この段差部にコリメートされたレーザ光をあ
てることによって光集積回路チップの位置を正確に読み
出すことができる。この読み出された信号によって外部
の実装治具を自動制御することによってヒートシンクや
基板への取付け位置精度を正確にすることができる。The present invention forms a step around the chip by plasma etching (RIE) or chemical etching. The position accuracy of the step from the optical component is determined by the same photosonography process as the integrated circuit fabrication process, and regardless of the cutting accuracy, the position of the optical integrated circuit chip can be determined by irradiating the stepped part with collimated laser light. Can be read accurately. By automatically controlling the external mounting jig based on the read signal, the accuracy of the mounting position on the heat sink or the substrate can be made accurate.
(6) 発明の実施例 以下図面を参照して本発明の実施例を説明する。(6) Embodiments of the Invention Embodiments of the present invention will be described below with reference to the drawings.
本発明は光部品,光集積回路の作製されたウエハーを光
半導体チップとして切り出す前に、チップ周辺をエッチ
ングし、チップ表面と光部品,光集積回路の形成された
チップ周辺に一定の段差をつける。この段差は、光部
品,光集積回路の作成プロセスと同じフォトリソグラフ
ィプロセスによって形成されたものであるため、光部
品,光集積回路などとの相対的な位置関係は非常に高精
度である。その後エッチングした部分を比較的低精度で
切り出すことができ、ヒートシンクや基板にチップボン
デングする時には、高精度に位置づけられた前記段差部
を利用して行なうものである。According to the present invention, before cutting a wafer on which an optical component and an optical integrated circuit are manufactured as an optical semiconductor chip, the periphery of the chip is etched to form a certain step between the chip surface and the periphery of the chip on which the optical component and the optical integrated circuit are formed. . Since this step is formed by the same photolithography process as the manufacturing process of the optical component and the optical integrated circuit, the relative positional relationship with the optical component, the optical integrated circuit and the like is very high. After that, the etched portion can be cut out with relatively low precision, and when the chip bonding is performed on the heat sink or the substrate, the stepped portion positioned with high precision is used.
第2図は、従来の自動制御による実装での欠点を取り除
いたもので、パターンニングによって光部品3との位置
関係を一定にした段差4を持つチップを示している。上
からこの段差部を見ながら実装もできるが、段差側面を
RIE(プラズマリアクティブエッチング)により鏡面状
態で作成できれば、この段差面にレーザ光をあて正確な
参照信号を取り出すことができ、実装における位置精度
を向上できる。FIG. 2 shows a chip having a step 4 in which the positional relationship with the optical component 3 is made constant by patterning after removing the drawbacks in the conventional automatic control mounting. You can mount it while looking at this step from above, but
If the mirror surface can be created by RIE (plasma reactive etching), a precise reference signal can be taken out by applying a laser beam to the step surface, and the mounting position accuracy can be improved.
第3図は段差部の拡大図を示したものであり、(a)が
RIE,(b)がケミカルエッチによる順メサ型4′のもの
と逆メサ型4″のものを示している。FIG. 3 is an enlarged view of the stepped portion, where (a) is
RIE, (b) shows a forward mesa type 4'and a reverse mesa type 4 "by chemical etching.
なお本実施例では、エッチングにより段差をつける例を
上げたが、第4図のような所定寸法形状のワクのパター
ンの移動・回転を検出できる自動制御実装治具を利用し
た場合には光集積回路チップ1の周辺に特に反射率の高
い膜5を第4図のように蒸着しておけば、これにコリメ
ート光をあてることによってその移置を検出できる。In this embodiment, an example in which a step is formed by etching is given. However, when an automatic control mounting jig capable of detecting movement / rotation of a pattern of a predetermined size shape as shown in FIG. If a film 5 having a particularly high reflectance is vapor-deposited around the circuit chip 1 as shown in FIG. 4, the transfer can be detected by applying collimated light to the film.
またこのような実装治具では、位置確認に用いうる第4
図以外のパターンによっても可能であることはいうまで
もない。Also, with such a mounting jig, the fourth jig that can be used for position confirmation
It goes without saying that it is possible to use patterns other than the figures.
(7) 発明の効果 一定位置関係にある段差をチップ周囲につけ、これを見
ながらヒートシンクや基板に対して所定の位置にくるよ
うにしてボンデングする。(7) Effects of the Invention A step having a fixed positional relationship is formed around the chip, and while observing the step, the step is brought to a predetermined position with respect to the heat sink and the substrate, and the bonding is performed.
本発明によれば、光集積回路中の光部品の位置を正確に
検出できるので、自動的にヒートシンクや基板にチップ
を実装又はボンデングするときその位置を正確に与える
ことができる。According to the present invention, the position of an optical component in an optical integrated circuit can be accurately detected, so that the position can be accurately given when a chip is automatically mounted or bonded on a heat sink or a substrate.
その結果、光の入出力時の結合損出が低下し、光部品の
完全自動実装に効果がある。As a result, coupling loss at the time of inputting / outputting light is reduced, which is effective for fully automatic mounting of optical components.
第1図は従来法を説明する図,第2図は本発明を説明す
る図,第3図は段差部の拡大図,第4図は本発明の他の
実施例を説明する図である。 1:チップ,2:チップ切出面,3:光部品,3′:集積回路,4,
4′,4″:段差,5:反射率の高い膜。FIG. 1 is a diagram for explaining a conventional method, FIG. 2 is a diagram for explaining the present invention, FIG. 3 is an enlarged diagram of a step portion, and FIG. 4 is a diagram for explaining another embodiment of the present invention. 1: Chip, 2: Chip cutout surface, 3: Optical component, 3 ′: Integrated circuit, 4,
4 ′, 4 ″: step, 5: film with high reflectance.
Claims (1)
の当該光部品,光集積回路以外の領域に、当該光部品,
光集積回路の作成プロセスと同じフォトリソグラフィプ
ロセスで決定されたチップボンディング位置決めパター
ンを形成する工程と、 次いで、該位置決めパターンを含むようにチップを切り
だす工程と、 次いで、該パターンを基準位置としてチップボンディン
グする工程とを有することを特徴とする半導体装置の製
法。1. An optical component, the optical component on a chip on which an optical integrated circuit is formed, and the optical component on an area other than the optical integrated circuit.
A step of forming a chip bonding positioning pattern determined by the same photolithography process as the manufacturing process of the optical integrated circuit; a step of cutting the chip so as to include the positioning pattern; and a chip using the pattern as a reference position. A method for manufacturing a semiconductor device, which comprises a step of bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58241304A JPH07105406B2 (en) | 1983-12-21 | 1983-12-21 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58241304A JPH07105406B2 (en) | 1983-12-21 | 1983-12-21 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60133735A JPS60133735A (en) | 1985-07-16 |
| JPH07105406B2 true JPH07105406B2 (en) | 1995-11-13 |
Family
ID=17072286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58241304A Expired - Fee Related JPH07105406B2 (en) | 1983-12-21 | 1983-12-21 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07105406B2 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5624941A (en) * | 1979-08-07 | 1981-03-10 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS5944772B2 (en) * | 1980-03-12 | 1984-11-01 | 富士通株式会社 | How to form automatic alignment pattern |
| JPS57169268A (en) * | 1981-04-10 | 1982-10-18 | Mitsubishi Electric Corp | Ohmic electrode material of n type 3-5 group compound semiconductor and formation of ohmic electrode therewith |
| JPS5851526A (en) * | 1981-09-24 | 1983-03-26 | Hitachi Ltd | Semiconductor element pellet and semiconductor device with said pellet |
| JPS5870528A (en) * | 1981-10-23 | 1983-04-27 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS58123787A (en) * | 1982-01-18 | 1983-07-23 | Fujitsu Ltd | Automatic die bonding device for semiconductor laser chip |
-
1983
- 1983-12-21 JP JP58241304A patent/JPH07105406B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60133735A (en) | 1985-07-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |