JPH07106975A - Oversampling a/d converter - Google Patents

Abstract

PURPOSE:To reduce the noise of a full scale setting signal that is caused by a noise signal by offsetting the noise component of the output side of a 1st oversampling modulator by the noise component superposed on the full scale setting signal of the output side of a 2nd oversampling modulator. CONSTITUTION:A 1st oversampling modulator 2 supplies a converted analog signal to a terminal A and also supplies a full scale setting signal to a terminal R. Then the modulator 2 outputs the relative value of the converted analog signal set to the full scale setting signal at a rate faster than the output rate of the final digital code. A 2nd oversampling modulator 4 supplies a full scale setting signal to the terminal A and a fixed signal to the terminal R respectively. Then the modulator 4 outputs the relative value of the full scale setting signal set to the fixed signal at a rate faster than the output rate of the final digital code. An adder 6 adds together the outputs of both modulators 2 and 4 and offsetes the noises.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oversampling AD converter.

More specifically, the present invention is an AD converter for sampling an analog input signal at a rate faster than the output rate of a finally output digital code, performing decimation processing, and outputting the digital code. For example, the present invention relates to an oversampling AD converter using a ΔΣ modulator.

[0003]

2. Description of the Related Art In recent years, oversampling technology has come into widespread use because ICs capable of following a high-speed clock can be mass-produced. Above all, the oversampling AD converter using the oversampling ΔΣ modulator has excellent linearity as a conversion characteristic: There is no singular point that causes zero-cross distortion: To increase the oversampling ratio As a result, it is possible to have a high resolution of 16 bits or more: Easy to integrate such as LSI: It has become more important technically and commercially.

FIG. 2 shows a conventional oversampling AD converter. Reference numeral 20 in the figure is an oversampling modulator. The converted analog input signal is supplied to the analog input terminal A, and the full scale setting signal is supplied to the reference input terminal R. The oversampling modulator 20 outputs a high-speed digital code representing a relative value with respect to the full scale setting signal by N times oversampling. Then, the digital filter 22 in the next stage performs decimation processing to remove unnecessary high-frequency components, and outputs a low-speed final digital code.

Here, the "relative value with respect to the full scale setting signal" means the relationship as shown in FIG. 2 (B). That is, when the analog input signal is V _A and the full scale setting signal is V _R ,

[0006]

[Equation 1] Relative value = V _A / V _R or

[0007]

[Formula 2] Relative value = k (V _A / V _R ) + C.

[0008]

However, in the conventional oversampling AD converter as shown in FIG. 2, unnecessary noise components (or unnecessary frequency components) superimposed on the full-scale setting signal are generated. Signal) appears directly as the output of the modulator. Moreover, the magnitude of the noise component that appears as the output of the modulator increases in proportion to the magnitude of the converted analog input signal.

Next, the magnitude of the noise component on the output side will be described in detail.

Now, the full scale setting signal value is REF, the noise component value (input error value) superimposed on the full scale setting signal is NREF, the converted analog input signal value is AIN, and the output side of the modulator The noise component value appearing in (that is, the output error value caused by the noise component superimposed on the full scale setting signal) is NOU
If T and the NREF is sufficiently smaller than the REF,

[0011]

[Formula 3] NOUT = − (AIN / REF) × NREF. Therefore, the absolute value of NOUT is

[0012]

[Formula 4] | NOUT | = (AIN / REF) × NREF, which is proportional to the converted analog input signal value AIN.
The broken line in FIG. 3 represents this.

As is apparent from FIG. 3, the magnitude | NOUT | of the noise component output from the modulator is AIN = 0.
It becomes zero when (no input), but becomes maximum (= NREF) when AIN = REF (that is, when the converted analog input signal value becomes equal to the full-scale setting signal value).

Therefore, in view of the above points, an object of the present invention is to
Even if the size of the converted analog input signal increases,
Oversampling AD that reduces the size of the output-side noise component caused by the noise component of the full-scale setting signal
To provide a converter.

[0015]

In order to achieve such an object, an oversampling modulator according to the present invention inputs a converted analog input signal and a full scale setting signal, and inputs the analog input to the full scale setting signal. First oversampling modulation means for outputting the relative value of the signal at a rate higher than the output rate of the final digital code, and the full scale setting signal and the specific value signal are input, and the full scale setting signal for the specific value signal is input. The relative value of is output at a rate higher than the output rate of the final digital code, and the signals output from the first and second oversampling modulation means are input, and the predetermined value is determined. The calculation means for outputting a signal of It is obtained by including a digital filter for outputting a digital code corresponding to the analog input signal at a predetermined rate.

Here, the first oversampling modulation means inputs the converted analog signal to an analog input terminal, and inputs the full scale setting signal to a reference input terminal to output the second oversampling modulation. Means inputs the full scale setting signal to an analog input terminal and the specific value signal inputs to a reference input terminal, and the arithmetic means outputs signals output from the first and second oversampling modulation means, respectively. It is preferable to add and output.

[0017]

According to the above structure of the present invention, the output side of the second oversampling modulation means is caused to output a noise component due to the noise superimposed on the full scale setting signal, and the output and the first oversampling are performed. The noise component appearing on the output side of the modulator can be canceled.
This makes it possible to reduce the magnitude of the output-side noise component resulting from the noise component of the full-scale setting signal even when the magnitude of the converted analog input signal increases.

[0018]

EXAMPLES Examples of the present invention will be described in detail below.

Embodiment 1 FIG. 1 shows an oversampling AD converter to which the present invention is applied. In the figure, 2 is a first oversampling modulator, which inputs a converted analog input signal to an A terminal (analog input terminal) and inputs a full-scale setting signal to an R terminal (reference input terminal). . Then, the relative value of the converted analog input signal to the full-scale signal (see FIG. 2B) is output at a rate faster than the output rate of the final digital code (that is, N times oversampling) and output.

Reference numeral 4 is a second oversampling modulator, which inputs the above-mentioned full-scale setting signal to the A terminal and also inputs a constant value signal to the R terminal. Then, the relative value of the full-scale setting signal with respect to the constant value signal is output at a rate faster than the output rate of the final digital code.

An adder 6 adds the outputs of the first and second oversampling modulators 2 and 4.

A digital filter 8 receives the output signal of the adder 6 and outputs a final digital code corresponding to the converted analog input signal.

Next, the operation of this embodiment will be described.

For convenience of explanation, assuming that the full scale setting signal value is REF, the noise component value (input error value) superimposed on the full scale setting signal is NREF, and the converted analog input signal value is AIN, Of the output signal of the first oversampling modulator 2, the noise component value NM1 due to NREF is

[0025]

[Formula 5] NM1 =-(AIN / REF) x NREF. Further, when the value of the constant value signal input to the second oversampling modulator 4 is BIN, the noise component value NM2 due to NREF in the output signal of the second oversampling modulator 4 is

[0026]

[Formula 6] NM2 = (REF / BIN) × NREF. Therefore, in the adder 6, both these component values NM
Since 1 and NM2 are added, the noise component value NADD of the output signal of the adder circuit 6 is

[0027]

[Formula 7] NADD = NM1 + NM2 = − (AIN / REF) × NREF + (REF / BIN) × NREF = {(REF / BIN) − (AIN / REF)} × NREF. here,

[0028]

[Equation 8] If BIN = α × REF (α> 1), NADD is

[0029]

[Equation 9] NADD = {(REF / α · REF) − (AIN / REF)} × NREF = (1 / REF) × {(REF / α) −AIN} × NREF. Now, assuming that α = 2 in order to minimize the noise component value, when the converted analog input signal value AIN has a value of 0 to REF, NADD is + (NRE
A value of − (NREF / 2) will be taken from F / 2).

That is, when α = 2 is set, as shown in FIG.
As indicated by the alternate long and short dash line in FIG.
Therefore, the maximum value (NREF / 2) will be taken.

Thus, the NADD is output from the digital filter 8 as a noise component of the final digital code.

The NADD has a constant term (REF /
Since BIN) is included, it is possible to correct the constant value in the digital filter 8. Further, the full-scale setting signal value REF needs to have an accurate value, but the value itself (BIN) of the constant value signal input to the second oversampling modulator 4 does not require accuracy, and thus can be easily obtained. be able to.

Embodiment 2 FIG. 4 shows another embodiment of the present invention. In the present embodiment, the first ΔΣ modulator 22 and the second ΔΣ modulator 24 are used as the first oversampling modulator 2 and the second oversampling modulator 4 shown in FIG. 1 are specified. . These ΔΣ modulators 2
The signals input to the A and R terminals 2 and 24 are as shown in FIG.
It is the same as the case shown in.

FIG. 5 is a block diagram showing the first ΔΣ modulator 22 shown in FIG. 4 in more detail. In the figure, 50 is an integrator, 52 is a quantizer that outputs a 1-bit digital signal based on the analog output of the integrator 50, and 54 is an analog output corresponding to the full-scale setting signal value. A DA converter for converting the value into a value, and a subtracter 56 for subtracting the output signal of the DA converter 54 from the converted analog input signal. Since this ΔΣ modulator itself is known, a detailed description will be given here.

The first and second ΔΣ modulators 22,
A logic circuit 26 corresponding to the adder 6 in FIG. 1 is connected to the subsequent stage of 24, and a digital filter 28 is connected to the subsequent stage of the logic circuit 26.

FIG. 6 shows a detailed circuit configuration of the logic circuit 26 and the digital filter 28 shown in FIG. The illustrated digital filter 28 includes a ROM 60 storing a predetermined impulse response coefficient, and sequentially performs addition, subtraction, and zero addition of the impulse response coefficient according to the control signals C1 to C3 output from the logic circuit 26. To go.

That is, the impulse response coefficient read from the ROM 60 is routed to the adder 63 via the sign inverter 61 and the first analog switch SW1,
Alternatively, the subtraction or the addition is sequentially performed with the final digital code by any of the paths immediately reaching the adder 63 via the second analog switch SW2.
Here, the first analog switch SW1 is turned on when the first control signal C1 output from the logic circuit 26 is "1". Further, the second analog switch SW2 is turned on when the second control signal C2 output from the logic circuit 26 is "1".

Further, when the third control signal C3 output from the logic circuit 26 is "1", addition / subtraction of the impulse coefficient is not performed and zero addition is performed, so that the third analog switch SW3 is turned on. And

FIG. 7 shows the operation of such a logic circuit 26.

Reference numeral 65 shown in FIG. 6 is a register, which holds the output of the adder 63 and outputs the final digital code, and at the same time, feeds back the output as one input of the adder 63.

Next, the results of experiments conducted by the present inventor based on the circuit configuration of FIG. 4 will be described.

As the first ΔΣ modulator 22, 1
A full-scale setting signal (REF = 2.5 is used by using a fourth-order ΔΣ modulator operating at a clock of 6.384 kHz.
The converted analog input signal for V) was output as a 1-bit pulse density signal. Here, the noise component (NR) to be superimposed on the full scale set value signal (REF)
EF), 0.1 V _pp (peak-to-peak voltage)
3 Hz sine wave was used.

Similarly for the second ΔΣ modulator 24, a fourth-order Δ operating at a clock of 16.384 kHz.
A constant value signal (BI
A full-scale setting signal for N = 2 × REF) was modulated and output as a 1-bit signal.

Further, the digital filter 28 is 775.
Using the FIR type filter with taps, the output from each ΔΣ modulator is convoluted with the impulse response function, and after rollover prevention operation and rounding operation at the time of overflow, a final 16-bit digital code is generated at a rate of 20 Hz. Output.

Under such a configuration, the magnitude AIN of the converted analog input signal is changed from 0 to RFF (= 2.5).
V), 3H included in the final digital code
The noise component of z was measured. As a result, the maximum value is obtained when AIN = 0 and AIN = REF, and 0.05 V
_pp was obtained. This corresponds to NREF / 2 and coincided with the alternate long and short dash line shown in FIG.

Other Embodiments Instead of the ΔΣ modulator shown in FIG. 4, a so-called MAS is used.
It is also possible to use a multistage noise shoeer called H, a delta modulator, an adaptive delta converter, or the like. However, when using these modulators,
There may be a case where a part of the digital filter in the latter stage is incorporated in the modulator.

[0047]

As described above, according to the present invention, the noise component resulting from the noise superimposed on the full scale setting signal is output to the output side of the second oversampling modulation means, and the output and the first overcurrent are generated. Since the configuration is used to cancel the noise component appearing on the output side of the sampling modulator, even if the size of the converted analog input signal is increased, the output side noise component caused by the noise component of the full scale setting signal It is possible to reduce the size of the.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a conventional technique.

FIG. 3 is a diagram showing the influence of a noise component superimposed on a full-scale setting signal on a noise component on the output side.

FIG. 4 is a block diagram showing another embodiment of the present invention.

5 is a block diagram showing an example of the ΔΣ modulator shown in FIG. 4. FIG.

6 is a detailed circuit diagram of a logic circuit 26 and a digital filter 28 shown in FIG.

FIG. 7 is an explanatory diagram showing an operation of the logic circuit shown in FIG.

[Explanation of symbols]

 2,4 Oversampling modulator 6 Adder 8 Digital filter 22,24 ΔΣ modulator 26 Logic circuit 28 Digital filter C1, C2, C3 Control signal

Claims (2)

[Claims] 1. A first overcurrent inputting a converted analog input signal and a full scale setting signal, and outputting a relative value of the analog input signal to the full scale setting signal at a rate faster than an output rate of a final digital code. Sampling modulation means, input the full scale setting signal and a specific value signal,
Second oversampling modulation means for outputting the relative value of the full-scale setting signal with respect to the specific value signal at a rate faster than the output rate of the final digital code, and output from the first and second oversampling modulation means, respectively. A digital signal which outputs a digital code corresponding to the converted analog input signal at a predetermined rate, and an arithmetic means for inputting the input signal and outputting a signal having a predetermined relationship. An oversampling AD converter comprising a filter. 2. The first oversampling modulator according to claim 1, wherein the converted analog signal is input to an analog input terminal, and the full scale setting signal is input to a reference input terminal. Oversampling modulation means inputs the full-scale setting signal to an analog input terminal, and inputs the specific value signal to a reference input terminal, and the computing means respectively outputs from the first and second oversampling modulation means. An oversampling AD converter characterized by adding output signals and outputting them.