JPH0714925Y2 - Address scan latch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to an address scan latch circuit, and more specifically to an address scan latch circuit that receives an address signal and outputs a signal of a level according to the address signal. A first OR gate circuit that receives a set signal at one input terminal and an output signal of the first OR gate circuit An AND gate circuit for receiving at an input terminal of the AND gate circuit, the output signal of the AND gate circuit is input to the other input terminal of the first OR gate circuit, and a second signal for receiving a scan-in signal and an X, Y address signal is provided.
And an NOR gate circuit for receiving an X, Y address signal and an output signal of the AND gate circuit, and inputting the output signal of the second OR gate circuit to the other input terminal of the AND gate circuit. Organize to make a difference.

[Industrial application field]

The present invention relates to an address scan latch circuit, and more particularly to an address scan latch circuit that receives an address signal and outputs a signal of a level corresponding to the address signal.

In an integrated circuit (IC) or a large scale integrated circuit (LSI), a large number of gate circuits are provided, and for example, an output signal corresponding to a signal input from an input terminal of the LSI appears at the output terminal of the LSI. Up to the delay time due to the above-mentioned gate circuit.

An address scan latch circuit is used to test whether or not this delay time is within the range defined by the standard.

FIG. 2 is a configuration diagram of a main part inside the LSI 1 in which such a delay time measurement is performed.

In the figure, 1 is an LSI, 2a is a signal input terminal, 2b is a signal output terminal, 3a is an OR gate circuit (hereinafter referred to as an OR gate), 3
b and 3c are NOR gate circuits (hereinafter referred to as NOR gates), 3d is OR
The gates 4a and 4b are address scan latch circuits.

The address scan latch circuits 4a and 4b have a signal input terminal 2
It is used to select a path through which a signal input from a passes through a gate circuit inside LSI 1 and a signal corresponding to the input signal appears at signal output terminal 2b.

For example, when the output signal levels of the address scan latch circuits 4a and 4b are H (high) and L (low), respectively, when the signal So indicated by the solid line is input to the signal input terminal 2a, the OR gate 3a.
Reach NOR gates 3b and 3c via
Since the H-level signal is input to the address scan latch circuit 4a, the output signal of the NOR gate 3b is L level.
On the other hand, since the NOR gate 3c receives the L level signal from the address scanning latch circuit 4b, the output signal of the NOR gate 3c is the same as the input signal as indicated by the solid line S ₀ ′. The level matches the level.

Therefore, a signal having a signal level matching the input signal is NO
Output terminal 2b via OR gate 3d via R gate 3c
Appears in.

In this way, when the output signal levels of the address scan circuits 4a and 4b are H and L, respectively, the signal input to the signal input terminal 2a passes through the path of the OR gate 3a, NOR gate 3c, and OR gate 3d (path A ) And appear at the signal output terminal 2b, the signal propagation delay time in the path A can be measured by comparing the signals at the signal input terminal 2a and the signal output terminal 2b.

When the output signals of the address scan latch circuits 4a and 4b are L and H, respectively, the input signals are OR gate 3a, NOR gate 3b, and
It appears at the signal output terminal 2b through the path (path B) of the OR gate 3d.

In this case, the signal propagation delay time in the path B can be measured by comparing the signals at the signal input terminal 2a and the signal output terminal 2b.

In this way, the address scan latch circuits 4a and 4b are used to select a signal propagation path. Address scan latch circuits 4a and 4b are required to reduce the size of the integrated circuit.
It is desirable to reduce the number of gate circuits constituting the.

[Conventional technology]

FIG. 3 is a block diagram of a conventional address scan latch circuit. 5a to 5c are OR gates and 5d is an AND (AN) gate.
D) gate, 6a OR gate, 6b NOR gate, 7a data input terminal, 7b clock signal input terminal, 7c
Is set signal SET input terminal, 7d is scan-in ▲ ▼
Signal input terminals, 7e and 7f are X and Y address signals ▲ ▼,
▲ ▼ Input terminals, and 8a and 8b are signal output terminals.

The OR gates 5a to 5c and the AND gate 5d form a latch circuit.
The gate 6a and the NOR gate 6b form a scan circuit.

The OR gate 5b is called a skew driver, and a sample signal of its output signals is input to the OR gate 5a,
The other output signal, the hold signal, is input to the OR gate 5c. FIG. 4 is a signal waveform diagram for explaining the operation of the address scan latch circuit shown in FIG. 3, in which the data signal D is applied to the terminal 7a and the clock pulse Cp is input to the terminal 7b. And this clock pulse
In synchronization with the fall of Cp, an output signal of the same level (H level or L level) as the data signal D appears at the signal output terminal 8a. The next clock pulse Cp is input to the clock signal input terminal 7b and is also input to the terminal 7a. Data signal D
The signal level appearing at the signal output terminal 8a is held except when the level of the signal is inverted.

The original latch circuit operates as described above, but since the address scan circuit is additionally provided, the signal appearing at the signal output terminal 8a is controlled as follows. Address signal input to X, Y address signal input terminals 7e, 7f when L level scan impulse P _SI is input to terminal 7d
Only when both ▼ and ▲ ▼ are at the L level, the H that appears at the output terminal 8a as shown by the solid line in FIG.
The level signal is inverted to L level.

Therefore, when both of the address signals are at the H level or one of them is at the L level, the H level appearing at the output terminal 8a.
The level signal is retained as it is.

Therefore, the output can be set to the H level or the L level by selecting the address signal level input to the address signal input terminals 7e and 7f.

The set signal SET is for setting the output of the signal output terminal 8a of the address scan latch circuit to the H level. When both the address signals ▲ ▼ and ▲ ▼ are set to L level, a signal in which the level of the signal held in the latch circuit is inverted appears at the terminal 8b.

[Problems to be solved by the invention]

The conventional address scan latch circuit is an OR gate.
A total of four gate circuits 5a to 5c and an AND gate 5d are required, and the address scan latch circuit becomes large,
In particular, there are many cases where a large number of such address scan latch circuits are built in an integrated circuit, which increases the size of the integrated circuit.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an address scan latch circuit that requires a smaller number of gate circuits and becomes smaller.

[Means for solving problems]

 FIG. 1 is a diagram for explaining the principle of the present invention.

9a is a first OR gate circuit that receives the set signal SET and the output signal of the AND gate circuit 9b, and 9b is an AND gate circuit that receives the output signal of the first OR gate circuit 9a and the output signal of the second OR gate circuit 10a. Is.

10b is a NOR gate circuit.

[Action]

When the first OR gate circuit 9a and the AND gate circuit 9b form a latch circuit and the set signal SET is input to the terminal 7c, the output signal Q of the latch circuit becomes H level.

In this state, when a scan impulse is input to the scan-in signal input terminal 7d, both the address signals ▲ ▼ and ▲ ▼ input to the address signal input terminals 7e and 7f are L level.
Only when the level is L, the signal at the output terminal 8a of the latch circuit is L
Level, other than that, address signal ▲
When both ▼ and ▲ ▼ are at H level or when either one of the address signals ▲ ▼ and ▲ ▼ is at H level, the signal at the output terminal 8a of the latch circuit is at H level.

Therefore, when the output signal Q of the latch circuit is set to the L level, both the address signals ▲ ▼ and ▲ ▼ are set to the L level, and when the output signal Q of the latch circuit is set to the H level, the address signals ▲ ▼ and ▲. At least one of ▼ may be set to the H level.

In this way, the output signal level of the latch circuit can be selected by the address signal.

The address scanning latch circuit according to the present invention requires only four gate circuits and is compact.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram for explaining the configuration of an embodiment of the present invention.

The first OR gate circuit (hereinafter referred to as OR gate) 9a and the AND gate circuit (hereinafter referred to as AND gate) 9b form a latch circuit, and the second OR gate (hereinafter referred to as OR gate) 10a and NOR
The gate 10b constitutes a scan circuit.

In order to set the output signal Q of the latch circuit to the H level, as shown in FIGS. 4 (d) and 4 (e), the scan-in signal ▲
Set signal input terminal 7c to H while ▼ is set to H level
Input level set pulse Ps. The set pulse Ps input to the OR gate 9a passes through the OR gate 9a and then is input to the AND gate 9b. Also, AND gate 9b has an OR
The H-level signal (the above-mentioned H-level scan-in signal ▲ ▼) is input from the gate 10a. Therefore, the output signal of the AND gate 9b becomes H level as shown by the alternate long and short dash line in FIG. Since the H level output signal of the AND gate 9b is input to the OR gate 9a, the output of the AND gate 9b holds the H level.

In this way, the output Q of the latch circuit becomes H level by inputting the H level set pulse to the set signal input terminal 7c in the state where the scan-in signal {circle over (H)} is set to H level.

In order to set the output Q of the latch circuit to the L level, the address signal input to the address signal input terminals 7e and 7f
4th with both ▼ and ▲ ▼ set to L level
As shown in the figure (d), L level scan impulse P
Input _SI to scan-in signal input terminal 7d.

Since all the input signals of the OR gate 10a are L level, the output of the OR gate 10a becomes L level, and the L level signal is input to the AND gate 9b.

Therefore, the output of the AND gate 9b becomes L level.

Since this L level signal is input to the OR gate 9a, the OR
It is re-input to the AND gate 9b via the gate 9a, and thereafter, this process is repeated, so that the output of the AND gate 9b is maintained in the L level state.

Thus, in order to set the output Q of the latch circuit to the L level, both the address signals ▲ ▼ and ▲ ▼ input to the address signal input terminals 7e and 7f are set to the L level, and the scan-in signal input terminal 7d is set to the L level. It suffices to input the level scan impulse P _SI .

FIG. 5 is a diagram schematically showing a case where a plurality of address scan latch circuits described in the above-described embodiment are arranged in a matrix.

In the figure, L ₁₁ , L ₁₂ ... L _mn are each the address scan latch circuit described in the above embodiment, and although not shown, the set signal input terminals are connected to each other, and , The scan-in signal input terminals are also connected to each other, so that the set signal and the scan-in signal are commonly applied to the address scan latch circuits.

ADDX and ADDY are X and Y address recorders, BX and BY are X and Y address buses, and X and Y address buses BX and BY are given to X and Y, respectively.
Y addresses X, Y address decoder ADDX, ADDY, is a record, the address signal lines _{PX 1, PX 2, ......... PX} m and PY _1, PY _2, given ......... PY _n.

X address signal lines PX ₁ is the first row address scan latch circuit L _11, L _12, X address signal input terminal X _11, X ₁₂ of ......... L _1n, are commonly connected to ......... X _1n cage, the other X address signal lines PX _2, ... PXm also each similarly second row ... address scan latch circuit L ₂₁ located in the m-th row, L
₂₂ … Lm ₁ , Lm ₂ … Lmn X address signal input terminals X ₂₁ , X ₂₂
… Xm ₁ , Xm ₂ … Xmn are commonly connected.

Y address signal lines PY ₁ , PY ₂ , ... PYn and address scan latch circuits L ₁₁ , L ₂₁ , ... L ₁₂ , L ₂₂ ... L located in each column
The connection relationship between the _1n , L _2n , ... And Y address signal input terminals is also the same. For example, the Y address signal line PY ₁ has the address scan latch circuits L ₁₁ , L ₂₁ , which are located in the first column.
... Lm ₁ Y address signal input terminals Y ₁₁ , Y ₂₁ ... are connected to Ym ₁ .

Given as a set signal SET to the high-level pulse to all the address scan latch circuit L ₁₁ ~Lmn, the output of all of the address scan latch circuit L ₁₁ ~Lmn these has an H level as described above.

Then, select certain of these matrix to provided the address scan latch circuit L ₁₁ ～Lmn, if its output to the L level, as described above, was the particular selection X and Y address signals are applied to the address buses BX and BY in order to apply an L level address signal only to the X and Y address signal input terminals of the address scan latch circuit.

Therefore, only the output of this particular selected address scan latch circuit is at the L level, and the outputs of all other address scan latch circuits are at the H level.

As described above, the output level of only the specific selected address scan latch circuit can be set to the desired L level, and the output signal of the address scan latch circuit thus obtained is used to The signal propagation path as described with reference to FIG. 2 can be selected, and the function as the address scan latch circuit can be achieved.

[Effect of device]

Thus, the address scan latch circuit according to the present invention has two OR gates, one AND gate, and one NOR gate.
Only four gates are required, the number of gates is small, the address scan latch circuit is small, and it is particularly suitable for use in an integrated circuit.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle and configuration of an address scan latch circuit according to the present invention, FIG. 2 is a block diagram of an internal portion of an LSI, and FIG. 3 is a conventional address scan latch circuit. FIG. 4 is a signal waveform diagram for explaining the operation of the address scan latch circuit, and FIG. 5 is a diagram in which the address scan latch circuits are arranged in a matrix. 5a to 5c: OR gate, 5d: AND gate, 6a: OR gate, 6b: NOR gate, 9a: OR gate, 9b: AND gate.

Claims (1)

[Scope of utility model registration request] 1. A first receiving a set signal to one input terminal
OR gate circuit (9a) and the first OR gate circuit (9a)
an AND gate circuit (9b) that receives the output signal of a) at one input terminal is provided, and the output signal of the AND gate circuit (9b) is input to the other input terminal of the first OR gate circuit (9a). Second, receiving scan-in signal and X, Y address signal
An OR gate circuit (10a) and a NOR gate circuit (10b) for receiving the X and Y address signals and the output signal of the AND gate circuit (9b), and the output of the second OR gate circuit (10a) Signal is the AND
An address scan latch circuit characterized by inputting to the other input terminal of the gate circuit (9b).