JPH0921848A - Observation method of internal signal in integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate investigation of LSI internal circuits by outputting an output signal of circuit element within LSI to the outside via a transistor specified within matrix circuit. SOLUTION: An external input terminal 11 of LSI is connected to a clock generating circuit 12, an external input terminal 10 is connected to an FF group 13 for specifying the position in the row direction and an FF group 14 for specifying the position in the column direction. A row decoder 15 and a column decoder 16 are connected to plural transistors constituting a matrix circuit 17. Output terminals of plural transistors constituting the matrix circuit 17 are connected to an external output terminal 18 of LSI. Namely, one transistor within the matrix circuit 17, specified by specifying signals inputted from external terminals 10, 11, is turned on, and the output of the circuit element connected to this transistor is outputted to an output terminal 18. Accordingly, an output signal of an arbitrary circuit element within LSI can be outputted to the outside by a specifying signal, for observation, thereby facilitating the analysis.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of observing an internal signal of an integrated circuit, and more particularly to a method of observing an internal signal in a circuit inside a large scale integrated circuit (LSI).

[0002]

2. Description of the Related Art In recent years, due to steady progress in LSI technology, L
The degree of integration in SI has increased significantly, and the circuit scale to be mounted on a 1-chip LSI has also increased significantly, which has diversified the functions of the LSI, and the number of pins required for 1 chip has also increased. is increasing. However, since the number of input / output pins of the LSI is limited, it is not possible to secure the number of pins required for observing all signals of a large-scale circuit in the LSI in addition to the number of pins required for one chip. It is possible.

[0003]

[Problems to be Solved by the Invention] It is not impossible for some problems to occur when using LSI.
Naturally, a situation that is presumed to be caused by the internal circuit operation of I will occur. However, as described above, it is impossible to further secure the number of pins for observing all signals of a large-scale circuit in the LSI, so the user of the LSI (especially the technician on the set maker side) should make a measurement. In practice, it is extremely difficult to determine the cause of the problem with the instrument, and the cause of the problem cannot be excluded from the estimated range, and further continuous investigation is extremely difficult.

In addition, conventional test data is used to generate an LSI.
Although it is also known to indirectly investigate the internal state of the LSI from the external terminal of the LSI or to investigate it by a model simulation of the LSI developed on a computer, it is difficult to analyze the cause and it requires a great deal of man-hours. There is also a problem that it costs.

[0005] The present invention has been made in view of the above points,
An object of the present invention is to provide a method of observing an internal signal of an integrated circuit, which makes it possible to easily investigate an internal circuit of an LSI by selecting an estimated signal from all signals inside the LSI and outputting it to the outside.

[0006]

In order to achieve the above object, the present invention has an input terminal connected to an output terminal of a predetermined circuit element in an integrated circuit, and an output terminal commonly connected to an external output terminal. A matrix circuit in which a plurality of selected transistors are arranged in a matrix, and one transistor designated by the designation signal among the plurality of transistors in the matrix circuit based on the designation signal input from the external input terminal of the integrated circuit And a decoding circuit that turns on by applying a switching signal to the control terminal of the integrated circuit connected from the input terminal of the designated one transistor to the input terminal of the one transistor through the output terminal The output signal of the element is output to the external output terminal.

Here, the above-mentioned decode circuit specifies a clock generation circuit for generating a clock synchronized with an external clock signal and a row direction position of a plurality of transistors forming a matrix circuit to be inputted from an external input terminal. A row decoding means for designating by a signal and a clock, a column decoding means for designating a position in the column direction among a plurality of transistors forming a matrix circuit by a designating signal and a clock inputted from an external input terminal, and a row decoding means. And a circuit for generating a switching signal based on the output signal of the column decoding means.

That is, according to the present invention, one transistor in the matrix circuit designated by the designation signal inputted from the external input terminal is turned on, and the circuit in the integrated circuit connected to the input terminal of this one transistor. Since the output signal of the element is output to the external output terminal via the one transistor, the output signal of any circuit element in the integrated circuit can be output to the external output terminal by the above-mentioned designation signal.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an image of a circuit formed on one chip for explaining the method of the present invention. As shown in the figure, a large number of gates such as an AND gate 2 and flip-flops 3 and 4 are arranged on an LSI chip 1, and output terminals of these AND gate 2, flip-flops 3 and 4 and the like. In the transistor matrix circuit, a plurality of transistors such as transistors 5, 6 and 7 are connected and arranged in a matrix.
This transistor matrix circuit is a circuit forming an essential part of the method of the present invention. The transistor 5 is, for example, the 1st transistor in the vertical direction and the 1st transistor in the horizontal direction, and the transistor 6 is, for example, the mth transistor in the vertical direction and the nth transistor in the horizontal direction. Further, the transistor 7 is, for example, the j-th transistor in the vertical direction and the k-th transistor in the horizontal direction.

FIG. 2 is a block diagram showing an embodiment of the method of the present invention. In the figure, the external input terminal 10 of the LSI
And 11, the external input terminal 11 is connected to the clock generation circuit 12, and the external input terminal 10 is connected to the flip-flop group 13 for specifying the row direction position and the flip-flop group 14 for specifying the column direction position. There is.

The flip-flop group 13 is composed of M flip-flops, and its output terminal is connected to the row decoder 15. Also, flip-flop group 1
Reference numeral 4 is composed of N flip-flops, the output terminal of which is connected to the column decoder 16. Further, the row decoder 15 and the column decoder 16 are respectively provided with a transistor matrix circuit 17 via a gate circuit (not shown).
Are connected to a plurality of transistors that form the. The output terminals of the plurality of transistors forming the transistor matrix circuit 17 are connected to the external output terminal 18 of the LSI. The clock generation circuit 12, the flip-flop groups 13 and 14, the row decoder 15, the column decoder 16 and the transistor matrix circuit 17 are respectively provided inside the LSI.

Transistors 5, 6 and 7 shown in FIG. 1 are a part of a plurality of transistors forming the transistor matrix circuit 17 shown in FIG.
LSI such as ND gate 2, flip-flops 3 and 4
The circuit elements forming the internal circuit are not shown in FIG.

FIG. 3 shows the relationship between a plurality of transistors forming the above transistor matrix circuit 17 and an LSI internal circuit. 2, the same components as those in FIG. 2 are denoted by the same reference numerals. In FIG. 3, the transistor matrix circuit 17 is composed of M in the vertical direction and N in the horizontal direction, for a total of _MN field effect transistors Q _{11 to} Q _MN .

Of these, the drain (or source) of the transistor Q _K3 is an output terminal of the flip-flop 22 of the flip-flop 22, AND gate 23, and OR gate 24, which constitutes a part of the internal circuit of the LSI, and AN.
It is connected to the connection point with the input terminal of the D gate 23.
The source (or drain) of the transistor Q _K3 is connected to the external output terminal (18 in FIG. 2). Similar to the transistor Q ₁₁ to Q _MN transistor Q _K3 transistor Q _K3 also each transistor other than of, is connected to the output terminal of each circuit element in which one of the drain and source constituting the internal circuit, the other is an external output terminal It is connected to the.

Further, the decoding circuit 21 includes the row decoder 15 and the column decoder 16 shown in FIG.
5 and a column circuit for outputting both of the output signals of the column decoder 16 to generate and output a switching signal. In FIG. 2, for convenience of illustration, the transistor matrix circuit 17 includes the above gate circuit. There is. The gate circuit of the decoding circuit 21, transistor Q ₁₁ to Q
It is provided in a one-to-one correspondence with the _MN and is connected to the gate of the corresponding transistor.

Next, the operation of this embodiment will be described. The clock generation circuit 12 generates a clock synchronized with the clock input signal input from the external input terminal 11. This clock is applied to the clock terminals of the M flip-flops constituting the flip-flop group 13, and the row position designation signals applied to the M flip-flops are fetched from the external input terminal 10 at this time. Then, the output clock of the clock generation circuit 12 is
The column position specifying signals applied to the N flip-flops constituting the flip-flop group 14 are applied to the clock terminals of the N flip-flops, respectively, and are applied to the N flip-flops from the external input terminal 10 at this time.

The row position designation signal and the column position designation signal fetched in each of the flip-flop groups 13 and 14 are supplied to the row decoder 15 and the column decoder 16 provided corresponding to each other, and decoded there. Then, it is applied to each transistor in the transistor matrix circuit 17 through the gate circuit, and only one transistor designated among them is turned on.

Here, for example, the row position "K" and the column position "
3 ”is designated, the output signal from the decoding circuit 21 turns on only the transistor Q _K3 among the transistors Q _{11 to} Q _{MN in} FIG. 3, which causes the output signal of the flip-flop 22 (that is, Internal signal)
Is output to the external output terminal 18 via the transistor Q _K3 in the transistor matrix circuit 17. As a result, the output signal of the flip-flop 22 can be measured and observed by the measuring instrument.

As described above, according to the embodiment of the present invention, the LSI
Matrix-type transistors Q _{11 to} Q _MN , whose input terminals are individually connected to all or most of the circuit elements inside the LSI on the chip, and an arbitrary unique transistor is selected from these transistors Q _{11 to} Q _MN. Flip-flop groups 13, 14 and row decoder 15 and column decoder 1
6 has a selection circuit composed of a gate circuit, one of the transistors in the transistor matrix circuit 17 corresponding to the input designation signal is inputted by inputting a designation signal of a desired value from the external input terminal 10. When turned on, the output signal of the internal circuit element corresponding to the input designation signal in the LSI can be taken out to the external output terminal 18 and observed. As a result, a total of MN internal signals can be selected and observed when the LSI is actually operating, and as a result, the cause of the failure can be analyzed more accurately than in the past.

The present invention is not limited to the above-mentioned embodiment, and for example, as the transistor forming the matrix circuit 17, a bipolar transistor can be used, and other switching elements can also be used. It is possible.

[0021]

As described above, according to the present invention,
The output signal of the circuit element in the integrated circuit designated by the designation signal input from the external input terminal of the integrated circuit is selectively output to the external output terminal through the corresponding one transistor in the matrix circuit. It is possible to observe a desired internal signal in the circuit, thus facilitating the analysis of the malfunction of the integrated circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing an image of a circuit formed on one chip for explaining the method of the present invention.

FIG. 2 is a configuration diagram showing an embodiment of the system of the present invention.

FIG. 3 is a diagram showing a relationship between a plurality of transistors forming a transistor matrix circuit and an LSI internal circuit in the system of the present invention.

[Explanation of symbols]

 1 chip 10, 11 external input terminal 12 clock generation circuit 13, 14 flip-flop group 15 row decoder 16 column decoder 17 transistor matrix circuit 18 external output terminal

Claims (2)

[Claims] 1. A matrix circuit in which a plurality of transistors, each having an input terminal connected to an output terminal of a predetermined circuit element in an integrated circuit and each output terminal commonly connected to an external output terminal, are arranged in a matrix. , A switching signal is applied to a control terminal of one of the plurality of transistors in the matrix circuit designated by the designation signal based on a designation signal input from an external input terminal of the integrated circuit to turn on. And a decoding circuit for converting the output signal of the circuit element in the integrated circuit connected to the input terminal of the one transistor via the output terminal from the input terminal of the designated one transistor to the external output terminal. A method of observing internal signals of an integrated circuit characterized by being configured to output. 2. The clock generating circuit for generating a clock synchronized with an external clock signal, and the decode circuit designating a row direction position of a plurality of transistors forming the matrix circuit to be inputted from the external input terminal. A row decoding means designated by a signal and the clock,
A column decoding means for designating a position in the column direction of a plurality of transistors forming the matrix circuit by the designation signal inputted from the external input terminal and the clock, and an output signal of the row decoding means and the column decoding means. The method for observing an internal signal of an integrated circuit according to claim 1, further comprising a circuit that generates the switching signal based on the switching signal.