JPH07161900A - Surface mount type semiconductor package - Google Patents

Surface mount type semiconductor package

Info

Publication number
JPH07161900A
JPH07161900A JP30316293A JP30316293A JPH07161900A JP H07161900 A JPH07161900 A JP H07161900A JP 30316293 A JP30316293 A JP 30316293A JP 30316293 A JP30316293 A JP 30316293A JP H07161900 A JPH07161900 A JP H07161900A
Authority
JP
Japan
Prior art keywords
lead
leads
base portion
semiconductor package
surface mount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30316293A
Other languages
Japanese (ja)
Inventor
Toru Sasaki
徹 佐々木
Katsushi Ono
勝史 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Facom Corp
Original Assignee
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Facom Corp filed Critical Fuji Facom Corp
Priority to JP30316293A priority Critical patent/JPH07161900A/en
Publication of JPH07161900A publication Critical patent/JPH07161900A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To widen the lead-row-direction intervals of pads on a printed wiring board side corresponding to leads maintaining a density, and to raise the ratio of pattern wiring between them. CONSTITUTION:Two kinds of leads are provided side by side on both, right and left, side surfaces of a semiconductor package 10 alternately. The first kind is a lead 11 and is formed by bending into the shape of a letter Z, and its lower side part is a base part 11a to be connected and fixed. The second kind is a lead 12, and if it is a right-hand side one it is formed by bending in an intermediate part so that its base part 12a may be positioned near and at the right-hand outside of the base part 11a of an adjoining lower side lead 11. This intermediate part is bent into the shape of a crank. Accordingly, the pitches of respective base parts 11a and 12a of respective kinds leads 11 and 12 adjoining each other in the directions of the lead rows are twice as large as the former ones, since their intermediate ones are thinned out seemingly.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、リードが導通固着さ
れるべきプリント配線板側パッドの、リード列方向の間
隔を広げ、その間のパターン配線率の向上が図れるよう
に、リードの形状,配置を改善した表面実装形半導体パ
ッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the shape and arrangement of the leads so that the spacing between the pads on the printed wiring board side to which the leads are electrically connected and fixed can be widened and the pattern wiring rate can be improved in the meantime. The present invention relates to a surface mount type semiconductor package having improved.

【0002】[0002]

【従来の技術】従来例について、図6〜図8を参照しな
がら説明する。図6はその平面図、図7はその要部の斜
視図、図8はプリント配線板の要部の平面図である。図
6において、半導体パッケージ30の左右の側面に、リー
ド31が並設される。このリード31は、図7 に示すよう
に、Z字形に折り曲げられ、その下辺部を導通固着され
るべきベース部31a とする。このリード31のベース部31
a が導通固着される、相手側のパッド32は、図8 に示さ
れるように、プリント配線板34に配線パターン33ととも
に形成された導通矩形領域である。
2. Description of the Related Art A conventional example will be described with reference to FIGS. FIG. 6 is a plan view of the same, FIG. 7 is a perspective view of an essential part thereof, and FIG. 8 is a plan view of an essential part of the printed wiring board. In FIG. 6, leads 31 are arranged in parallel on the left and right side surfaces of the semiconductor package 30. As shown in FIG. 7, the lead 31 is bent into a Z shape, and its lower side portion is used as a base portion 31a to be electrically fixed. The base portion 31 of this lead 31
The mating pad 32 to which a is conductively fixed is a conductive rectangular area formed together with the wiring pattern 33 on the printed wiring board 34, as shown in FIG.

【0003】さて、最近の半導体パッケージでは、その
プリント配線板における回路部品の実装密度向上の要請
のために、SOP(Small Outline Package)の例にみる
ように、そのリード間ピッチを、0.5 mm程度に狭くして
ある。ところが、図8 に示すように、プリント配線板34
の隣り合うパッド32の間隔gが狭くなって、その間に配
線パターン33を通せなくなる。無理をすると、安全な絶
縁距離が保証されないため品質上問題になる。その改善
策として、特開平3-74866 号公報に記載の発明では、リ
ードを外側方に長く伸びるものと、短いものとの2種類
にし、これを交互に並べ、リード列の方向には同じピッ
チであるが、隣り合うパッド間に間隔を広くとる工夫が
なされている。
In recent semiconductor packages, the pitch between leads is about 0.5 mm as seen in the example of SOP (Small Outline Package) in order to improve the mounting density of circuit components on the printed wiring board. It is narrowed to. However, as shown in Figure 8, the printed wiring board 34
The gap g between the adjacent pads 32 becomes narrower, and the wiring pattern 33 cannot be passed between them. If it is not done, a safe insulation distance cannot be guaranteed, which causes a quality problem. As an improvement measure, in the invention described in Japanese Patent Laid-Open No. 3-74866, there are two types of leads, one that extends outwardly and the other that extends shortly, and they are arranged alternately, and the pitch is the same in the direction of the lead row. However, it is devised to widen the space between adjacent pads.

【0004】[0004]

【発明が解決しようとする課題】特開平3-74866 号公報
に記載の発明には、隣り合うパッド間に間隔を広くとっ
て、その間に配線パターンを通すことができるという長
所がある反面、リードのうち、外側方に長く伸びるもの
によって、占有面積が広くとられ、実装密度の向上が阻
害されるという問題がある。
The invention described in Japanese Patent Application Laid-Open No. 3-74866 has an advantage that a space can be widened between adjacent pads and a wiring pattern can be inserted between them, but the leads can be used. Among them, the one that extends to the outer side has a problem that the occupied area is widened and the improvement of the mounting density is hindered.

【0005】この発明が解決しようとする課題は、従来
の技術がもつ以上の問題点を解消して、実装密度を維持
させながら、リードが導通固着されるべきプリント配線
板側パッドの、リード列方向の間隔を広げ、その間のパ
ターン配線率の向上が図れるように、リードの形状,配
置を改善した表面実装形半導体パッケージを提供するこ
とにある。
The problem to be solved by the present invention is to solve the above-mentioned problems of the prior art, and to maintain the mounting density, the lead row of the printed wiring board side pad to which the leads should be conductively fixed. An object of the present invention is to provide a surface mount type semiconductor package in which leads are improved in shape and arrangement so as to widen the interval in the direction and improve the pattern wiring rate therebetween.

【0006】[0006]

【課題を解決するための手段】請求項1に係る表面実装
形半導体パッケージは、側面に第1,第2の各リードが
交互に並設され、その第1リードは、Z字形で、その下
辺部を導通固着されるべきベース部とし、その第2リー
ドは、そのベース部を、隣り合う一方の側の第1リード
のベース部の外側方に近接して位置させる形に、中間部
で折り曲げ形成されてなる。
A surface mount type semiconductor package according to a first aspect of the present invention has first and second leads alternately arranged on a side surface thereof, the first lead having a Z shape and a lower side thereof. And the second lead is bent at the middle portion so that the second lead is positioned close to the outer side of the base of the first lead on one side adjacent to the first lead. Formed.

【0007】請求項2に係る表面実装形半導体パッケー
ジは、側面に第1,第2の各リードが交互に並設され、
その第1リードは、コ字形で、その下辺部を導通固着さ
れるべきベース部とし、その第2リードは、そのベース
部を、隣り合う一方の側の第1リードのベース部の外側
方に近接して位置させる形に、中間部で折り曲げ形成さ
れてなる。
According to another aspect of the surface mount semiconductor package of the present invention, first and second leads are alternately arranged side by side.
The first lead has a U-shape, and the lower side of the first lead serves as a base portion to be conductively fixed, and the second lead has the base portion on the outer side of the base portion of the first lead on one adjacent side. It is formed by bending in the middle part so as to be positioned close to each other.

【0008】[0008]

【作用】請求項1に係る表面実装形半導体パッケージで
は、側面に交互に並設された第1,第2の各リードのう
ちで、第1リードは、Z字形で、その下辺部を導通固着
されるべきベース部とし、第2リードは、そのベース部
を、隣り合う一方の側の第1リードのベース部の外側方
に近接して位置させる形に、中間部で折り曲げ形成され
るから、リード列方向の隣り合う第1リード同士と、第
2リード同士との各ベース部、および対応する各パッド
のピッチが、従来のものの2倍になる。
In the surface mount type semiconductor package according to the first aspect of the present invention, of the first and second leads arranged alternately on the side surface, the first lead is Z-shaped and the lower side portion thereof is conductively fixed. As the base portion to be formed, the second lead is bent and formed in the intermediate portion so that the base portion is located close to the outer side of the base portion of the first lead on one adjacent side, The pitch of the respective base portions of the first leads and the second leads that are adjacent to each other in the lead row direction and the corresponding pads are twice as large as that of the conventional one.

【0009】請求項2に係る表面実装形半導体パッケー
ジでは、側面に交互に並設された第1,第2の各リード
のうちで、第1リードは、コ字形で、その下辺部を導通
固着されるべきベース部とし、第2リードは、そのベー
ス部を、隣り合う一方の側の第1リードのベース部の外
側方に近接して位置させる形に、中間部で折り曲げ形成
されるから、リード列方向の隣り合う第1リード同士
と、第2リード同士との各ベース部、および対応する各
パッドのピッチが、従来のものの2倍になる。
According to another aspect of the surface mount semiconductor package of the present invention, of the first and second leads arranged alternately on the side surface, the first lead is U-shaped and the lower side thereof is conductively fixed. As the base portion to be formed, the second lead is bent and formed in the intermediate portion so that the base portion is located close to the outer side of the base portion of the first lead on one adjacent side, The pitch of the respective base portions of the first leads and the second leads that are adjacent to each other in the lead row direction and the corresponding pads are twice as large as that of the conventional one.

【0010】[0010]

【実施例】この発明に係る表面実装形半導体パッケージ
の実施例について、以下に図を参照しながら説明する。
図1は第1実施例の平面図、図2は同じくその要部の斜
視図、図3は同じくそのプリント配線板の要部の平面図
である。図1において、半導体パッケージ10の左右の各
側面にリード列が設けられるが、リードに第1,第2の
2種類があり、これが交互に並設される。第1はリード
11で、Z字形に折り曲げ形成され、その下辺部を導通固
着されるべきベース部11a とする。第2はリード12で、
そのベース部12a が、右側について言うと、隣り合う下
側のリード11のベース部11a の右外方に近接して位置す
るように、中間部で折り曲げ形成される。この中間部の
折り曲げは、図2 に示すように、クランク状になされ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a surface mount type semiconductor package according to the present invention will be described below with reference to the drawings.
FIG. 1 is a plan view of the first embodiment, FIG. 2 is a perspective view of a main part thereof, and FIG. 3 is a plan view of a main part of the printed wiring board. In FIG. 1, a lead row is provided on each of the left and right side surfaces of the semiconductor package 10, and there are two types of leads, a first lead and a second lead, which are alternately arranged side by side. First is the lead
At 11, the base portion 11a is bent and formed in a Z shape, and its lower side portion is used as a base portion 11a to be conductively fixed. The second is lead 12,
Speaking of the right side, the base portion 12a is bent and formed at the intermediate portion so as to be located close to the right outside of the base portion 11a of the adjacent lower lead 11. As shown in Fig. 2, the bending of this intermediate part is made into a crank shape.

【0011】したがって、リード列方向の隣り合う各リ
ード11同士と、各リード12同士との各ベース部11a,12a
のピッチは、その中間のものが間引かれた形になって、
従来のものの2倍になる。これに対応して、図3 に示す
ように、プリント配線板1 において、各リード11,12 の
ベース部11a,12a が導通固着されるべき各パッド11b,12
b は、そのリード列方向の隣り合うもの同士の間隔がG
となって、中間のものが間引かれた分だけ、従来の間隔
(図8の間隔g参照)より格段に広くなる。
Therefore, the bases 11a, 12a of the leads 11 adjacent to each other in the lead row direction and the leads 12 adjacent to each other are formed.
The pitch of the middle is thinned out,
It is twice as much as the conventional one. Correspondingly, as shown in FIG. 3, in the printed wiring board 1, the base portions 11a and 12a of the leads 11 and 12 are to be electrically conductively fixed to the pads 11b and 12b.
In b, the distance between the adjacent elements in the lead row direction is G.
Therefore, the distance of the intermediate one is significantly thinned and becomes much wider than the conventional distance (see the distance g in FIG. 8).

【0012】第2実施例について、図4の平面図、図5
の要部の斜視図を参照しながら説明する。図4におい
て、半導体パッケージ20の左右の各側面にリード列が設
けられるが、リードに第1,第2の2種類があり、これ
が交互に並設される。第1はリード21で、図5に示すよ
うに、コ字形に折り曲げ形成され、その下辺部を導通固
着されるべきベース部21a とする。第2はリード22で、
そのベース部22a が、右側について言うと、隣り合う下
側のリード21のベース部21a の右外方に近接して位置す
るように、中間部で折り曲げ形成される。この中間部の
折り曲げは、図2に示すように、クランク状になされ
る。したがって、リード列方向の隣り合う各リード21同
士と、各リード22同士との各ベース部21a,22a のピッチ
は、その中間のものが間引かれた形になって、第1実施
例におけると同様に従来のものの2倍になり、対応する
各パッドについても間隔が広くなる。
FIG. 5 is a plan view of the second embodiment, and FIG.
It will be described with reference to a perspective view of the main part of FIG. In FIG. 4, lead rows are provided on each of the left and right side surfaces of the semiconductor package 20, and there are two types of leads, the first and second types, which are alternately arranged in parallel. The first is a lead 21, which is bent and formed in a U-shape as shown in FIG. 5, and has a lower side portion as a base portion 21a to be conductively fixed. The second is lead 22,
Speaking of the right side, the base portion 22a is bent and formed at an intermediate portion so as to be located close to the right outside of the base portion 21a of the adjacent lower lead 21. The bending of the intermediate portion is made into a crank shape as shown in FIG. Therefore, the pitches of the base portions 21a, 22a between the leads 21 adjacent to each other in the lead row direction and between the leads 22 are such that the intermediate ones are thinned out. Similarly, it is twice as large as that of the conventional one, and the spacing between the corresponding pads is also widened.

【0013】ここで、第1実施例と第2実施例の特長の
違いについて述べる。第1実施例では、一方のリード11
のベース部11aが外側に折り曲げられるから、他方のリ
ード12の外側方に張り出す量が大きくなり、それだけ占
有面積が広くなる不利をもつ反面、各リード11,12の導
通固着の状態検査が容易になり品質保証が十分にでき
る。第2実施例では、一方のリード21のベース部21aが
内側に折り曲げられるから、他方のリード22の外側方に
張り出す量が小さくなり、それだけ占有面積が小さく抑
えられる利点をもつ反面、一方のリード21の導通固着の
状態検査がやや困難で、十分な品質保証をやや阻害する
おそれがある。
Differences in features between the first embodiment and the second embodiment will now be described. In the first embodiment, one lead 11
Since the base portion 11a of B is bent outward, the amount of protrusion of the other lead 12 to the outside becomes large, which has the disadvantage of occupying a larger area. On the other hand, it is easy to inspect the state of conduction fixation of the leads 11 and 12. The quality can be fully guaranteed. In the second embodiment, since the base portion 21a of one lead 21 is bent inward, the amount of protrusion of the other lead 22 to the outside becomes small, which has the advantage that the occupying area can be kept small. It is rather difficult to inspect the state of continuity and fixation of the leads 21, and there is a possibility that sufficient quality assurance may be slightly hindered.

【0014】[0014]

【発明の効果】請求項1または2に係る表面実装形半導
体パッケージでは、いずれもリード列方向の隣り合う第
1リード同士と、第2リード同士との各ベース部、およ
び対応する各パッドのピッチが、従来のものの2倍にな
る。したがって、実装密度を維持させながら、リードが
導通固着されるべきプリント配線板側のパッドの間隔が
2倍近く広がり、ひいてはその間のパターン配線率の向
上、またはパターン接触による異常発生率の低下が図れ
る。両者の違いとして、一方の請求項1に係る表面実装
形半導体パッケージでは、第1リードが外側に折り曲げ
られるから、第1リードの導通固着の状態検査が容易に
なり、品質保証が十分できる。他方の請求項2に係る表
面実装形半導体パッケージでは、第1リードが内側に折
り曲げられるから、全体として外側方に張り出す量が小
さくなり、それだけ占有面積が小さく抑えられる。
In the surface mount type semiconductor package according to the first or second aspect of the present invention, the base portions of the first leads and the second leads, which are adjacent to each other in the lead row direction, and the pitch of the corresponding pads are provided. However, it is twice as much as the conventional one. Therefore, while maintaining the mounting density, the distance between the pads on the side of the printed wiring board to which the leads are to be conductively fixed is expanded nearly twice, and consequently the pattern wiring rate during that time can be improved or the abnormality occurrence rate due to the pattern contact can be reduced. . The difference between the two is that, in the surface mount type semiconductor package according to claim 1, the first lead is bent outward, so that it is easy to inspect the state of conduction fixation of the first lead, and sufficient quality assurance can be ensured. On the other hand, in the surface mount type semiconductor package according to the second aspect, since the first lead is bent inward, the amount of protrusion to the outside is reduced as a whole, and the occupied area is suppressed to that extent.

【図面の簡単な説明】[Brief description of drawings]

【図1】発明に係る第1実施例の平面図FIG. 1 is a plan view of a first embodiment according to the invention.

【図2】第1実施例の要部の斜視図FIG. 2 is a perspective view of a main part of the first embodiment.

【図3】第1実施例のプリント配線板の要部の平面図FIG. 3 is a plan view of a main part of the printed wiring board according to the first embodiment.

【図4】発明に係る第2実施例の平面図FIG. 4 is a plan view of a second embodiment according to the invention.

【図5】第2実施例の要部の斜視図FIG. 5 is a perspective view of an essential part of the second embodiment.

【図6】従来例の平面図FIG. 6 is a plan view of a conventional example.

【図7】従来例の要部の斜視図FIG. 7 is a perspective view of a main part of a conventional example.

【図8】従来例のプリント配線板の要部の平面図FIG. 8 is a plan view of a main part of a conventional printed wiring board.

【符号の説明】[Explanation of symbols]

1 プリント配線板 2 配線パターン 10 半導体パッケージ 11 リード(第1) 11a ベース部 11b パッド 12 リード(第2) 12a ベース部 12b パッド 20 半導体パッケージ 21 リード(第1) 21a ベース部 22 リード(第2) 22a ベース部 1 printed wiring board 2 wiring pattern 10 semiconductor package 11 lead (first) 11a base portion 11b pad 12 lead (second) 12a base portion 12b pad 20 semiconductor package 21 lead (first) 21a base portion 22 lead (second) 22a base part

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】側面に第1,第2の各リードが交互に並設
され、その第1リードは、Z字形で、その下辺部を導通
固着されるべきベース部とし、その第2リードは、その
ベース部を、隣り合う一方の側の第1リードのベース部
の外側方に近接して位置させる形に、中間部で折り曲げ
形成されてなることを特徴とする表面実装形半導体パッ
ケージ。
1. A first lead and a second lead are alternately arranged side by side on a side surface, the first lead is Z-shaped, and a lower side portion thereof is a base portion to be conductively fixed, and the second lead is A surface mount type semiconductor package, characterized in that the base portion is bent and formed in an intermediate portion so that the base portion is located close to the outer side of the base portion of the first lead on one adjacent side.
【請求項2】側面に第1,第2の各リードが交互に並設
され、その第1リードは、コ字形で、その下辺部を導通
固着されるべきベース部とし、その第2リードは、その
ベース部を、隣り合う一方の側の第1リードのベース部
の外側方に近接して位置させる形に、中間部で折り曲げ
形成されてなることを特徴とする表面実装形半導体パッ
ケージ。
2. A first side and a second side are alternately arranged side by side on the side surface, the first lead is U-shaped, and the lower side thereof is a base portion to be conductively fixed, and the second lead is A surface mount type semiconductor package, characterized in that the base portion is bent and formed in an intermediate portion so that the base portion is located close to the outer side of the base portion of the first lead on one adjacent side.
JP30316293A 1993-12-03 1993-12-03 Surface mount type semiconductor package Pending JPH07161900A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30316293A JPH07161900A (en) 1993-12-03 1993-12-03 Surface mount type semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30316293A JPH07161900A (en) 1993-12-03 1993-12-03 Surface mount type semiconductor package

Publications (1)

Publication Number Publication Date
JPH07161900A true JPH07161900A (en) 1995-06-23

Family

ID=17917635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30316293A Pending JPH07161900A (en) 1993-12-03 1993-12-03 Surface mount type semiconductor package

Country Status (1)

Country Link
JP (1) JPH07161900A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1134418A2 (en) 2000-03-15 2001-09-19 SANYO ELECTRIC Co., Ltd. Rotary compressor
JP2009094322A (en) * 2007-10-10 2009-04-30 Nichia Corp Light emitting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1134418A2 (en) 2000-03-15 2001-09-19 SANYO ELECTRIC Co., Ltd. Rotary compressor
JP2009094322A (en) * 2007-10-10 2009-04-30 Nichia Corp Light emitting device

Similar Documents

Publication Publication Date Title
JP2538107B2 (en) Method for manufacturing high density semiconductor module
KR100281216B1 (en) Semiconductor devices
US6121690A (en) Semiconductor device having two pluralities of electrode pads, pads of different pluralities having different widths and respective pads of different pluralities having an aligned transverse edge
US5324985A (en) Packaged semiconductor device
JPH07161900A (en) Surface mount type semiconductor package
US7193158B2 (en) Wiring board device
JPH03289162A (en) Surface-mount type electronic component
JP2947244B2 (en) Semiconductor device
JP3334798B2 (en) BGA type semiconductor device
JPH0618246B2 (en) Semiconductor device
JPS62188350A (en) Lead frame
JPH01205456A (en) Multi-pin case for lsi
JPH04237154A (en) Semiconductor package
JPS63128654A (en) Semiconductor device mounting body
KR0125869Y1 (en) Semiconductor Integrated Circuit Package Structure for Memory Module
JPH09232498A (en) Semiconductor device
EP0918378A1 (en) A platelike member
JP3256073B2 (en) IC socket
JP3118272B2 (en) Electrical connector
KR200273960Y1 (en) connector for module I.C
JP2000236155A (en) Package of surface mount components
JP3164084B2 (en) Semiconductor device frame
JPS6252996A (en) Part mounting pad for printed circuit board
JPH07297527A (en) Printed board
GB2224164A (en) An Improved circuit board