JPH071675Y2 - TFT matrix array - Google Patents
TFT matrix arrayInfo
- Publication number
- JPH071675Y2 JPH071675Y2 JP1988122451U JP12245188U JPH071675Y2 JP H071675 Y2 JPH071675 Y2 JP H071675Y2 JP 1988122451 U JP1988122451 U JP 1988122451U JP 12245188 U JP12245188 U JP 12245188U JP H071675 Y2 JPH071675 Y2 JP H071675Y2
- Authority
- JP
- Japan
- Prior art keywords
- bus line
- tft
- matrix array
- terminal
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011159 matrix material Substances 0.000 title claims description 12
- 238000005530 etching Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 2
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 230000007547 defect Effects 0.000 description 5
- 238000007689 inspection Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Liquid Crystal Display Device Control (AREA)
Description
【考案の詳細な説明】 （イ）産業上の利用分野 本考案はアクティブマトリクス型の液晶表示素子に用い
られるTFTマトリクスアレイに関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a TFT matrix array used for an active matrix type liquid crystal display device.
（ロ）従来の技術 マトリックス状にTFTを形成して成るアクティブマトリ
ックス方式液晶パネルは、高品位な表示が得られること
から注目されている。しかしながら、アクティブマトリ
ックス方式液晶パネルは、製造プロセスが多く、構造も
複雑であることからドレインバスラインやゲートバスラ
イン等の各配線電極の断線及び配線電極のクロスオーバ
ー部でのシヨートなどの欠陥が多発する惧れがあった。(B) Conventional technology An active matrix type liquid crystal panel formed by forming TFTs in a matrix shape is drawing attention because it can provide high-quality display. However, since the active matrix type liquid crystal panel has many manufacturing processes and a complicated structure, defects such as disconnection of each wiring electrode such as a drain bus line and a gate bus line and a short at a crossover portion of the wiring electrode frequently occur. There was a fear of doing it.
（ハ）考案を解決しようとする課題 上述の欠陥対策として、デバイス構造などに欠陥救済の
ためにバイパスラインの追加を行なった冗長構成が必要
となる（実開昭61−181号）。このような何らかの冗長
構成と同時に欠陥発生場所を探し出す検査工程がパネル
製造には不可欠となる。欠陥発生場所を探し出すために
端子又は画素領域に対応してそのアドレスを教えるため
の何らかのマークが必要であり、本考案はその要求を満
たすためのものである。(C) Problem to be solved by the invention As a countermeasure against the above-mentioned defects, a redundant configuration in which a bypass line is added to the device structure to relieve the defect is required (Actual Development No. 61-181). An inspection process for finding a defect occurrence location at the same time as such a redundant configuration is indispensable for panel manufacturing. In order to find the location of the defect, some mark for teaching the address corresponding to the terminal or the pixel area is required, and the present invention satisfies the demand.
（ニ）課題を解決するための手段 本考案のTFTマトリクスアレイは、ゲートバスライン用
端子又はドレインバスライン用端子自体に、エッチング
除去によって形成されたアドレスに相当する数字パター
ンが刻印したものである。(D) Means for Solving the Problems In the TFT matrix array of the present invention, a gate bus line terminal or a drain bus line terminal itself is engraved with a numerical pattern corresponding to an address formed by etching removal. .
（ホ）作用 本考案によれば、端子に直接そのラインのアドレス番号
を刻印しているので、TFT検査工程でのアドレス確認が
容易に行なえる。(E) Function According to the present invention, the address number of the line is directly stamped on the terminal, so that the address can be easily confirmed in the TFT inspection process.
（ヘ）実施例 第２図は液晶表示パネル用のTFTマトリクスアレイの平
面図であり、240本のゲートバスラインとその端子電極
Ｇ及び480本のドレインバスラインとその端子電極Ｄが
接続され、各ラインの交点には表示電極（省略）をソー
ス側に結合したTFT（省略）が形成されている。(F) Example FIG. 2 is a plan view of a TFT matrix array for a liquid crystal display panel, in which 240 gate bus lines and their terminal electrodes G and 480 drain bus lines and their terminal electrodes D are connected, A TFT (omitted) in which a display electrode (omitted) is coupled to the source side is formed at the intersection of each line.
第１図は第２図のゲートバスライン用の端子電極Ｇの配
列平面図であり、アドレス番号１〜11の端子を示してい
る。FIG. 1 is a plan view showing the arrangement of the terminal electrodes G for the gate bus line in FIG. 2, showing the terminals with address numbers 1 to 11.
同図の端子電極Ｇは例えばアルミニウからなり、これを
パターンニングする祭に、同時にアドレスに相当する番
号Ｎをエッチング除去する事によって、アドレス表示が
行なわれる。The terminal electrode G in the figure is made of, for example, aluminum, and at the same time as patterning this, the number N corresponding to the address is removed by etching to display the address.
尚、ドレインバスライン用端子電極Ｄも同様にアドレス
表示が可能である。The address can be similarly displayed on the drain bus line terminal electrode D.
（ト）考案の効果 本考案によれば、TFTの検査工程において必要な端子の
アドレスが刻印番号を目視する事によって、容易に判別
でき、この検査工程の効率向上が望める。(G) Effect of the Invention According to the present invention, the address of the terminal required in the TFT inspection process can be easily identified by visually checking the engraved number, and the efficiency of this inspection process can be improved.
第１図は本考案のTFTマトリクスアレイの要部平面図、
第２図はTFTマトリクスアレイの平面模式図である。 Ｇ…ゲートバスライン用端子電極、Ｄ…ドレインバスラ
イン用端子電極、Ｎ…アドレス番号。FIG. 1 is a plan view of a main portion of a TFT matrix array of the present invention,
FIG. 2 is a schematic plan view of a TFT matrix array. G ... Gate bus line terminal electrode, D ... Drain bus line terminal electrode, N ... Address number.
Claims (1)
タ）をマトリクス配置し、該TFTの配線電極であるゲー
トバスライン又はドレインバスラインと絶縁基板周辺位
置に設けたゲートバスライン用端子又はドレインバスラ
イン用端子とを接続した端子構造を有するTFTマトリク
スアレイに於いて、 上記端子自体に、エッチング除去によって形成された数
字パターンが刻印されていることを特徴としたTFTマト
リクスアレイ。1. A plurality of TFTs (thin film transistors) are arranged in a matrix on an insulating substrate, and a gate bus line or a drain bus line which is a wiring electrode of the TFT and a gate bus line terminal or a drain bus provided at a peripheral position of the insulating substrate. What is claimed is: 1. A TFT matrix array having a terminal structure in which line terminals are connected, wherein the terminals themselves are engraved with a numeral pattern formed by etching removal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988122451U JPH071675Y2 (en) | 1988-09-19 | 1988-09-19 | TFT matrix array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988122451U JPH071675Y2 (en) | 1988-09-19 | 1988-09-19 | TFT matrix array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0245529U JPH0245529U (en) | 1990-03-28 |
| JPH071675Y2 true JPH071675Y2 (en) | 1995-01-18 |
Family
ID=31370398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988122451U Expired - Lifetime JPH071675Y2 (en) | 1988-09-19 | 1988-09-19 | TFT matrix array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071675Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0623893U (en) * | 1992-06-24 | 1994-03-29 | 株式会社新来島どっく | Anchor chain root stop structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62120732U (en) * | 1986-01-21 | 1987-07-31 |
-
1988
- 1988-09-19 JP JP1988122451U patent/JPH071675Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0245529U (en) | 1990-03-28 |
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