JPH0720077B2 - Compression buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is suitable for use in satellite communication systems.

The present invention relates to a compression buffer circuit of a time division multiple access communication device. In particular, a packet buffer is applied to a time division multiple access communication device (hereinafter referred to as a TDMA communication device), and even if one burst in a TDMA frame is shared by multiple stations, a compression buffer that does not cause a burst collision on the satellite Regarding the circuit.

〔Overview〕

The present invention relates to a case where a packet communication system is applied to a TDMA communication system by transmitting a signal requesting transmission together with data when data needs to be transmitted from a ground station in a compression buffer circuit of a TDMA communication device. However, it is designed so that burst collision does not occur on the satellite.

[Conventional conventional]

A conventional compression buffer circuit is composed of a channel data storage circuit, a write / read switching circuit and an address control circuit,
The channel-multiplexed terrestrial system data string is sequentially written to the channel data storage circuit corresponding to the address designated by the address control circuit, and the written channel multiplexed data is designated by the address control circuit at the time designated by the satellite system timing. The circuit configuration is such that the addresses are sequentially output in the order of the address.

[Problems to be solved by the invention]

However, in such a conventional compression buffer circuit, the burst data string corresponding to the channel designated by the satellite timing is unconditionally output even if the channel data is not inserted in the terrestrial channel data string. Is
The TDMA burst structure was formed and output from the TDMA communication device.

In such a compression buffer circuit, burst allocation is fixed in the TDMA communication system, and there is no problem in the case where each burst in the TDMA frame is an occupied burst for each station of the TDMA participating station. When a single burst in a TDMA frame is shared by multiple TDMA participating stations as in the packet communication method as a transmission path, there is a drawback that burst collisions occur constantly on the satellite and communication becomes impossible. Was there.

The present invention solves the above-mentioned drawbacks and a compression buffer circuit in which burst collision does not occur on a satellite even when a packet communication system is applied to a TDMA communication system and a plurality of stations share one burst in a TDMA frame. The purpose is to provide.

[Means for solving problems]

The present invention relates to a channel data storage circuit (20) for temporarily storing a terrestrial data string having a frame structure to convert it into a burst signal, and a channel data storage circuit for this channel data storage circuit based on input terrestrial system timing and satellite system timing. In a compression buffer circuit of a time division multiple access communication device equipped with a write / read control circuit (30) for performing write / read control, this signal is sent based on a channel data transmission request signal corresponding to the input terrestrial data string. A channel on / off information storage means (40) for storing the channel in which the channel exists and a latch means (50) for latching the output of the channel on / off information recording means and outputting a burst on / off control signal. The circuit provides a write control signal to the channel on / off information storage means based on the channel data transmission request signal. That the write control means (part of 33),
Latch timing control means (a part of 31) for applying a latch timing signal to the latch means is included.

[Action]

The channel data storage circuit stores a channel multiplexed data string forming an terrestrial frame structure input from the outside in correspondence with an address designated by the write / read control circuit.
The channel data transmission request signal of each channel corresponding to the channel multiplexed data string is input to the channel on / off information storage circuit, and the channel for which the channel data transmission request signal indicates the transmission request is addressed by the write / read control circuit. Write the request status to be sent to. That is, the burst transmission request signal of the burst whose transmission request corresponds to the receiving channel is stored. Next, immediately after the burst transmission request signal is read corresponding to the address designated by the write / read control circuit according to the satellite timing designation, the burst address transmission request signal is cleared, and the initial state is restored. In preparation for input of a channel data transmission request signal in the write mode. The latch timing control means outputs a latch timing signal, the latch means latches the output of the channel on / off information storage circuit in accordance with this latch timing signal, and a burst on / off control signal for controlling "on" and "off" of the burst. Output.
By the above operation, burst collision can be prevented even when the packet communication system is applied to the TDMA communication system.

〔Example〕

 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a compression buffer circuit according to an embodiment of the present invention.

Here, the feature of the present invention is the burst transmission request portion surrounded by the alternate long and short dash line shown in FIG. That is, the channel data transmission request signal 101 is input to the input terminal 1 from outside the figure. The channel data transmission request signal 101 is connected from the input terminal 1 to one input of the AND gate 10.

Terrestrial channel multiplexed data string 102 is input terminal 2 from outside the figure.
And the terrestrial channel multiplexed data string 102 is connected to the data input of the channel data storage circuit 20 from the input terminal 2.

The ground system timing signal 103 is connected to the input terminal 3 from outside the figure, and the ground system timing signal 103 is connected from the input terminal 3 to the ground system timing input of the address control circuit 31 and the input of the write / read switching circuit 32.

In the read / write switching circuit 32, a signal of 1 TDMA frame cycle is created, and this signal is further divided by 1/2. The write / read switching signal 32 is sent from the write / read switching circuit 32 to the address control circuit 3
1 and a write / read switching input of write control circuit 33.

From outside the figure, the TDMA frame timing signal 105 and the burst start signal 106 are connected to the TDMA frame timing signal input and the burst start signal input of the address control circuit 31.

The channel data transmission request signal 101 is connected to the channel data transmission request signal input of the write control circuit 33 from the input terminal 1. The latch timing signal 107 is connected from the address control circuit 31 to the other input of the AND gate 10 and the latch timing signal input of the write control circuit 33.

The channel data transmission request signal 101 from the AND gate 10 is prohibited only in the section designated by the latch timing signal 107, and is connected as the output signal 108 to the channel data transmission request signal input of the channel on / off information storage circuit 40. The write timing signal 109 of the channel on / off information from the write control circuit 33 is connected to the write timing signal input of the channel on / off information storage circuit 40, and the address control signal 110 ₁ from the address control circuit 31 sends the channel on / off information storage circuit 40. Is connected to the address control signal input of. When the write timing signal 109 is input, the data transmission request signal is written to the address specified by the address control signal 110 ₁ in the channel on / off information storage circuit 40, and when the write timing signal 109 is not input, the address is output. Control signal 1
10 ₁ data sending request signal stored in the address specified by the is output as an output signal 111 is connected to the data transmission request signal input of the latch circuit 50. Further, the latch timing signal 107 from the address control circuit 31 is connected to the latch timing signal input of the latch circuit 50, and the output signal 111 is latched. Burst on / off signal from latch circuit 50
112 is connected to the output terminal 6.

The write timing signal 113 from the write control circuit 33 is connected to the write timing signal input of the channel data storage circuit 20, and the address control signal 110 ₂ from the address control circuit 31 is connected to the address control signal input of the channel data storage circuit 20. To be done. When the write timing signal 113 is input,
The terrestrial channel multiplexed data string 102 is written at the address designated by the address control signal 110 ₂ . When the write timing signal 113 is not input, the terrestrial channel multiplexed data sequence 102 stored at the address designated by the address control signal 110 ₂ is read out and connected to the output terminal 7 as the burst data signal 114.

The operation of the compression buffer circuit having such a configuration will be described. In FIG. 1, the channel data storage circuit 20 is
Terrestrial channel multiplexed data sequence 102 forming the terrestrial system frame structure input from the input terminal 2, write / read control circuit 30
From the write timing signal 113 and the address control signal 110 ₂ output from the write / read control circuit 30 are input to the address designated by the address control signal 110 _{2 at the} timing designated by the write timing signal 113. The terrestrial channel multiplexed data string 102 is written, and the stored data content is output corresponding to the address designated by the address control signal 110 _{2 in the} section where the write timing signal 113 does not exist.

The channel on / off information storage circuit 40 specifies the channel data transmission request signal 101 corresponding to the terrestrial channel multiplexed data string 102 input from the input terminal 1 by the latch timing signal 107 output from the write / read control circuit 30. Only the section is banned at AND gate 10, AND gate 10
Of the write / read control circuit 3 using the timing 109 input as the output signal 108 of the write / read control circuit 30 of FIG.
The read address specified by the address control signal 110 ₁ for writing and reading the channel data transmission request signal output from 0, and the read address designated by the address control signal 110 _{1 in the} section where the write timing signal 109 does not exist The channel data transmission request signal stored corresponding to is output.

The output signal 111 of the channel on / off information storage circuit 40 is latched by the latch circuit 50 at the timing instructed by the latch timing signal 107 output from the write / read control circuit 30, and is output as the burst on / off control signal 112 at the output terminal 6. Is output from. The latch timing signal 107 is supplied to the latch circuit 50 and also to the AND gate 10, inhibits the channel data transmission request signal 101, and supplies the output signal 108 to the channel on / off information storage circuit 40.
The channel on / off information storage circuit 40 uses the write timing of the write timing signal 109 at the timing of the latch timing signal 107 to clear the stored content corresponding to the read address designated by the address control signal 110 ₁ , and waits for the next write. Enter the state. That is, the channel data transmission request signal stored for each channel clears the state of this channel after reading the transmission request signal of this channel, and waits for the next writing to this channel.

The write / read control circuit 30 includes a write / read switching circuit 32, a write control circuit 33, an address control circuit 31, etc., and generates a write / read control signal for the channel on / off information storage circuit 40 and the channel data storage circuit 20. It is a circuit to do.

The write / read switching circuit 32 inputs the terrestrial system timing signal 103, counts the terrestrial system timing signal 103, creates a signal of 1 TDMA frame period, and further divides this signal by half to divide the TDMA frame period. Outputs a write / read switching signal 104 defining a write area and a read area of the memory circuit.

The address control circuit 31 inputs the terrestrial system timing signal 103, the write / read switching signal 104, the TDMA frame timing signal 105 and the burst start signal 106, and the terrestrial system in the section where the write / read switching signal 104 indicates the writing area. The timing signal 103 is counted, the channel data transmission request signal 101 and the address control signals 110 ₁ and 110 ₂ corresponding to the terrestrial channel multiplexed data sequence 102 are output, and the write / read switching signal 10
In the section where 4 designates the read area of the channel on / off information storage circuit 40 and the channel data recording circuit 20, satellite system timing is counted using the TDMA frame timing signal 105 and burst start signal 106, and the channel on / off information storage circuit 40 and channel The read address designation signal of the data storage circuit 20 is output as the address control signals 110 ₁ and 110 ₂ , and at the same time the latch timing signal 107 is output.

The write control circuit 33 inputs the write / read switching signal 104, the data transmission request signal 101, and the timing signal 107, and the write / read switching signal 104 writes the write areas of the channel on / off information storage circuit 40 and the channel data storage circuit 20. The write timing signal 113 corresponding to the terrestrial channel multiplexed data sequence 102 is output in the section instructing
The write timing signal 109 of the channel on / off information storage circuit 40 is output at the timing when 01 indicates the channel data transmission request state.

Further, in the section in which the write / read switching signal 104 indicates the read areas of the channel on / off information storage circuit 40 and the channel data storage circuit 20, the write timing signal 109 of the channel on / off information storage circuit 40 is set using the timing of the timing signal 107. Output. That is, the channel on / off information storage circuit 40 outputs the content of the address designated by the address control signal 110 ₁ in the read area as the output signal 111, and the output signal 111 is latched by the latch circuit 50 and at the same time, the content of this address. It is the operation to write and specify to clear.

FIG. 2 is a time chart of signals of various parts of the compression buffer circuit of the present invention.

〔The invention's effect〕

As described above, according to the present invention, it becomes possible to realize the transmission control of the verse corresponding to the call, and to detect the transmission request state of this channel even in the request period of the call, that is, even when the transmission packet data is 1 TDMA frame or less. , Has an excellent effect of enabling burst transmission (packet data transmission).

[Brief description of drawings]

FIG. 1 is a block diagram of a compression buffer circuit according to an embodiment of the present invention. FIG. 2 is a time chart of signals at various parts of the compression buffer circuit of the present invention. 1 to 3 ... input terminal, 4 to 7 ... output terminal, 10 ... AND gate, 20 ... channel data storage circuit, 30 ... write / read control circuit, 31 ... address control circuit, 32 ... book Integrated read / write switching circuit, 33 ... Write control circuit, 40 ... Channel on / off information storage circuit, 50 ... Latch circuit, 101 ... Channel data transmission request signal, 102 ... Terrestrial channel multiplexed data sequence, 103 ... Terrestrial system timing signal, 104 ... Write / read switching signal, 105 ... TDMA frame timing signal, 106
... Burst start signal, 107 ... Latch timing signal, 108, 111 ... Output signal, 109, 113 ... Write timing signal, 112 ... Burst on / off control signal, 114 ...
Burst data signal.

Claims (1)

[Claims] 1. A channel data storage circuit (20) for temporarily storing a frame-structured terrestrial data string to convert it into a burst signal, and this channel data storage circuit based on input terrestrial system timing and satellite system timing. In a compression buffer circuit of a time division multiple access communication device having a write / read control circuit (30) for performing write / read control of the above, based on a channel data transmission request signal corresponding to the input terrestrial data string, A channel on / off information storage means (40) for storing a channel in which a signal exists, and an output of the channel on / off information storage means are latched,
Latch means (50) for outputting a burst on / off control signal
And a write control means (a part of 33) for applying a write control signal to the channel on / off information storage means on the basis of the channel data transmission request signal, and a latch means. And a latch timing control means (a part of 31) for giving a latch timing signal.