JPH07221122A - Schottky gate field effect transistor and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a Schottky gate field effect transistor having a high breakdown voltage and a manufacturing method thereof. [Structure] An n-type GaAs operating layer is formed on the semi-insulating semiconductor substrate 1 and then annealed, and the surface of the n-type GaAs active operating layer 32 is chemically treated with an etchant containing hydrofluoric acid to obtain a Ga component. By comparison, the electron trap layer 4 rich in As component is formed, and the Schottky gate electrode 51 and the ohmic contact electrodes 61 and 62 are formed on the electron trap layer 4, thereby forming a Schottky gate field effect transistor having a high breakdown voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky gate field effect transistor.

[0002]

2. Description of the Related Art The general structure of a conventional Schottky gate field effect transistor is uniform on the surface of a semi-insulating semiconductor substrate 1 such as GaAs by epitaxial growth or ion implantation, as illustrated in the sectional view of FIG. After the n-type operating layer 81 having a thickness is formed, a metal is vapor-deposited on the surface of the operating layer to form the source electrode 61 and the drain electrode 62.
And a Schottky gate electrode 51 is formed. In such a conventional Schottky gate field effect transistor, it is known that if the resistance between the gate and the source is large, the microwave characteristics, particularly the noise characteristics of the transistor are deteriorated. To improve the microwave characteristics, it is necessary to lower the resistance between the gate and the source, and to achieve this purpose, it is necessary to increase the carrier concentration of the operating layer or increase the thickness of the operating layer. ,
Either method further causes a problem that the pinch-off voltage becomes excessive.

In order to solve such a problem, FIG.
As illustrated in FIG. 1, there is proposed a structure in which the thickness of the operating layer 83 near the source electrode is increased while keeping the thickness of the operating layer 82 immediately below the gate that controls the pinch-off voltage at a desired value (Japanese Patent Laid-Open No. Sho. 59-52881). In this structure, first, an operating layer having a uniform thickness corresponding to the thickness directly under the source electrode 61 and the drain electrode 62 is formed, and then only a portion 82 which should be directly under the gate electrode 51 is thinned by recess etching or the like. Each electrode 51, 61 and 62 is formed.

However, in such a structure, since the surface of the operating layer is not flat, it is not only difficult to perform fine photolithography for forming electrodes, but also extremely strict accuracy is required for controlling the etching of the operating layer. Therefore, there is a problem that the yield becomes low.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a Schottky gate field effect transistor which has a high breakdown voltage and is easy to manufacture.

[0006]

According to the Schottky gate field effect transistor of the present invention, the above-mentioned object is to provide a semi-insulating semiconductor substrate, an n-type GaAs operating layer formed on the surface of the semiconductor substrate, and the operation. In a Schottky gate field effect transistor having a source electrode, a Schottky gate electrode, and a drain electrode formed on the layer, the operating layer has a thickness that gives a predetermined pinch-off voltage, and the surface of the GaAs operating layer. Ga of As
This is achieved by having a region with a high abundance ratio to. According to the present invention, further, a step of forming an n-type GaAs operating layer on the surface of the semi-insulating semiconductor substrate, a step of chemically treating the surface with an etchant containing hydrofluoric acid, a source electrode and a drain electrode. And a step of forming a Schottky electrode, a method of manufacturing a Schottky gate electrode transistor is provided.

[0007]

According to the Schottky gate field effect transistor of the present invention, since the abundance ratio of As is higher than that of Ga in the surface region of the n-type GaAs operating layer having a thickness that gives a predetermined pinch-off voltage, Invert from mold to p-type. Therefore, this region serves as a p-type GaAs operating layer and serves as an electron trap. Therefore, when a positive voltage is applied to the drain electrode, the electron trap formed on the surface where current leakage first starts catches electrons and suppresses them, so that the drain breakdown voltage can be improved.

[0008]

The preferred embodiments of the present invention will be described in detail below.

FIG. 1 is a sectional view of a Schottky gate field effect transistor according to an embodiment of the present invention, where 1 is GaA.
Semi-insulating semiconductor substrate such as s (specific resistance ρ> 10 ⁷ Ω · c
m), 32 are n-type GaAs active operating layers, 4 is an electron trap layer, 61 is a source electrode, 62 is a drain electrode, and 51 is a Schottky gate electrode. In the field effect transistor of the present invention, as illustrated in FIG. 1, a region where the As component is rich, that is, a region which becomes the electron trap layer 4 is 5 to 100 Å from the surface on the surface of the n-type GaAs active operation layer 32.
(As is 50 in this region)
It exists in the ratio of% ≦ As / (Ga + As) ≦ 90%. Since this becomes a p-type operation layer, the gate leak current which is the cause of the breakdown voltage deterioration is reduced. Therefore, the drain breakdown voltage is improved.

FIG. 2 is a sectional view showing an example of a method of manufacturing the field effect transistor of FIG. First, as shown in FIG.
As shown in (b), GaAs semi-insulating semiconductor substrate 1
A resist pattern 2 is formed on the surface of the substrate to expose ²⁹ Si ⁺ ions under predetermined conditions (for example, implantation energy of 30 to 50 Ke).
V 5 × 10 ¹² dose / cm ² ) to form an n ⁻ operating layer 3 having a uniform thickness. Next, the pattern 2 formed of the resist is removed by ashing with a plasma asher,
A pattern 21 is formed by another resist, and ²⁹ Si ⁺ ions are implanted under predetermined conditions (for example, implantation energy 90 to 180 KeV, to implant deeper than the previous ion implantation).
2 × 10 ¹³ dose / cm ² ) and n ⁺ operating layer 3
1 is formed. That is, as the condition of the second ion implantation, the implantation energy is larger than that of the first implantation because the implantation is deeper than that of the first implantation, and the implantation amount of the final peak carrier concentration is higher than that of the first peak carrier concentration. This is to prevent it from becoming excessive. This is to prevent dielectric breakdown due to the voltage applied to the gate. Similarly, after the pattern 21 is removed by ashing, about 1000 Å of SiN _x film is formed to activate the n ⁻ operating layer 3 and the n ⁺ operating layer 31.
As shown in (c), annealing is performed at 900 ° C. for 20 minutes in an N ₂ atmosphere to form the n-type GaAs active operation layer 32. This annealing may be performed by furnace annealing, but if the temperature rising rate is slow, thermal diffusion of impurities will occur and impair the rapidity of the impurity concentration distribution.
It is preferably performed by flash annealing with a halogen lamp or an arc amplifier having a high temperature rise rate of 300 ° C./sec. This SiN film is PECVD
Although it is formed by (Plasma Enhanced CVD) method, thermal CVD or sputter deposition method, PECVD method capable of forming a thin film at about 300 ° C. is preferable from the viewpoint of reducing substrate surface damage. This SiN film is removed by an etchant containing phosphoric acid or the like. As a result, the thickness of the obtained n-type GaAs active operating layer 32 is preferably 1000 to 5000Å, and more preferably 1000 to 2000Å.

Then, as shown in FIG. 2D, in order to form a region which is the electron trap layer 4 on the surface of the n-type GaAs active operation layer 32, the concentration of hydrofluoric acid is 5 to 40% by weight. Chemical treatment with an etchant containing. As a result, Ga on the GaAs surface is eluted into the etchant, and As remains on this surface. Further, this chemical treatment is preferably performed for 10 seconds to 10 minutes in an ultrasonic environment from the viewpoint of increasing the treatment speed. The depth of the electron trap layer 4 extends from the surface to 100 Å, more preferably from the surface to 30 Å. Further, the abundance ratio of the remaining As to Ga is preferably 50% ≦ As / (Ga + A
s) 90%.

Next, FIGS. 2 (e), 3 (f), and (g)
As described above, the Schottky gate electrode uses a three-layer structure of Ti / Pt / Au from the viewpoints of low resistance, fine workability, adhesion to a substrate, heat resistance, and low thermal stress between a semiconductor substrate and These thicknesses are respectively formed with 500/500 / 2000Å. The source / drain electrodes, which are ohmic electrodes, are formed by vapor deposition, lift-off, and alloying of AuGe.

FIG. 4 is a sectional view showing another example of a method for manufacturing a field effect transistor. This is shown in Figure 4.
In (a), n is formed on the GaAs semi-insulating semiconductor substrate 1.
Resist, SiO ₂ , Si to form the working layer of the mold
The pattern 7 is formed of an insulating film of N or the like, and the pattern shown in FIG.
In (d), a vapor phase epitaxial growth method (V
PE), metalorganic vapor phase epitaxial growth method, etc.
A layer of As component is formed by growing a As layer on which an activated layer is activated in the same manner as in the above-described method, and by chemically treating the surface of the layer with an etchant containing hydrofluoric acid. A gate electrode and an ohmic electrode are formed.

Experimental Example How much the drain breakdown voltage of the Schottky gate field effect transistor of the present invention depends on the ratio of Ga to As on the GaAs surface, that is, the surface composition (Ga%),
I investigated if it would change. The structure of the Schottky gate field effect transistor used in this experiment was the same as that of the above-mentioned embodiment, and the gate length was 1.0 μm and the gate width was 200 μm. As a measurement condition, V _gd = + 5 on the drain side between the gate and drain electrodes.
By applying V (see FIG. 5), it was investigated how the gate leakage current changes depending on the surface composition (Ga to As ratio: Ga%), and the results are summarized in the following table. The surface composition was changed by chemically treating the surface of the activated operating layer with an etchant containing hydrofluoric acid to elute Ga.

Table Relationship between GaAs surface composition and leak current Sample Hydrofluoric acid Surface composition (Ga%) Gate leak current (A) treatment condition (A) None 42 1.00 × 10 ⁻⁰⁶ (B) Immersion ( 7 min) 25 4.50 × 10 ^-07 (C) Immersion (7 min) +20 1.30 × 10 ^-08 Ultrasonic immersion (1 min) Note GaAs surface composition was subjected to Auger analysis (measurement conditions: electron beam voltage 2. 0 kV, beam current 89 nA).

Further, from this table, the gate leakage current G
The relationship is shown in Table 1 as the dependence on the aAs surface composition.

[0017]

[Table 1]

According to this, in the sample (A) formed by being immersed in the etchant containing hydrofluoric acid for 7 minutes, the surface composition of Ga was 25%, and the gate leakage current at this time was 4.50. Although it was × 10 ^-07 A, in the sample (B), the surface composition of Ga was 20%, so that it was further reduced to 1.30 × 10 ^-08 A, which is smaller than that without chemical treatment by the etchant. It was confirmed to be greatly improved.

[0019]

As described above, according to the Schottky gate field effect transistor of the present invention, the surface region of the n-type GaAs operating layer having a thickness that gives a predetermined pinch-off voltage has an area of As compared with Ga. Since it has a high abundance ratio of n-type, it is inverted from n-type to p-type and becomes a p-type GaAs operating layer,
It becomes an electronic trap. Therefore, when a positive voltage is applied to the drain electrode, the electron trap formed on the surface where current leakage first starts catches electrons and suppresses them, so that the drain breakdown voltage can be improved. As a result, a Schottky gate field effect transistor with high reliability and high yield can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a Schottky gate field effect transistor of the present invention.

FIG. 2 is a sectional view showing in a flow chart an example of a method of manufacturing the Schottky gate field effect transistor of the present invention.

FIG. 3 is a cross-sectional view showing a flowchart of an example of a method of manufacturing the Schottky gate field effect transistor of the present invention.

FIG. 4 is a sectional view showing in a flow chart another example of the method of manufacturing the Schottky gate field effect transistor of the present invention.

FIG. 5 is a diagram showing a configuration cross section and measurement conditions of a Schottky gate field effect transistor of an experimental example.

FIG. 6 is a sectional view of a conventional Schottky gate field effect transistor.

FIG. 7 is a cross-sectional view of a conventional Schottky gate field effect transistor.

[Explanation of symbols]

1 ... Semi-insulating semiconductor substrate, 2, 7, 21, 22, 23 ...
Insulating pattern, 3 ... n ^- operating layer, 32 ... n-type GaAs
Active operating layer, 4 ... Electron trap layer, 5 ... Schottky gate electrode metal, 51 ... Schottky gate electrode, 6 ... Ohmic contact metal, 61 ... Source electrode, 62 ... Drain electrode, 8 ... Epitaxial growth layer

Claims (6)

[Claims] 1. A Schottky gate having a semi-insulating semiconductor substrate, an n-type GaAs operating layer formed on the surface of the semiconductor substrate, and a source electrode, a Schottky gate electrode, and a drain electrode formed on the operating layer. In the field effect transistor, the operating layer has a thickness that gives a predetermined pinch-off voltage, and
A Schottky gate field effect transistor having a region where the surface of the operating layer has a high abundance ratio of As to Ga. 2. The Schottky gate field effect transistor according to claim 1, wherein the region is a layer existing at a depth of 30Å from the surface. 3. An n-type Ga is formed on the surface of a semi-insulating semiconductor substrate.
A method of manufacturing a Schottky gate field effect transistor, comprising: a step of forming an As operating layer; a step of chemically treating the surface with an etchant containing hydrofluoric acid; and a step of forming a source electrode, a drain electrode and a Schottky electrode. 4. The method of manufacturing a Schottky gate field effect transistor according to claim 3, wherein the chemical treatment step includes an ultrasonic treatment step. 5. The method for manufacturing a Schottky gate field effect transistor according to claim 3, wherein the concentration of hydrofluoric acid in the etchant is 10 to 25% by weight. 6. The step of sonicating comprises 20 seconds to 3 seconds.
The method for manufacturing a Schottky gate field effect transistor according to claim 4 or 5, wherein the method is performed for 6 minutes.