JPH0722221A - Production of fixed resistor - Google Patents
Production of fixed resistorInfo
- Publication number
- JPH0722221A JPH0722221A JP5159255A JP15925593A JPH0722221A JP H0722221 A JPH0722221 A JP H0722221A JP 5159255 A JP5159255 A JP 5159255A JP 15925593 A JP15925593 A JP 15925593A JP H0722221 A JPH0722221 A JP H0722221A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resistor
- insulating
- printing
- baking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
(57)【要約】 (修正有)
【目的】 表面の平滑性に優れ、抵抗値の変動を最小限
に抑え、さらに電極の剥離が発生することがない固定抵
抗器の製造方法を提供する。
【構成】 本発明は、表面側の端子電極膜31a、31
bを導電性ペーストの複数回の印刷・焼付けにより形成
する工程と、前記端子電極膜の下層310とのみ接続す
るように抵抗体膜4を抵抗体ペーストの印刷・焼付けに
より形成する工程と、前記抵抗体膜4を覆うように絶縁
膜5を絶縁ペーストの印刷焼付けにより形成する工程
と、を含む固定抵抗器の製造方法である。
(57) [Summary] (Modified) [Objective] To provide a method for manufacturing a fixed resistor which has excellent surface smoothness, minimizes fluctuations in resistance value, and does not cause electrode peeling. According to the present invention, the surface side terminal electrode films 31a, 31
b is formed by printing and baking conductive paste a plurality of times; forming the resistor film 4 by printing and baking the resistor paste so as to connect only to the lower layer 310 of the terminal electrode film; And a step of forming an insulating film 5 so as to cover the resistor film 4 by printing and baking an insulating paste, and a method of manufacturing a fixed resistor.
Description
【0001】[0001]
【産業上の利用分野】本発明は、チップ抵抗、多連抵抗
器などの固定抵抗器の製造方法に関して、特に、抵抗値
の変化が少なく、且つ表面の平滑性が高い固定抵抗器の
製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a fixed resistor such as a chip resistor and a multiple resistor, and more particularly to a method for manufacturing a fixed resistor having a small change in resistance value and a high surface smoothness. It is about.
【0002】[0002]
【従来の技術】従来、固定抵抗器、例えばチップ抵抗器
は、アルミナなどの矩形状の絶縁基板の対向する両端部
に端子電極が配置され、この2つの端子電極の一部に重
畳するようにトリミングされ、且つ抵抗値が調整された
抵抗体膜が配置され、さらに抵抗体膜上に絶縁膜が形成
されていた。2. Description of the Related Art Conventionally, in a fixed resistor, for example, a chip resistor, terminal electrodes are arranged at opposite ends of a rectangular insulating substrate made of alumina or the like, and are arranged so as to overlap a part of these two terminal electrodes. A resistor film, which is trimmed and whose resistance value is adjusted, is arranged, and an insulating film is further formed on the resistor film.
【0003】従来のチップ抵抗器の基板の表面におい
て、主に端子電極部分は端子電極となる導体膜の1層の
みが形成され、抵抗体膜部分は、抵抗体膜及び絶縁膜の
2層が形成されている。さらに構造によっては、絶縁膜
を2層構造とすることがあるが、結局、主に端子電極が
形成された部位と抵抗体膜が形成された部位とでは基板
上での厚みが異なり、全体としての表面平滑性が悪かっ
た。On the surface of the substrate of the conventional chip resistor, mainly one terminal electrode portion is formed with only one layer of the conductor film, and the resistor film portion is formed with two layers of the resistor film and the insulating film. Has been formed. Further, depending on the structure, the insulating film may have a two-layer structure, but after all, the thickness on the substrate is different mainly between the part where the terminal electrode is formed and the part where the resistor film is formed, and as a whole. Had poor surface smoothness.
【0004】このようにチップ抵抗器の表面平滑性が劣
ると、チップ抵抗器をプリント配線基板への自動実装す
るため、その表面を吸引した場合、吸引もれが発生して
実装効率が低下してしまう。If the surface smoothness of the chip resistor is poor as described above, the chip resistor is automatically mounted on the printed wiring board. Therefore, when the surface of the chip resistor is sucked, suction leakage occurs and the mounting efficiency is lowered. Will end up.
【0005】そこで、表面の平滑性を向上させるため、
従来より、端子電極の表面側において、厚みを補正する
ため、ダミー電極膜を形成していた。Therefore, in order to improve the smoothness of the surface,
Conventionally, a dummy electrode film is formed on the surface side of the terminal electrode in order to correct the thickness.
【0006】例えば、図4において、1はチップ抵抗器
であり、2は絶縁基板であり、3a、3bは端子電極で
あり、4は抵抗体膜であり、5は絶縁膜である。For example, in FIG. 4, 1 is a chip resistor, 2 is an insulating substrate, 3a and 3b are terminal electrodes, 4 is a resistor film, and 5 is an insulating film.
【0007】ここで、端子電極3a、3bは絶縁基板の
対向する端部の表面、裏面及び端面につながる厚膜導体
膜30a、30bと、表面側厚膜導体膜上に形成したダ
ミー電極膜35a、35bと、該厚膜導体膜30a、3
0b及びダミー電極膜35a、35bの表面全面を被覆
したメッキ層34a、34bとから構成される。Here, the terminal electrodes 3a and 3b are the thick film conductor films 30a and 30b connected to the front surface, the back surface and the end surface of the opposite ends of the insulating substrate, and the dummy electrode film 35a formed on the front surface side thick film conductor film. , 35b and the thick conductor films 30a, 3b.
0b and the plating layers 34a and 34b covering the entire surfaces of the dummy electrode films 35a and 35b.
【0008】図4に示したチップ抵抗器の製造方法の工
程の概要は、以下のとおりである。The outline of the steps of the method of manufacturing the chip resistor shown in FIG. 4 is as follows.
【0009】(1)素子領域を区分する分割溝が形成さ
れた大型絶縁基板を用意する。 (2)各素子領域に端子電極の一部となる表面側及び裏
面側電極膜を導電性ペーストの印刷・焼付けにより形成
する。(1) A large-sized insulating substrate having a dividing groove for dividing the element region is prepared. (2) The front surface side and back surface side electrode films, which become part of the terminal electrodes, are formed in each element region by printing and baking a conductive paste.
【0010】(3)各素子領域の対向する表面側端子電
極の一部と接続する抵抗体膜を抵抗体ペーストの印刷・
焼成により形成する。(3) Printing a resistor paste on a resistor film which is connected to a part of the surface side terminal electrodes facing each element region.
It is formed by firing.
【0011】(4)各素子領域の抵抗体膜上に第1層目
の絶縁膜を絶縁ペーストの印刷・焼成により形成する。(4) A first insulating film is formed on the resistor film in each element region by printing and baking an insulating paste.
【0012】(5)抵抗体膜の抵抗値を測定しながら、
抵抗体膜の一部をトリミングして抵抗値の調整を行う。(5) While measuring the resistance value of the resistor film,
The resistance value is adjusted by trimming a part of the resistor film.
【0013】(6)各素子領域の抵抗体膜上、即ち第1
層目絶縁膜上に第2層目の絶縁膜を絶縁ペーストの印刷
・焼成により形成する。(6) On the resistor film in each element region, that is, the first
A second insulating film is formed on the second insulating film by printing and baking an insulating paste.
【0014】(7)各素子領域の表面側電極膜上にダミ
ー電極膜を導電性ペーストの印刷焼付けにより形成す
る。(7) A dummy electrode film is formed on the surface-side electrode film of each element region by printing and baking a conductive paste.
【0015】(8)大型基板を各素子領域の端子電極側
の端面が現れるように短冊状に1次分割を行う。(8) The large-sized substrate is first divided into strips so that the end surfaces of the respective element regions on the terminal electrode side appear.
【0016】(9)各素子領域の表面側電極膜と裏面側
電極膜とが接続するように端面電極膜を形成する。(9) The end surface electrode film is formed so that the front surface side electrode film and the back surface side electrode film in each element region are connected.
【0017】(10)短冊状基板を個々の素子領域に2
次分割を行う。(10) Two strip-shaped substrates are provided in each element region.
Next division is performed.
【0018】(11)各素子の表面側電極膜、裏面電極
膜及び端面電極膜の表面にメッキ層を形成する。(11) A plating layer is formed on the surface of the front surface side electrode film, the back surface electrode film and the end surface electrode film of each element.
【0019】[0019]
【発明が解決しようとする課題】上述のように表面の平
滑性を向上させるために、ダミー電極膜を形成したチッ
プ抵抗器において、ダミー電極膜35a、35bは、抵
抗値調整された後に形成される。In order to improve the smoothness of the surface as described above, in the chip resistor in which the dummy electrode film is formed, the dummy electrode films 35a and 35b are formed after the resistance value is adjusted. It
【0020】ここで、ダミー電極膜35a、35bや第
2層目の絶縁膜52は、導電性ペースト又は絶縁ペース
トの印刷・焼成によって形成される。このため、抵抗値
の調整をおこなった抵抗体膜4は、その後に複数回の熱
処理工程が加わるため、その都度、抵抗値の変動が発生
してしまい、結局、トリミング工程において調整した抵
抗値から大きく抵抗値が大きく変動してしまうことがあ
った。Here, the dummy electrode films 35a and 35b and the second-layer insulating film 52 are formed by printing and baking a conductive paste or an insulating paste. Therefore, the resistance film 4 whose resistance value has been adjusted is subjected to a plurality of heat treatment steps thereafter, so that the resistance value varies each time, and eventually the resistance value adjusted in the trimming step is changed. The resistance value may fluctuate greatly.
【0021】また、ダミー電極膜35a、35bは、絶
縁膜5を形成した後に形成されるため、図4に示すよう
にダミー電極膜35a、35bの一部は、絶縁膜5の一
部に被覆してしまう。従って、この接合部分では密着性
が劣化してしまい、電極剥がれなどの問題を含んでい
た。Since the dummy electrode films 35a and 35b are formed after the insulating film 5 is formed, part of the dummy electrode films 35a and 35b cover the insulating film 5 as shown in FIG. Resulting in. Therefore, the adhesiveness is deteriorated at this joint portion, which causes a problem such as electrode peeling.
【0022】本発明は上述の問題点に鑑みて案出された
ものであり、その目的は、表面の平滑性に優れ、抵抗値
の変動を最小限に抑え、さらに、電極の剥離が発生する
ことがない固定抵抗器の製造方法を提供することにあ
る。The present invention has been devised in view of the above-mentioned problems, and an object thereof is to have excellent surface smoothness, to minimize fluctuations in resistance value, and to cause peeling of electrodes. It is to provide a manufacturing method of a fixed resistor which does not exist.
【0023】[0023]
【課題を解決するための手段】本発明によれば、矩形状
基板の対向する表面側端部に、多層構造の一対の端子電
極を、前記一対の端子電極間に抵抗体膜を、前記抵抗体
膜上に絶縁膜を夫々形成して成る固定抵抗器の製造方法
において、前記端子電極を導電性ペーストの複数回の印
刷・焼付けにより形成する工程と、前記端子電極の下層
とのみ接続するように抵抗体膜を抵抗体ペーストの印刷
・焼付けにより形成する工程と、前記抵抗体膜を覆うよ
うに絶縁膜を絶縁ペーストの印刷・焼付けにより形成す
る工程と、を含む固定抵抗器の製造方法である。According to the present invention, a pair of terminal electrodes having a multilayer structure, a resistor film between the pair of terminal electrodes, and the resistor In a method of manufacturing a fixed resistor formed by forming an insulating film on a body film, the step of forming the terminal electrode by printing and baking a conductive paste a plurality of times, and connecting only the lower layer of the terminal electrode. And a step of forming a resistor film by printing / baking a resistor paste, and a step of forming an insulating film by printing / baking an insulating paste so as to cover the resistor film. is there.
【0024】[0024]
【作用】以上のように、従来の表面平滑性を向上させる
ダミー電極膜がポストシンター(後焼成)によって形成
されていたのに対して、本発明では、表面側の電極膜の
形成にあたり、形状の異なる2回の印刷、乾燥及び焼付
け焼成によって達成される。この時、端子電極は2回印
刷による下層と上層とが1回の焼成によって形成される
ため、実質的に一体化し、従来のようにダミー電極膜が
剥離するなどの問題が発生しない。As described above, the conventional dummy electrode film for improving the surface smoothness is formed by post sintering (post-baking), whereas in the present invention, the shape of the electrode film on the surface side is changed. Of two different prints, drying and baking. At this time, since the lower layer and the upper layer of the terminal electrode are formed by one-time firing by printing twice, they are substantially integrated and the problem of peeling the dummy electrode film unlike the conventional case does not occur.
【0025】また、上述のように、表面平滑性を向上さ
せる表面側の電極膜の上層が、抵抗値調整工程前に既に
形成(焼成)されているため、抵抗値調整後の熱処理工
程を減らすことができるので、調整された抵抗値の変動
を最小限に抑えることができる。Further, as described above, since the upper layer of the electrode film on the surface side for improving the surface smoothness is already formed (baked) before the resistance value adjusting step, the heat treatment step after the resistance value adjusting is reduced. Therefore, the fluctuation of the adjusted resistance value can be minimized.
【0026】[0026]
【実施例】以下、本発明の固定抵抗器の製造方法を図面
に基づいて詳説する。図1は、本発明に係る固定抵抗器
の一例であるチップ抵抗器の平面図であり、図2は図1
中のX−X線断面を示す図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a fixed resistor according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a plan view of a chip resistor which is an example of a fixed resistor according to the present invention, and FIG.
It is a figure which shows the XX cross section in the inside.
【0027】チップ抵抗器1は、絶縁基板2、端子電極
3a、3b、抵抗体膜4、絶縁膜5とから構成されてい
る。The chip resistor 1 is composed of an insulating substrate 2, terminal electrodes 3a and 3b, a resistor film 4 and an insulating film 5.
【0028】絶縁基板2はアルミナなどの絶縁性材料か
らなり、その長辺方向の対向する端部には、端子電極3
a、3bが形成されている。The insulating substrate 2 is made of an insulating material such as alumina, and the terminal electrodes 3 are provided at opposite ends in the long side direction.
a and 3b are formed.
【0029】端子電極3a、3bは、表面、裏面及び端
面に形成した各端子電極膜31a〜33a、31b〜3
3bから構成され、さらに、その表面に半田濡れ性を向
上させるメッキ層34a、34bが形成されている。The terminal electrodes 3a and 3b have respective terminal electrode films 31a to 33a and 31b to 3 formed on the front surface, the back surface and the end surface.
3b, and plated layers 34a and 34b for improving solder wettability are formed on the surface thereof.
【0030】さらに、表面側端子電極膜31a、31b
は、下層310と上層311とかなる。下層310は裏
面電極膜32a、32b、端面電極膜33a、33bと
の接続を達成するものであり、上層311は、完成され
たチップ抵抗器1の表面平滑性を達成するためのもので
ある。Further, the surface side terminal electrode films 31a, 31b
Is a lower layer 310 and an upper layer 311. The lower layer 310 is for achieving the connection with the back surface electrode films 32a and 32b and the end surface electrode films 33a and 33b, and the upper layer 311 is for achieving the surface smoothness of the completed chip resistor 1.
【0031】上述各電極膜31a〜33a、31b〜3
3bは絶縁基板2の端部の表面側にAg系導電性ペース
トを2回印刷(1回目の印刷で下層310、2回目の印
刷で上層311を印刷形成する)・乾燥、裏面側及び端
面に夫々Ag系導電性ペーストを用いて、印刷・乾燥し
て焼きつけにより形成され、さらに、Niメッキ層、半
田メッキ層がメッキ処理によって形成されている。The above-mentioned electrode films 31a to 33a and 31b to 3
3b is printed with Ag-based conductive paste twice on the surface side of the end of the insulating substrate 2 (the lower layer 310 is printed by the first printing and the upper layer 311 is printed by the second printing), dried, and on the back side and the end surface. Each is formed by printing, drying, and baking using an Ag-based conductive paste, and a Ni plating layer and a solder plating layer are further formed by plating.
【0032】抵抗体膜4は、端子電極3a、3bの表面
側の端子電極膜31a、31bの主に下層310の一部
に接続するように例えば酸化ルテニウム系の抵抗体ペー
ストを印刷・焼きつけにより被着形成されている。The resistor film 4 is formed by printing and baking, for example, a ruthenium oxide-based resistor paste so as to be connected to mainly the lower layer 310 of the terminal electrode films 31a and 31b on the surface side of the terminal electrodes 3a and 3b. It is adhered and formed.
【0033】絶縁膜5は、1層もしくは2層構造であ
り、例えば2層構造の場合には、前記抵抗体膜4を形成
した後に、直ちに第1層目絶縁膜51を、少なくとも抵
抗体膜4のトリミングされる部分41を含むように抵抗
体膜4全体に被着形成される。The insulating film 5 has a one-layer or two-layer structure. For example, in the case of a two-layer structure, immediately after forming the resistor film 4, the first-layer insulating film 51, at least the resistor film is formed. 4 is deposited and formed on the entire resistor film 4 so as to include the trimmed portion 41.
【0034】さらに、第2層目の絶縁膜52は、抵抗体
膜4を充分に被覆すようにように被着形成される。第1
層目の絶縁膜51は、例えばレーザー光等によるトリミ
ング時における抵抗体膜4への衝撃を軽減するために形
成するものである。また、第2層目の絶縁膜52は、抵
抗体膜4をメッキ液から保護するために形成される。
尚、抵抗体膜4は、この第1層目及び第2層目の絶縁膜
51、52の何れかにまたは両方によって、抵抗体膜4
よりも大い寸法の印刷形成によって被覆されている。Further, the second-layer insulating film 52 is deposited so as to sufficiently cover the resistor film 4. First
The insulating film 51 of the layer is formed to reduce the impact on the resistor film 4 at the time of trimming with laser light or the like. The second insulating film 52 is formed to protect the resistor film 4 from the plating solution.
The resistor film 4 is formed by either or both of the first and second insulating films 51 and 52.
It is covered by a larger size print formation.
【0035】次に図1に示すチップ抵抗器の製造方法を
説明する。Next, a method of manufacturing the chip resistor shown in FIG. 1 will be described.
【0036】(1)素子領域を区分する分割溝が形成さ
れた大型絶縁基板を用意する。 (2)各素子領域に端子電極3a、3bの一部となる表
面側電極膜31a、31bとなる導体膜をAg系導電性
ペーストを用いて印刷・乾燥を行う。具体的には、図3
に示すように、まず下層310を印刷し、さらに所定形
状の上層311を印刷するという2回印刷をおこなう。
尚、上層311の印刷は、完成したチップ抵抗器の表面
平滑性を考慮して、複数回おこなっても構わない。(1) A large-sized insulating substrate having a dividing groove for dividing the element region is prepared. (2) Printing and drying a conductor film, which becomes the surface side electrode films 31a and 31b, which become part of the terminal electrodes 3a and 3b, in each element region, using Ag-based conductive paste. Specifically, FIG.
As shown in (2), first, the lower layer 310 is printed, and then the upper layer 311 having a predetermined shape is printed.
The upper layer 311 may be printed a plurality of times in consideration of the surface smoothness of the completed chip resistor.
【0037】(3)各素子領域に端子電極3a、3bの
一部となる裏面側電極膜32a、32bとなる導体膜を
Ag系導電性ペーストを印刷・乾燥を行う。(3) An Ag-based conductive paste is printed and dried on each element region to form a conductor film to be the back-side electrode films 32a and 32b which will be a part of the terminal electrodes 3a and 3b.
【0038】(4)表面側及び裏面側電極膜31a、3
1b、32a、32bとなる導体膜をを850℃で絶縁
基板に焼きつける。(4) Surface side and back side electrode films 31a, 3
The conductor films 1b, 32a and 32b are baked on an insulating substrate at 850 ° C.
【0039】(5)各素子領域の対向する表面側端子電
極膜31a、31bの主に下層310接続する抵抗体膜
4を形成する。具体的には、酸化ルテニウム系抵抗体ペ
ーストを印刷・乾燥し、850℃で焼成する。(5) Forming the resistor film 4 mainly connected to the lower layer 310 of the surface side terminal electrode films 31a and 31b facing each other in each element region. Specifically, a ruthenium oxide-based resistor paste is printed, dried, and fired at 850 ° C.
【0040】(6)各素子領域の抵抗体膜4上に第1層
目絶縁膜51を形成する。具体的にはホウ珪酸鉛ガラス
を含む絶縁ペーストを印刷・乾燥し、600℃で焼成す
る。(6) The first-layer insulating film 51 is formed on the resistor film 4 in each element region. Specifically, an insulating paste containing lead borosilicate glass is printed, dried, and fired at 600 ° C.
【0041】(7)抵抗体膜4の抵抗値を測定しなが
ら、抵抗体膜4の一部をトリミングして抵抗値の調整を
行う。具体的には、表面側電極膜31a、31bに測定
器のプローブを当てながら、例えばYAGレーザーを抵
抗体膜4に、横切る方向に照射して、抵抗体膜4及び第
1層目の絶縁膜51の一部を消失させる。(7) While measuring the resistance value of the resistor film 4, a part of the resistor film 4 is trimmed to adjust the resistance value. Specifically, while applying a probe of a measuring device to the front-side electrode films 31a and 31b, for example, a YAG laser is applied to the resistor film 4 in a transverse direction so that the resistor film 4 and the first-layer insulating film are irradiated. A part of 51 is erased.
【0042】(8)各素子領域の抵抗値が調整された抵
抗体膜4上、即ち第1層目絶縁膜51上に第2層目の絶
縁膜52を形成する。具体的にはホウ珪酸鉛ガラスを含
む絶縁ペーストを印刷・乾燥し、600℃で焼成する。(8) A second insulating film 52 is formed on the resistor film 4 whose resistance value is adjusted in each element region, that is, on the first insulating film 51. Specifically, an insulating paste containing lead borosilicate glass is printed, dried, and fired at 600 ° C.
【0043】(9)大型基板を各素子領域の端子電極3
a、3b側の端面が現れるように短冊状に1次分割を行
う。(9) A large substrate is used as a terminal electrode 3 for each element region.
Primary division is performed in a strip shape so that the end faces on the a and 3b sides appear.
【0044】(10)各素子領域の表面側電極膜31
a、31bと裏面側電極膜32a、32bとが接続する
ように端面側電極膜33a、33bを形成する。具体的
には、Ag系導電性ペーストを印刷・乾燥し、600℃
で焼きつける。(10) Surface side electrode film 31 in each element region
The end surface side electrode films 33a and 33b are formed so that the a and 31b are connected to the back surface side electrode films 32a and 32b. Specifically, Ag-based conductive paste is printed and dried at 600 ° C.
Bake in.
【0045】(11)短冊状基板を個々の素子領域に2
次分割を行う。(11) Two strip-shaped substrates are provided in each element area.
Next division is performed.
【0046】(12)各素子の表面側電極膜31a、3
1b、裏面電極膜32a、32b及び端面電極膜33
a、33bの表面にメッキ層34a、34bを形成す
る。(12) Surface side electrode films 31a, 3 of each element
1b, back surface electrode films 32a and 32b, and end surface electrode film 33
Plating layers 34a and 34b are formed on the surfaces of a and 33b.
【0047】以上のように、本発明において、表面側電
極膜31a、31bが下層310と表面平滑性を向上さ
せるための上層311とから構成されているので、完成
したチップ抵抗器1において、抵抗体膜4が形成された
部位と端子電極3a、3bが形成された部位の表面に段
差が発生することを抑えることができ、吸引による実装
信頼性が大きく向上する。As described above, in the present invention, since the surface side electrode films 31a and 31b are composed of the lower layer 310 and the upper layer 311 for improving the surface smoothness, the resistance of the completed chip resistor 1 is improved. It is possible to suppress the occurrence of a step between the surface where the body film 4 is formed and the surface where the terminal electrodes 3a and 3b are formed, and the mounting reliability due to suction is greatly improved.
【0048】また、上層311が下層310と同一工程
で焼きつけされるので、実質的に上層311と下層31
0とが一体化され、上層311が下層310に安定して
接合でき、上層311と下層310との間での剥離が一
切起こることがない。Since the upper layer 311 and the lower layer 310 are baked in the same step, the upper layer 311 and the lower layer 31 are substantially formed.
0 is integrated, the upper layer 311 can be stably bonded to the lower layer 310, and peeling between the upper layer 311 and the lower layer 310 does not occur at all.
【0049】さらに、抵抗体膜4の抵抗値を調整した後
は、絶縁膜、実施例では第2層目の絶縁層52の焼成工
程による熱処理のみとなるため、抵抗値が調整された抵
抗体膜4の抵抗値変動を極小化することができる。Further, after the resistance value of the resistor film 4 is adjusted, only the heat treatment in the firing step of the insulating film, that is, the second insulating layer 52 in the embodiment, is performed. It is possible to minimize the variation in the resistance value of the film 4.
【0050】本発明者は、表面の平坦化による自動実装
機による実装試験、抵抗値調整後の抵抗値の変動による
歩留、さらに温度サイクル後のダミー電極膜35a、3
5b又は上層311の接合強度を本発明品と図4に示す
従来品とで比較を行った。The inventor of the present invention has found that the mounting test by an automatic mounting machine by flattening the surface, the yield due to the variation of the resistance value after the resistance value adjustment, and the dummy electrode films 35a, 3 after the temperature cycle are performed.
5b or the bonding strength of the upper layer 311 was compared between the product of the present invention and the conventional product shown in FIG.
【0051】自動実装機による実装試験における実装ミ
スは、本発明品においては0.01%であり、従来品に
おいては0.03%であった。また、抵抗値歩留は、本
発明品においては98%であり、従来品においては96
%であった。さらに表面側電極膜31a、31bの温度
サイクル後の接着強度は、本発明品においては1.5K
g(最小0.8Kg)であり、従来品においては1.0
Kg(最小0.5Kg)であった。The mounting error in the mounting test by the automatic mounting machine was 0.01% in the present invention product and 0.03% in the conventional product. The resistance yield is 98% in the product of the present invention and 96 in the conventional product.
%Met. Further, the adhesive strength of the surface side electrode films 31a and 31b after the temperature cycle is 1.5 K in the product of the present invention.
g (minimum 0.8 Kg), 1.0 for conventional products
It was Kg (minimum 0.5 Kg).
【0052】即ち、表面の平坦化に起因する実装効率、
抵抗値の変動及び接着強度のいずれにおいても、本発明
は非常に良好な結果となった。That is, the mounting efficiency due to the flattening of the surface,
The present invention gave very good results in both the variation of the resistance value and the adhesive strength.
【0053】以上の説明は、チップ抵抗器についてであ
るが、例えば多連抵抗器の場合には、1素子あたり、複
数の抵抗体膜およびその抵抗体膜に対応した端子電極を
形成するように端子電極のパターンおよび抵抗体膜のパ
ターンを制御すればよい。The above description is of a chip resistor. For example, in the case of a multiple resistor, a plurality of resistor films and terminal electrodes corresponding to the resistor films are formed per element. The pattern of the terminal electrode and the pattern of the resistor film may be controlled.
【0054】[0054]
【発明の効果】以上のように、本発明によれば、表面の
平滑性に優れ、抵抗値の変動を最小限に抑え、さらに電
極の剥離が発生することがない固定抵抗器の製造方法と
なる。As described above, according to the present invention, there is provided a method for manufacturing a fixed resistor which has excellent surface smoothness, minimizes fluctuations in resistance value, and prevents peeling of electrodes. Become.
【0055】[0055]
【図1】本発明に係る固定抵抗器の一例であるチップ抵
抗器の平面図である。FIG. 1 is a plan view of a chip resistor which is an example of a fixed resistor according to the present invention.
【図2】図1中のX−X線断面を示す縦断面図である。FIG. 2 is a vertical sectional view showing a section taken along line XX in FIG.
【図3】本発明のチップ抵抗器の製造主要工程を説明す
る縦断面図である。FIG. 3 is a vertical cross-sectional view explaining the main steps of manufacturing the chip resistor of the present invention.
【図4】従来のチップ抵抗器の縦断面図である。FIG. 4 is a vertical sectional view of a conventional chip resistor.
1 ・・・・チップ抵抗器 2 ・・・・絶縁基板 20・・・・大型絶縁基板 21・・分割溝 3a、3b・・・端子電極 31a、31b・・・表面側端子電極膜 310・・・・・・・下層 311・・・・・・・上層 32a、32b・・・裏面側端子電極膜 33a、33b・・・端面側端子電極膜 35a、35b・・・ダミー電極膜 4・・・・・・・抵抗体膜 5・・・・・絶縁膜 51・・・・第1層目の絶縁膜 52・・・・第2層目の絶縁膜 1 ... Chip resistor 2 ... Insulating substrate 20 ... Large insulating substrate 21 ... Dividing groove 3a, 3b ... Terminal electrode 31a, 31b ... Surface side terminal electrode film 310 ... ...... Lower layer 311 ・ ・ ・ ・ Upper layer 32a, 32b ・ ・ ・ Back surface side terminal electrode film 33a, 33b ・ ・ ・ End surface side terminal electrode film 35a, 35b ・ ・ ・ Dummy electrode film 4 ... .... Resistor film 5 ... Insulating film 51 ... First insulating film 52 ... Second insulating film
Claims (1)
層構造の一対の端子電極を、前記一対の端子電極間に抵
抗体膜を、前記抵抗体膜上に絶縁膜を夫々形成して成る
固定抵抗器の製造方法において、 前記端子電極を導電性ペーストの複数回の印刷・焼付け
により形成する工程と、 前記端子電極の下層とのみ接続するように抵抗体膜を抵
抗体ペーストの印刷・焼付けにより形成する工程と、 前記抵抗体膜を覆うように絶縁膜を絶縁ペーストの印刷
・焼付けにより形成する工程と、を含むことを特徴とす
る固定抵抗器の製造方法。1. A pair of multi-layered terminal electrodes, a resistor film is formed between the pair of terminal electrodes, and an insulating film is formed on the resistor film, respectively, at opposite end portions of the rectangular substrate on the surface side. A method of manufacturing a fixed resistor comprising: a step of forming the terminal electrode by printing / baking a conductive paste a plurality of times; and a step of printing the resistor paste so that the resistor film is connected only to a lower layer of the terminal electrode. A method of manufacturing a fixed resistor, comprising: a step of forming by baking, and a step of forming an insulating film by printing and baking an insulating paste so as to cover the resistor film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5159255A JPH0722221A (en) | 1993-06-29 | 1993-06-29 | Production of fixed resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5159255A JPH0722221A (en) | 1993-06-29 | 1993-06-29 | Production of fixed resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0722221A true JPH0722221A (en) | 1995-01-24 |
Family
ID=15689763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5159255A Pending JPH0722221A (en) | 1993-06-29 | 1993-06-29 | Production of fixed resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0722221A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008187193A (en) * | 2008-03-21 | 2008-08-14 | Kyocera Corp | Wiring board |
-
1993
- 1993-06-29 JP JP5159255A patent/JPH0722221A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008187193A (en) * | 2008-03-21 | 2008-08-14 | Kyocera Corp | Wiring board |
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