JPH07225672A - Barrel shifter and control method - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a barrel shifter and a control method thereof that can effectively use the same resource without adding large-scale hardware or increasing the calculation time. [Structure] Five-stage selecting means 1-4, 105 for selecting shift side data or non-shift side data with respect to input data
If the shift side data is not selected by any of the selection means 1 to 4, 105 of the five stages,
The mask signal 17 of the input mask pattern 13 is output, and when the shift-side data is selected by at least one of the five-stage selecting means 1 to 4, 105, the fifth selecting means 105 is selected. Shift permission signal 16
The control unit 15 outputs a mask signal 17 for selecting shift-side data or non-shift-side data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a barrel shifter capable of flexibly performing digit alignment of data required for high-speed signal processing and the like, and a control method thereof.

[0002]

2. Description of the Related Art Due to the complexity of signal processing algorithms in recent years, high-speed signal processing systems are required. Conventionally, a barrel shifter as shown in FIG. 4 has been devised in order to flexibly perform digit alignment of data handled in such signal processing, and many digital signal processors applying this have been devised.

An example of the above-mentioned conventional barrel shifter will be described below with reference to the drawings.

FIG. 4 is a block diagram of the barrel shifter. As shown in FIG. 4, the barrel shifter has input data 1
1st selecting means 1 for shifting left 1 bit to 1 and left 2 to the output data of the first selecting means
The second selecting means 2 for performing the bit shift, hereafter, similarly, the third selecting means 3 for performing the left 4 bit shift, the fourth selecting means 4 for performing the left 8 bit shift, and the right 16 bits. It is composed of fifth selecting means 5 for performing the shift.

Each selection means has a first selection signal 6 for controlling the selection of the first selection means 1, a second selection signal 7 for controlling the selection of the second selection means 2, and a third selection means. Third selection signal 8 for performing selection control of No. 3 and fourth selection means 4
The fourth selection signal 9 for controlling the selection and the fifth selection signal 10 for controlling the selection of the fifth selecting means 5 are input. The input data 11 is input to the first selecting means 1 and then shifted according to each selection signal, and as a result, the output data 12 is output from the fifth selecting means 5.

FIG. 5 is a block diagram showing the internal structure of the first to fifth selecting means 1 to 5 of the barrel shifter shown in FIG. That is, each of the selection means 1 to 5 has an inverter gate 100 that generates an inverted signal of the selection signal.
And a multiplexer 101 for selecting a signal, and a signal (non-shift side data) 102 of a bit k (k: 0 to 15) and a bit k-i (i: 1, 2, 4, 8,
-16) signal (shift side data) 103,
Select according to the selection signal.

Next, the operation of the conventional barrel shifter configured as described above will be described. (Case 1) First, the fifth selection signal 10 to the first in FIG.
The operation in the case where the selection signal 6 of (1) is right 1 bit shift of x "1f" will be described.

Input data 11 is 16-bit data and is first
The values of the selection signal 6 to the fifth selection signal 10 are all "1"
At this time, all the shift operations from the first selecting means 1 to the fifth selecting means 5 are selected.

At this time, the first selection means 1 uses the input data 1
Bit k-1 for each bit k of 1 (k: 0 to 15)
, The result is a 1-bit left shift.

Next, the second selecting means 2 selects the value of the bit k-2 for each bit k of the input data, and as a result, the left 2 bit shift is executed.

Next, the third selecting means 3 selects the value of bit k-4 for each bit k of the input data, and as a result, the left 4-bit shift is executed.

Next, the fourth selecting means 4 selects the value of the bit k-8 for each bit k of the input data, and as a result, the left 8-bit shift is executed.

Next, the fifth selecting means 5 selects the value of bit k + 16 for each bit k of the input data, and as a result, the right 16-bit shift is executed.

As described above, all the selecting means 1 to 5 perform the shift operation so that the right one bit shift is finally executed. (Case 2) Next, the operation in the case of right 16-bit shift will be described.

The fifth input data 11 is 16-bit data
The value of the first selection signal 6 from the selection signal 10 of x is “10”
At this time, the non-shift operation is selected for all of the first selecting means 1 to the fourth selecting means 4, and only the fifth selecting means 5 selects the shift operation.

At this time, the first selection means 1 uses the input data 1
The value of the bit k is selected for each bit k of 1 (k: 0 to 15), and as a result, the shift processing is not executed.

Next, the second selecting means 2 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the third selecting means 3 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the fourth selecting means 4 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the fifth selecting means 5 selects the value of bit k + 16 for each bit k of the input data, and as a result, the right 16-bit shift is executed.

As described above, the first to fourth selecting means 1 to 4
No shift processing is performed up to the selecting means 4 of the above, and only the fifth selecting means 5 performs the shift operation, so that the right 16
Bit shift is executed. (Case 3) Next, the operation in the case of left 1-bit shift will be described.

The fifth input data 11 is 16-bit data.
The value of the first selection signal 6 from the selection signal 10 of x is “01”
At this time, the second selecting means 2 to the fifth selecting means 5 all select the non-shift operation, and only the first selecting means 1 selects the shift operation.

At this time, the first selection means 1 uses the input data 1
Bit k-1 for each bit k of 1 (k: 0 to 15)
, The result is a 1-bit left shift.

Next, the second selecting means 2 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the third selecting means 3 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the fourth selecting means 4 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the fifth selecting means 5 selects the value of the bit k for each bit k of the input data, and as a result, the shift process is not executed.

As described above, only the first selecting means 1 performs the shift processing, and the second selecting means 2 to the fifth selecting means 5 do not perform the shift processing, so that the left 1 is finally obtained.
Bit shift is executed. (Case 4) Finally, the operation when the shift process is not executed will be described.

First input data 11 is 16-bit data
The values of the selection signal 6 to the fifth selection signal 10 are all "0"
At this time, all the non-shift operations from the first selecting means 1 to the fifth selecting means 5 are selected.

At this time, the first selecting means 1 selects the value of the bit k for each bit k (k: 0 to 15) of the input data, and as a result, the shift processing is not executed.

Next, the second selecting means 2 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the third selecting means 3 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the fourth selecting means 4 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the fifth selecting means 5 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

As described above, the first selection means 1 to the fifth
Since all of the selection means 5 do not perform the shift process, the shift process is not finally executed, and the input data 11 is directly output as the output data 12.

[0036]

However, in the conventional configuration as described above, the barrel shifter is a mere data path and does not make sense as an arithmetic unit in an arithmetic operation that does not require shift processing. It had a problem that it was bad.

In consideration of such problems of the conventional barrel shifter, the present invention makes it possible to effectively utilize the same resource without causing addition of large-scale hardware and increase in calculation time, and the barrel shifter and its control. It is intended to provide a method.

[0038]

The present invention has N stages of selection means for selecting shift-side data or non-shift-side data for input data in accordance with a selection signal, and right 2 ^N-1 bits. , Left 2 ^N-1 -1 bit shiftable barrel shifter outputs the input mask signal when the shift-side data is not selected by any of the N-stage selecting means. When the shift side data is selected by at least one of the stage selecting means, a mask signal for selecting the shift side data or the non-shift side data is output according to the selection signal for the final stage selecting means. It is a barrel shifter equipped with a control unit for controlling.

[0039]

According to the present invention, the control unit is one of N-stage selection means.
If the shift-side data is not selected by any of the selecting means, the input mask signal is output, and if the shift-side data is selected by at least one of the N-stage selecting means, the final stage is selected. The shift-side data or the non-shift-side data is selected according to the selection signal for the selection means.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments.

FIG. 1 is a block diagram of a barrel shifter according to an embodiment of the present invention. In FIG. 1, the first to fourth selecting means 1 to 4 have the same configuration as that of the conventional example described in FIG. 4, and perform the same operation.

The difference from the conventional barrel shifter is the fifth one.
The configuration of the selection means 105 and the control unit 15 are added. The control unit 15 receives the mask pattern 13 at the time of mask processing, the shift execution signal 14 requesting the shift execution, and the fifth selection signal 10, and inputs the fifth selection signal 10, the mask pattern 13, and the shift execution signal. 14
Based on the shift enable signal 16 and the mask signal 1 described later.
7 and 7 are output to the fifth selecting means 105 (FIG. 2 is a diagram showing a relationship between an input signal and an output signal in the control section 15). That is, the shift permission signal 16 is valid when the shift is executed, and the mask signal 17 is valid when the non-shift processing is executed.

FIG. 3 is an internal block diagram of the fifth selecting means 105 in the barrel shifter of this embodiment. The difference between the fifth selecting means 105 and the other selecting means (see FIG. 5) is that
The point is that the mask signal 17 is input instead of the inverted selection signal inverted by the inverter gate.

Next, the operation of the barrel shifter of the above embodiment will be described with reference to FIG. (Case 11 in FIG. 2) First, in FIG. 2, the operation in the case where the fifth selection signal 10 to the first selection signal 6 are x "1f" and the shift execution signal 14 is "1" for right 1-bit shift Will be explained.

First input data 11 is 16-bit data
When all the values of the selection signals 6 to 9 are "1", the shift operation is selected from the first selection unit 1 to the fourth selection unit 4.

At this time, the first selecting means 1 selects the value of the bit k-1 for each bit k (k: 0 to 15) of the input data, and as a result, the left one bit shift is executed.

Next, the second selecting means 2 selects the value of the bit k-2 for each bit k of the input data, and as a result, the left 2 bit shift is executed.

Next, the third selecting means 3 selects the value of the bit k-4 for each bit k of the input data, and as a result, the left 4-bit shift is executed.

Next, the fourth selecting means 4 selects the value of bit k-8 for each bit k of the input data, and as a result, the left 8-bit shift is executed.

Next, the fifth selecting means 105 includes the control unit 15
Since the shift enable signal 16 output from is "1" and the mask signal 17 is x "0000", the non-shift side data (the signal 102 side in FIG. 3) is invalid, and each bit k of the input data is On the other hand, the value of bit k + 16 (shift side data, signal 103 side in FIG. 3) is selected, and as a result, right 16
Bit shift is executed.

Therefore, the right one bit shift is finally executed. (Case 12 in FIG. 2) Next, in the case of the right 16-bit shift in which the fifth selection signal 10 to the first selection signal 6 are x "10" and the shift execution signal 14 is "1" in FIG. The operation will be described.

The input data 11 is 16-bit data and is the first
When all the values of the selection signals 6 to 9 are "0", all the non-shift operations from the first selection unit 1 to the fourth selection unit 4 are selected.

At this time, the first selecting means 1 selects the value of the bit k for each bit k (k: 0 to 15) of the input data, and as a result, the shift process is not executed.

Next, the second selecting means 2 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the third selecting means 3 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the fourth selecting means 4 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the fifth selecting means 105 includes the control unit 15
Since the shift permission signal 16 output from is 1 and the mask signal 17 is X “0000”,
Similarly, for each bit k of input data, bit k +
A value of 16 is selected and, as a result, right 16-bit shift processing is executed.

Therefore, the right 16-bit shift is finally executed. (Case 13 in FIG. 2) Next, in FIG. 2, in the case of the 1st left shift of the fifth selection signal 10 to the first selection signal 6 is x "01" and the shift execution signal 14 is "1". The operation will be described.

If the input data 11 is 16-bit data and the second
All the values of the selection signal 7 to the fifth selection signal 10 are “0”
At this time, all the non-shift operations from the second selecting means 2 to the fifth selecting means 105 are selected.

At this time, the first selecting means 1 selects the value of the bit k-1 for each bit k (k: 0 to 15) of the input data, and as a result, the left one bit shift is executed.

Next, the second selecting means 2 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the third selecting means 3 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the fourth selecting means 4 selects the value of the bit k for each bit k of the input data, and as a result, the shift processing is not executed.

Next, the fifth selecting means 105 controls the control unit 15
Since the shift enable signal 16 output from is "0" and the mask signal 17 is X "ffff", the value of the bit k for each bit k of the input data (on the signal 102 side in FIG. 3)
Is selected, and as a result, the shift process is not executed.

Therefore, the left one bit shift is finally executed. (Case 14 in FIG. 2) Next, in FIG. 2, all the bits from the fourth selection signal 9 to the first selection signal 6 x "0" and the shift execution signal 14 "0" are enabled. The operation in the case of mask processing will be described.

First input data 11 is 16-bit data
When all the values of the selection signals 6 to 9 are "0", all the non-shift operations from the first selection unit 1 to the fourth selection unit 4 are selected.

At this time, each bit k (k: 0 to 15) of the input data is input from the first selecting means 1 to the fourth selecting means 4.
, The value of bit k is selected, and as a result, the shift processing is not executed.

Next, the fifth selecting means 105 controls the control unit 15
Since the shift permission signal 16 output from is "0" and the mask signal 17 is X "ffff", mask processing is performed on each bit of the input data, and all the data becomes valid. Therefore, finally, the input data 11 is directly output as the output data 12. (Case 15 in FIG. 2) Next, in FIG. 2, 4 bits of 4th selection signal 9 to 1st selection signal 6 are x "0" and shift execution signal 14 is "0" The operation in the case of the mask processing that is enabled only will be described.

The first input data 11 is 16-bit data.
When all the values of the selection signals 6 to 9 are "0", the non-shift operation is selected from the first selection means 1 to the fourth selection means 4 as in the case 14 described above. .

At this time, each bit k (k: 0 to 15) of the input data is input from the first selecting means 1 to the fourth selecting means 4.
, The value of bit k is selected, and as a result, the shift processing is not executed.

Next, the fifth selecting means 105 includes the control unit 15
Since the shift enable signal 16 output from is "0" and the mask signal 17 is X "00f0", mask processing is performed on bits 4 to 7 of the input data. Therefore, finally, 0 is output to bits 0 to 3 and bits 8 to 15, and the data of bits 4 to 7 of the input data 11 is output as the output data 12 as it is. This means that the data of bits 4 to 7 can be cut out.

As described above, according to the present embodiment, when the shift execution signal input to the final stage selecting means of the N stage selecting means constituting the barrel shifter is not valid, the non-shift side is selected. Conventionally, by providing a control unit that outputs a mask signal for performing mask processing on input data, and outputs a shift permission signal for selecting input data on the shift side when the input shift execution signal is valid, In addition to the shift processing of the above, when the non-shift processing is executed, the mask signal of the specific bit is masked or cut out by the same hardware at the final stage of the barrel shifter by the same hardware, and the resource is used even when the non-shift processing is executed The efficiency can be increased.

Although the multiplexer is used as the selection means in the above embodiment, the present invention is not limited to this, and another circuit, device or the like having the same function may be used.

Further, in the above embodiment, the control section and the selection means at the final stage are independently provided, but the present invention is not limited to this and may be an integrated configuration.

Further, in the above embodiment, the coefficient N = 5 and the selection means of five stages are used, but the present invention is not limited to this, and any other value may be used.

[0076]

As is apparent from the above description, the present invention outputs the input mask signal when the shift side data is not selected by any of the N-stage selecting means. When shift-side data is selected by at least one of the N-stage selecting means, a mask signal for selecting shift-side data or non-shift-side data is selected in accordance with the selection signal for the final-stage selecting means. Since the output control unit is provided, there is an advantage that the same resource can be effectively used without causing large-scale addition of hardware and increase in calculation time.

[Brief description of drawings]

FIG. 1 is a block diagram of a barrel shifter according to an embodiment of the present invention.

FIG. 2 is a diagram explaining an operation of a control unit in the embodiment.

FIG. 3 is an internal block diagram of a fifth selecting means in the embodiment.

FIG. 4 is a block diagram of a conventional barrel shifter.

FIG. 5 is an internal configuration diagram of a selection unit in a conventional barrel shifter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st selection means 2 2nd selection means 3 3rd selection means 4 4th selection means 5 5th selection means 15 Control part 16 Shift permission signal 17 Mask signal 100 Inverter gate 101 Multiplexer 102 Bit k signal 103-bit k-i signal 105 Fifth selection means

Claims (2)

[Claims] 1. An N-stage selection means for selecting shift-side data or non-shift-side data for input data according to a selection signal, and has right 2 ^N-1 bits and left 2 ^N-1 -1. In the barrel shifter capable of shifting bits, when the shift-side data is not selected by any of the N-stage selecting means, the input mask signal is output to select one of the N-stage selecting means. In the case where the shift side data is selected by at least one selecting means, a control section for outputting a mask signal for selecting the shift side data or the non-shift side data is provided according to the selection signal to the final stage selecting means. Barrel shifter characterized by that. 2. Right 2 ^N-1 bits and left 2 ^N-1 -1 bits are selected by N stages of selection means for selecting shift side data or non-shift side data for input data according to a selection signal. In the shiftable barrel shifter control method, when the shift-side data is not selected by any of the N-stage selecting means, the input mask signal is output to select one of the N-stage selecting means. , At least 1
When the shift side data is selected by one of the selecting means, a mask signal for selecting the shift side data or the non-shift side data is output according to the selection signal to the selecting means at the final stage. .