JPS6017534A - Floating-point numeral normalized circuit - Google Patents

Abstract

PURPOSE:To perform shifting to a mantissa by plural times and shorten processing time which is needed for normalization by consisting a titled circuit combined a circuit which determines the shift number of the mantissa, a shifter for shifting the mantissa and a circuit which subtracts an index. CONSTITUTION:The titled circuit is constituted by combinating the shift-number determination circuit which determines the shift number of the mantissa, the shifter for shifting the mantissa and the operation circuit for subtracting the index. For example, the shift number SH of the mantissa by inputting values from the most significant bit to 4-bit A1-A4 of the mantissa register 1 is outputted. Next, the shifter 6 is shifted to the left by only the SH value by inputting the shift number SH to the shift controller 9, and the contents of the mantissa register 1 is shifted to the left by the SH value by inputting the contents of the mantissa register 1 to the shifter 6. The contents of the index of the index register 2 is subtracted by only the SH value by inputting the shift number SH to the X side of the operation circuit 10 and inputting the contents of the index register 2 to the Y side, and normalize the floating-point numeral.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention reduces processing time by shifting the mantissa by multiple bits in a circuit that normalizes a floating point number whose mantissa is represented by 2's complement in four tables and whose base is 2. Regarding floating-point numerical normalization circuits aimed at
1".

Now, the mantissa is expressed as a two's complement number, and in order to normalize a floating point number with a base of 2, it is sufficient that the value of the most significant bit of the mantissa differs from the value of the next bit. Figure 1 shows an example of a conventional floating-point value normalization circuit. In Figure 9, (1) is a mantissa register that has a shift function and holds the value of the mantissa;
2) is an exponent register that holds the exponent value (a 31-digit exclusive OR gate).

S is its output signal, and 14) is an 11 circuit that subtracts the value of the index by 1. Since the conventional floating point number regular circuit is configured as above, the most significant bit of the mantissa register O) and the next bit are exclusively ORed (3)
If the output signal S is 0'' and Ir,
Since the values of the second bit are the same, the contents of the mantissa register (1) are shifted to the left by one bit, and at the same time the contents of the exponent register (1) are shifted to the left by one bit.
The contents of 2) are reduced by 1 by the -1 circuit (4). This circuit performs normalization by repeatedly performing this operation until the output signal (s) becomes "1".

In the conventional circuit described above, the shift 1- of the d mantissa is always ζ
Since this can only be done one bit at a time, the drawback is that the normalization process generally takes a long time.

In order to improve the drawbacks of conventional circuits, this invention combines a shift number determining circuit for determining the number of shifts applied to the mantissa, a shifter for shifting the mantissa, and an arithmetic circuit for exponential subtraction. It is an object of the present invention to provide a floating-point value normalization circuit which can shift a mantissa by a plurality of bits by configuring the same, thereby shortening the processing time required for normalization.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, (11 and f21 are registers that are the same as the conventional one and hold the mantissa and exponent values, respectively. (5) is the value from the most significant bit of the mantissa register (1) to the following 4 bits. A shift number determination circuit capable of obtaining the shift number SH to be applied to the mantissa part as an output by inputting A1 to A4.

(6) is a 1-bit shift (7) that can shift the contents of the mantissa register (1) by 1 bit; and a 2-bit shift (71) that can shift the contents of the mantissa register (11) by 2 bits;
8), which can shift up to 3 bits (9) is the output S of the number determining circuit (5)
A shifter controller controls the shifter (6) so that the contents of the mantissa register (1) are shifted to the left by the value of R. On is a shifter controller that controls the shifter (6) so that the contents of the mantissa register (1) are shifted left by the value of R. It is an arithmetic circuit.

The operation of the floating point value normalization circuit according to the present invention, which is configured as follows:

The mantissa of the floating point value is held in the mantissa register (1) and the exponent is held in the exponent register (2).7, The value A1 to A4 from the most significant bit of the mantissa register (1) to the following 4 bits is determined by the number of shifts. Input to circuit (5) ζ
Thus, the binding shift number SH is output as the mantissa. Here, the output SR for inputs A1 to A4 is as shown in the table.
.

The truth table or SH of the table shift number determining circuit is represented by a 2-bit binary number. By inputting SH to the shift control (9), the shifter (
6) is controlled to shift to the left by the value of EIH. By inputting the contents of the mantissa register (1) to the shifter (6), the contents of the mantissa register +1+ are shifted to the left by the value of SH. At the same time, SH is connected to arithmetic circuit a.
Input to Y side of 1, contents of exponent register Exercise 2 circuit +1
(Exponent register (2) by inputting to the Y side of I
The contents of are reduced by the value of SR.

Normalization is performed in this way, but SH= 11 (
In case 2), there is a possibility that normalization has not been completed, so it is necessary to repeat the operation described above.

As described above, according to the floating point value normalization circuit of the present invention, the mantissa can be shifted by a plurality of bits during normalization, so that the processing time during normalization can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional floating-point value normalization circuit, and FIG. 2 is a diagram showing the configuration of an embodiment of the floating-point value normalization circuit of the present invention. (1) is a mantissa register;
(2) is an exponent register, (3) is an exclusive OR
The gate f51 is a shift number determining circuit. (6) is a shifter, (711dl bit shifter, (8) is a 2-bit shifter, (9) is a shifter controller, to
n is an arithmetic circuit. Note that the same reference numerals are given to the same or corresponding parts in the figures.

Claims (1)

[Scope of Claims] A circuit for normalizing a floating point number whose mantissa is expressed as a two's complement number and has a base of 2, comprising: a mantissa register that holds the value of the mantissa; an exponent register that holds the exponent; and the mantissa. Input the value at a certain pin 14 below the most significant bit of the register. a shift number determination circuit that determines the mantissa 6 and the number of shifts;
A shifter that shifts the mantissa of the mantissa register based on the output of the shift number determining circuit, and an arithmetic circuit that subtracts the contents of the exponent register from the output of the shift number determining circuit. A floating-point numerical normalization circuit featuring: