JPH0722932A - on. Delay circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Fail-safe on, which does not generate delayed output when the oscillator fails. Provide a delay circuit. [Configuration] The oscillator 3 is configured to include either PUT or UJT, operates with an input voltage Vin as a power supply, and produces an output pulse. The AND circuit 5 outputs an output pulse when the power supply voltage is supplied to the power supply terminal, the gate voltage of the PUT or the base voltage of UJT is input to one input terminal A, and the output pulse is input to the other input terminal B. The output voltage Vo is generated at the same time as memorizing, and the output voltage Vo disappears when a circuit failure occurs. The gate voltage of PUT or the base voltage of UJT supplied to one input terminal A is set higher than the voltage of the power supply terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is an on-switch used for fail-safe information processing in the field of railway signals, for example. Regarding the delay circuit, PUT or U
A fail-safe oscillator configured by any of JTs and a fail-safe AND circuit that stores the output pulse of the oscillator input to the other input terminal when one input terminal has an input voltage are combined, By turning on the gate voltage of PUT or the base voltage of UJT forming the oscillator to one input terminal of the AND circuit, the circuit is turned on due to a circuit failure on the oscillator side. Delay. This is to prevent the time from being shortened and to improve fail-safety.

[0002]

2. Description of the Related Art This type of on. The basics of the delay circuit are
This has already been disclosed in Japanese Patent Application Laid-Open No. 57-157623 (Japanese Patent Application No. 56-42075) proposed by the applicant of the present invention. FIG. 4 shows the on. A delay circuit, 1 is a power input terminal, 2 is a constant voltage circuit, 3 is an oscillator, 4 is an amplifier,
Reference numeral 5 is an AND circuit.

The constant voltage circuit 2 is composed of a transistor Q1, a Zener diode Zd serving as a reference voltage source, and a resistor R1, and has an input voltage V1 supplied to a power supply input terminal 1.
The input voltage Vs (Vs <Vin), which is a power source, is supplied to the oscillator 3 and the AND circuit 4 by stabilizing in.

The oscillator 3 is constructed by using PUT (programmable unijunction transistor) or UJT (unijunction transistor).
Here, an example using a PUT is shown, in which a resistor R2 and a capacitor C1 are connected in series between the hot side power supply line (a) and the cold side power supply line (b) led from the output end of the constant voltage circuit 2. The circuit is connected and the anode A of the PUT is connected to the connection point between the resistor R2 and the capacitor C1. Also,
Resistors R4 and R5 between the power line (a) and the power line (b)
Connected in series, and connect PUT to the connection point of resistors R4 and R5.
The gate G of is connected. The cathode K of the PUT is connected to the power line (b) through the resistor R3.

The amplifier 4 comprises resistors R6 and R7 and a transistor Q2, amplifies the oscillation output of the oscillator 3 generated at both ends of the resistor R3, and then supplies it to the AND circuit 5 through the capacitor C2.

The AND circuit 5 operates using the input voltage Vs stabilized by the constant voltage circuit 2 as a power source, and
When the output pulse of the oscillator 3 is supplied to the input terminal B through the amplifier 4 while the input voltage Vin is supplied to the input terminal A of the two provided input terminals A and B, this output At the same time that the pulse is stored, the DC voltage Vo is output. Due to this storage operation, a feedback circuit including a diode D2 is added from the output side of the AND circuit 5 to the input terminal B. Input voltage Vin to input terminal A
Then, when the output pulse of the oscillator 3 is input to the input terminal B, the feedback circuit performs a self-holding operation, and the output pulse of the oscillator 3 is stored. A clamp diode D1 is connected between the input terminal B and the power supply line (a) to clamp the output pulse input to the input terminal B to the input voltage Vs.

The AND circuit 5 is constructed as a fail-safe circuit in which two inputs oscillate when a predetermined value is input to generate an output, and the output voltage disappears due to a circuit failure. Such an AND circuit is disclosed in, for example, Japanese Patent Publication No.
No. 5, Japanese Patent Publication No. 48-3077, etc.
It is configured by combining a logical product operation oscillator and a rectifier circuit.
OSC1 in FIG. 4 is an AND operation oscillator, and RC1 and RC2 are rectifier circuits.

On of the above. In the delay circuit, FIG.
As shown in (a), when the input voltage Vin is supplied to the power supply input terminal 1 at t0, the input voltage Vs stabilized by the constant voltage circuit 2 is applied to the oscillator 3 and the AND circuit 5, and these are Start operation.

As shown in FIG. 5 (b), the oscillator 3 is turned on depending on the time constant of the resistor R2 and the capacitor C1 from the time t0 when the input voltage Vs is applied. Delay. An output pulse P1 is generated at t1 which is delayed by time Td1. The output pulse P1 is input to the input terminal B of the AND circuit 5 through the amplifier 4, but at this point the input voltage Vin has already been supplied to the input terminal A of the AND circuit 5, so that The input condition is satisfied, and the delay output Vo is generated in the AND circuit 5. Since a part of the delayed output Vo is input to the input terminal B through the feedback circuit formed of the diode D2, the self-holding operation is applied to store the output pulse, and the delayed output Vo is continuously obtained.

[0010]

On the other hand, on. In the delay circuit, the delay output Vo becomes zero at the time of circuit failure and is turned on. Delay. The side where the time Td1 is extended is the fail-safe side.

However, when the input voltage Vin is input to the input terminal A of the AND circuit 5, the resistance R of the oscillator 3 is increased.
When 4 is disconnected, the electric charge accumulated in the capacitor C1 of the oscillator 3 is discharged from the anode A of the PUT through the cathode K, and the output pulse Per is applied across the resistor R3.
(See FIG. 5B) will occur. For this reason, the input conditions are satisfied at the input terminals A and B of the AND circuit 5, and the normal ON. Delay. On, shorter than time Td1. Delay. At time Td2, the delayed output Vo is generated, and there is a problem that the fail-safe property is impaired.

Therefore, an object of the present invention is to provide a fail-safe on-state which does not produce a delayed output when the oscillator fails.
It is to provide a delay circuit.

[0013]

In order to solve the above-mentioned problems, the on. The delay circuit has an oscillator,
AND circuit, the oscillator is a PUT or UJ
It is configured to include any of T, the AND circuit has a power supply terminal and two input terminals, and the gate voltage of the PUT or the base voltage of UJT is input to one of the input terminals, When the output pulse of the oscillator is input to the other input terminal, the output pulse is stored and at the same time an output voltage is generated, and when a circuit failure occurs, the output voltage disappears and is supplied to the one input terminal. Said PUT
Gate voltage or UJT base voltage is set higher than the voltage of the power supply terminal.

[0014]

The oscillator is configured to include either PUT or UJT, and the AND circuit receives the gate voltage of PUT or the base voltage of UJT at one of its input terminals. , At the same time that the input voltage is applied to the oscillator, the gate voltage of the PUT or U that responds to the input voltage is applied to one input terminal of the AND circuit.
The base voltage of JT is input.

On the other hand, the oscillator starts its operation when an input voltage is applied, and generates an output pulse with a delay of a time depending on its own oscillation cycle. This output pulse is input to the other input terminal of the AND circuit. As a result, the input condition in the AND circuit is adjusted to produce a delayed output, and the self-holding operation is performed to store the output pulse. Even if the output pulse disappears, the delayed output is continuously obtained.

In the AND circuit, since the gate voltage of PUT or the base voltage of UJT supplied to one input terminal is set higher than the voltage of the power supply terminal, a fail-safe window. A comparator can be configured.

Next, with the input voltage applied, P
When the resistance that gives the UT gate voltage or the UJT base voltage is disconnected, there is no input to one input terminal of the AND circuit. Therefore, even if an output pulse is generated in the oscillator due to disconnection, the delay output of the AND circuit is kept at zero and turned on. Delay. It becomes a failure mode on the side where the time is extended and becomes a fail safe.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. It is an electric circuit diagram of a delay circuit. In the figure, the same reference numerals as those in FIG. 4 denote the same components. In this embodiment, one end of the resistor R2 forming the oscillator 3 and the gate G of the PUT are connected.
Is connected to one end of a resistor R4 connected to the power input terminal 1, and the connection point between the resistor R4 and the resistor R5 connected to the gate G of the PUT is connected to the AND circuit via the diode D3. 5 is connected to the input terminal A. That is,
The resistors R4 and R5 form a resistor voltage dividing circuit for the input voltage Vin, and the divided voltage is the gate voltage. Resistance R4
And the value of the resistor R5 are set so that the input voltage of the input terminal A is higher than the voltage applied to the power supply terminal. The voltage of the power supply terminal may be given in response to the input voltage Vin,
It may be always applied from another power source different from the input voltage Vin. As shown in the figure, when applied in response to the input voltage Vin, a delayed output is obtained only when the input voltage Vin is applied, and the fail-safe property can be enhanced. When always supplied from another power source, the input of the input voltage Vin can be constantly monitored.

A capacitor C3 is connected between the input terminal A and the ground. The capacitor C3 is provided for the purpose of preventing the potential of the input terminal A from decreasing due to the decrease of the gate voltage because the gate voltage of the PUT decreases momentarily when the PUT oscillates. The diode D3 is provided to prevent the electric charge of the capacitor C3 from discharging through the resistor R5.

Turning on the above embodiment. The delay circuit operates in the same manner as described with reference to FIGS. 4 and 5 when the circuit is normal. That is, as described with reference to FIGS. 5A to 5C, when the input voltage Vin is supplied to the power input terminal 1 at t0, the oscillator 3 starts operating by using the input voltage Vin as a power source, and the AND circuit. 5 starts operation by using the input voltage Vs obtained by stabilizing the input voltage Vin as a power source, and the input voltage Vin
The output pulse P1 is generated at time t1 which is delayed by time Td1 depending on the time constant of the resistor R2 and the capacitor C1 from the time t0 when the voltage is applied. The output pulse P1 is input to the input terminal B of the AND circuit 5 through the amplifier 4.

At time t1 when the output pulse P1 is supplied to the input terminal B, since the divided voltage of the input voltage Vin is already supplied to the input terminal A through the resistor R4 and the diode D3, the input condition in the AND circuit 5 is Then, a delay output is generated in the AND circuit 5. Since a part of the delayed output is input to the input terminal B through the feedback circuit, the self-holding operation is performed and the output pulse is stored and the delayed output Vo is obtained.

Next, after the input voltage Vin is applied and before the output pulse P1 of the oscillator 3 is generated, if the resistor R4 for giving the gate voltage of the PUT or the base voltage of the UJT is disconnected, the input of the AND circuit 5 There is no input to terminal A. Therefore, even if an output pulse is generated in the oscillator 3 due to the disconnection of the resistor R4, the delay output Vo of the AND circuit 5 is kept at zero and turned on. Delay. It becomes a failure mode on the side where the time Td1 is extended, and becomes a fail safe.

The AND circuit 5 is constructed as a fail-safe circuit in which the output voltage disappears due to a circuit failure.
An example of such an AND circuit 5 is the Japanese Patent Publication No.
The windows disclosed in Japanese Utility Model Laid-Open No. 57-4764, in addition to those known in Japanese Patent Publication No. 29045, Japanese Patent Publication No. 48-3077, and the like.
A comparator and an AND circuit proposed as Japanese Patent Application No. 59-81572 can be used. The window disclosed in Japanese Utility Model Laid-Open No. 57-4764 is a window having a window characteristic for at least one of inputs. It is a comparator, and also Japanese Patent Application No. 59-8157.
The AND circuit proposed as No. 2 has a 2-input window. comparator. It is configured as an AND gate.

FIG. 2 is a window disclosed in Japanese Utility Model Laid-Open No. 57-4764. In the electric circuit diagram of the comparator, the input voltages Va and Vb applied to the input terminals A and B are represented by {R13 / (R8 + R12 + R13)} Vb> Vs. ． ． (1) Vf = {R11 / (R10 + R11)} Va <Vs (2) (Vs <Va) Within a range that can be satisfied, the transistors Q4, Q5; off → transistor Q3; on →
Transistor Q3; on-> transistors Q4, Q5; on-> transistor Q3; off oscillation occurs. As a result,
An oscillation output oscillating between the input voltage Va applied to the input terminal A and substantially zero volt is obtained at the output terminal V01.

That is, this window. The comparator is
The input voltages Va and Vb applied to the input terminals A and B are
The oscillation output is generated only when the equations (1) and (2) are satisfied, and the input voltage Vb drops below the range that satisfies the equation (1), or the input voltage Va is (2). When the voltage rises above the range satisfying the formula or when the power source voltage is Vs or less, the circuit oscillation is stopped, and the lower and upper limits are generated in the input voltages Vb and Va that can continue the oscillation operation.

This window. To configure the AND circuit 5 using the comparator, the gate of the PUT that constitutes the oscillator 3 is connected to the input terminal A via the diode D3.
The gate voltage is used as an input in the window and the output pulse of the oscillator 3 is applied to the input terminal B by connecting to the input terminal B. In addition, rectifier circuits RC1 and RC2 are connected to the output terminal V01.
And a feedback circuit with a diode D2 from the rectifier circuit RC2 to the input terminal B.

Next, the fail-safe property will be described. (1) The AND circuit 5 is a circuit whose output disappears when a circuit failure occurs, and is turned on in response to the circuit failure. Delay. This is the direction in which the time Td1 extends and is fail-safe. (2) Disconnection of resistor R1 Since the power supply to the AND circuit 5 is cut off, the AND circuit 5
The output of is zero, which is fail safe. (3) Failure of transistor Q1 Collector. Since there is no power input to the AND circuit 5 when there is an open-circuit failure between the emitters, it is fail-safe. At the time of a short circuit failure, the voltage of the input terminal A becomes lower than the power supply voltage Vs, so that the output of the AND circuit 5 is zero, which is fail-safe. (4) Failure of Zener diode Zd At the time of open circuit failure, it becomes the same as at the time of short circuit failure of the transistor Q1 and it is fail safe. In the case of a short-circuit failure, the power supply voltage of the AND circuit 5 becomes zero, which is fail safe. (5) Disconnection of resistors R2 to R5 The PUT cannot oscillate, which is fail safe. If the resistor R4 is disconnected when there is an input, it is fail safe as described above. (6) Failure of capacitor C1 PUT cannot oscillate in both cases of opening and short-circuiting, which is fail-safe. (7) Disconnection of resistors R6 and R7 Since the output pulse of the oscillator 3 does not enter the input terminal B of the AND circuit 5, it is a fail safe. (8) Transistor Q2 collector. In both cases of open and short between emitters,
Since the output pulse of the oscillator 3 does not enter the input terminal B of the AND circuit 5, it is fail-safe. When the transistor Q2 is short-circuited while the input voltage Vin is being applied, the input terminal B becomes a negative input. No signal is generated when the transistor Q2 is opened. (9) Failure of PUT Anode. It is fail-safe because it cannot oscillate when the cathode is open. anode. At the time of short circuit between the cathodes, the anode. Since the gates are also short-circuited, there is no oscillation output. (10) Failure of capacitor C2 When the capacitor C2 is opened, there is no input to the AND circuit 5. When short-circuited, the output of the transistor Q2 is short-circuited by the diode D1, so that no pulse is input to the input terminal B. (11) Failure of diode D1 Since the clamp action is lost when the diode D1 is open, the input voltage to the input terminal B cannot be higher than the power supply voltage Vs. Therefore, the AND circuit 5 cannot oscillate, which is fail safe. At the time of short circuit, the input of input terminal B becomes zero,
The AND circuit 5 cannot oscillate. (12) Failure of diode D2 When open, no feedback is provided, so self-holding is not possible and delayed output cannot be obtained. At the time of short circuit, the input pulse is
Since it is absorbed by the smoothing capacitor of C2, the AND circuit 5
Cannot oscillate. (13) Failure of the diode D3 When the diode D3 is opened, the input to the input terminal A of the AND circuit 5 becomes zero, so that the AND circuit 5 cannot oscillate. PU in case of short circuit
At the same time when the output pulse of T enters the AND circuit 5, PUT
Due to the decrease in the gate voltage during oscillation, the input to the input terminal A of the AND circuit 5 becomes negative, and the AND circuit 5 cannot oscillate. (14) Failure of capacitor C3 The output pulse of the PUT is input to the input terminal B, and at the same time, the negative pulse from the gate G of the PUT is also input to the input terminal A, and the AND circuit 5 cannot oscillate. Becomes When a short circuit occurs, the input to the input terminal A of the AND circuit 5 becomes zero, so that the AND circuit 5 cannot oscillate.

FIG. 3 shows ON. It is an electric circuit diagram in another example of a delay circuit. In this embodiment, the oscillator 3 is composed of UJT, and the voltage of the base B1 of the bases B1 and B2 of the UJT is input to the input terminal A. Also in this example,
ON by similar circuit action. The delayed output of the delay can be obtained and the same fail-safe property can be secured.

[0029]

As described above, according to the present invention, a fail-safe oscillator composed of either PUT or UJT and one input terminal having an input voltage is input to the other input terminal. In combination with a fail-safe AND circuit that stores the output pulse of the oscillator, the gate voltage of PUT or the base voltage of UJT that configures the oscillator is applied to one input terminal of the AND circuit, and the voltage of one input terminal is By setting it higher than the voltage applied to the power supply terminal, the circuit including the oscillator turns on due to circuit failure. Delay. ON with a high degree of fail-safety that does not shorten the time. A delay circuit can be provided.

[Brief description of drawings]

FIG. 1 shows an ON. It is an electric circuit diagram of a delay circuit.

FIG. 2 shows an ON. A window suitable for constructing a logical product circuit of delay circuits. It is an electric circuit diagram of a comparator.

FIG. 3 shows an ON. It is an electric circuit diagram in another example of a delay circuit.

FIG. 4 shows a conventional ON. It is an electric circuit diagram of a delay circuit.

FIG. 5: Conventional ON. 6 is a time chart for explaining the operation of the delay circuit.

[Explanation of symbols]

3 oscillator 5 AND circuit PUT programmable. Unijunction. Transistor UJT Unijunction. Transistor Vin Input voltage R1 to R7 Resistance C1 to C3 Capacitor D1 to D3 Diode Q1 and Q2 Transistor

Claims (4)

[Claims] 1. An on-device including an oscillator and an AND circuit. A delay circuit, wherein the oscillator is configured to include either PUT or UJT, and the AND circuit has a power supply terminal and two input terminals, and one of the input terminals is the PUT. Gate voltage or U
When the base voltage of JT is input and the output pulse of the oscillator is input to the other input terminal, the output pulse is stored and at the same time the output voltage is generated, and the output voltage disappears when a circuit failure occurs. , The gate voltage of the PUT or the base voltage of UJT supplied to the one input terminal is set higher than the voltage of the power supply terminal.
Delay circuit. 2. The oscillator operates by using an input voltage as a power supply to generate the output pulse, and the AND circuit is configured such that a power supply voltage is supplied to the power supply terminal and the power supply voltage is the same as the input voltage. The on-state according to claim 1, wherein is supplied from a different power supply of a different system. Delay circuit. 3. The logical product circuit has a window characteristic in at least one of two inputs, and a gate voltage or a base voltage of the oscillator is used as an input in a window of the logical product circuit, and the output pulse is the logical product. The on-state according to claim 1 or 2, which is used as the other input of the circuit. Delay circuit. 4. The oscillator includes a resistance voltage dividing circuit, a diode, and a capacitor, the resistance voltage dividing circuit divides the input voltage, and the divided voltage is the gate voltage of the PUT or the UJT. As a base voltage, the anode of the diode is connected to the gate of the PUT or the base of UJT, the cathode of the diode is connected to the one input terminal, and the capacitor is connected between the cathode of the diode and ground. The on-state according to claim 1, 2 or 3, Delay circuit.