JPH07244580A - Version control device - Google Patents

Abstract

PURPOSE:To easily execute the version control of all processing blocks without requiring expertise. CONSTITUTION:When a system power supply is turned on, a version information reading part 8 reads out the version information of controllers 5-1 to 5-N, units 6-1 to 6-N, etc., constituting the system and sends the read contents to a memory 3. These version information data are stored in a version information storing part 7 included in the memory 3. Then the version managing device starts the normal operation of the system and the storing part 7 is protected so as to invalidate an access to the memory 3 at the normal operation of the system. When the version information is required to be known, the contents of the storing part 7 are outputted by using a specific version reading instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a version management device for confirming the version of each processing block composed of various programs and hardware constituting an information processing system and managing the version.

[0002]

2. Description of the Related Art An information processing apparatus comprises a processor unit, a memory, a controller, and various other processing blocks. In addition, these processing blocks
Each will be individually improved and upgraded. For system maintenance and program debugging,
It is necessary to know the version of each processing block in such a system. That is, conventionally, when the system administrator is requested to perform maintenance inspection or debugging work, the place where the version information is stored for each processing block is investigated, and this is read and used by a certain input / output instruction or the like. Was.

[0003]

By the way, the above conventional apparatus has the following problems to be solved.
The version information of each processing block constituting the system is essential information for debugging and maintenance work in order to confirm the performance and usage of the processing block. However, the work of confirming the version of the target processing block differs for each processing block, requires a lot of specialized knowledge, and there is a problem that only a skilled operator can confirm this promptly.

[0004]

The version management device of the present invention adopts the following configuration in order to solve the above problems. This device is provided with a version information reading unit for reading the version information of each processing block that configures the system when the system is powered on. In addition, a version information storage unit that stores and holds the version information of each block read by the version information reading unit in a predetermined area before the normal operation of the system is started.

[0005]

When the power of the system is turned on, the version information reading unit reads the version information of the controller, unit, etc. that form the system and sends it to the memory. The version information storage section in the memory stores these version information. The device then begins normal operation of the system. If the user wants to know the version information, the contents of the version information storage unit are output using a version read command. Therefore, version management of all the processing blocks can be easily performed without specialized knowledge.

[0006]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. [Embodiment 1] FIG. 1 is a block diagram showing an embodiment of the apparatus of the present invention. The device shown in the figure has a bus line 1, a processor 2, a memory 3, and a ROM 4 for system initialization.
And the controllers 5-1 to 5-N are connected. The controller 5-N has a bus line 1-
Units 6-1 to 6-N are connected through 1.

For example, the controller 5-N is an input / output control device, and the units 6-1 to 6-N are printers, displays, and other various input / output devices.
A version information reading unit 8, a memory control unit 9, and a version information output control unit 10 are connected to the memory 3. In the above block diagram, the bus line 1 is for transferring data and address signals, and the processor 2 controls the operation of each part of the device through the bus line 1.

The memory 3 also stores various data and parameters necessary for the processor 2 to operate. This memory 3 is a random access memory (R
AM) and the like. In addition, RO for system initialization
The M4 stores a program that starts up when the power of the device is turned on, automatically checks the states of various parts of the system, initializes the system, and prepares for normal operation of the system. . This device is, for example,
It consists of only memory.

In the version management device of the present invention, the version information reading section 8 is provided in the form of a program inside the ROM 4 for system initialization. As will be described later with reference to FIG. 2, the version information reading unit 8 controls to read the version information of each processing block constituting the system when the system is powered on. The processing block includes the controller 5-1 shown in the figure.
.About.5-N, units 6-1 to 6-N, and other various modules connected to the system. The system initialization ROM 4 is also a memory that stores a certain version of the initialization program, and is included in the processing block to be read by the version information reading unit 8.

In the memory 3, a version information storage unit 7 is set in a certain area inside the memory 3. The version information storage unit 7 stores the version information of each block read by the version information reading unit 8. A memory control unit 9 and a version information output control unit 10 are provided to control the reading of the version information stored in the version information storage unit 7. Arrows 11-1, 11-2, 11-shown in the figure
3 shows the flow of version information sent to the version information storage unit 7 when the system is powered on.

FIG. 2 shows a specific operation flowchart of the apparatus of the present invention as described above. First, in step S1, the system is powered on. Next, in step S2, the system initialization ROM 4 shown in FIG.
Is started. At this time, the operation by the version information reading unit 8 is started together with the series of initialization processes. That is, in step S3, the version information reading unit 8 writes the data in the system initialization ROM 4 and the controllers 5-1 to 5-N or the units 6-1 to 6-N according to a predetermined procedure described as a program in advance. Read version information.

For example, the version information of the controllers 5-1 to 5-N is read by a read command of a fixed I / O address. In addition, the units 6-1 to 6-N
Version information is read by activating the controller 5-N and outputting a constant command from the controller 5-N to each of the units 6-1 to 6-N,
It is read out toward the memory 3 via the controller 5-N.

As described above, the location where the version information is stored differs depending on the type of element, unit, or device. The version information reading unit 8 is prepared in advance with information regarding such a version information reading method for each processing block and a storage address. The version information is read from a unique storage location for each processing block, and arrow 11- It is sent to the version information storage unit 7 like 1 to 11-3. Thus, in step S4, the version information of all the processing blocks is stored in the version information storage unit 7 in a predetermined order. This version information is composed of, for example, an element number for identifying an element and a version number.

By executing the above processing when the power of the system is turned on, when version information is required for maintenance inspection or debugging after that, the operator uses the version read command or the like to store the memory 3 information. The version information storage unit 7 therein can be accessed to easily obtain the requested version information.

[Embodiment 2] In the device of this embodiment, in order to avoid the memory access operation during normal operation from becoming complicated by storing the above version information in the memory 3, the following operation is performed. I am taking measures. That is, in step S5, the version information storage unit 7 is masked. This control is performed by the memory control unit 9 shown in FIG.

After that, from step S6 to step S
The operation of 9 enables the output of version information.
That is, if a certain command is input during normal operation of the device,
In step S6, it is determined whether this is a version read command. If it is not a version read command, the process proceeds to step S7 and other processing is advanced.

In the case of the version read command, the process proceeds to step S8, and the mask release executed in step S5 is performed. Then, in step S9, the version information storage unit 7 of the memory 3 is made accessible,
Version information is output. This output is performed using, for example, a printer, a display, or other various output means. It should be noted that such output means is not shown in FIG. When the output of such version information is completed, the process moves to step S5 again, and masking of the version information storage unit is executed.

FIG. 3 is a block diagram of a memory control unit for executing the masking of the version information storage unit as described above. The embodiment shown in FIG. 3 is a circuit having the functions of the memory control unit 9 and the version information output control unit 10 shown in FIG. Of course, these blocks may be configured separately.

The memory controller 9 of FIG. 3 is provided with a decoder 17 which is connected to the address bus 15 for accessing the memory 3 and accepts it. Further, the decoder 17 is configured to receive an ALE (address latch enable) signal for access control. Two flip-flops 21 and 2 are provided on the output side of the decoder 17.
2 are arranged. The output of the flip-flop 21 is sent to the NAND gate 23. The output of the flip-flop 22 is the NAND gate 23 and the AND gate 2.
Sent to 4. The output of the NAND gate 23 is AND
It is sent to the gate 25. The output of the AND gate 24 is sent to the OR gate 26, and the output of the AND gate 25 is sent to the OR gate 27.

A WE (write enable) signal for the memory 3 is input from the outside of this circuit and is input to the remaining terminals of the OR gate 26. In addition, the A signal 32 for operation control that becomes effective only during the initialization processing
Is input to the other terminals of the AND gate 24 and the AND gate 25. Further, the OE (output enable) signal 33 for the memory 3 is input to the other terminal of the OR gate 27. The outputs of the OR gate 26 and the OR gate 27 are output as the actual write enable signal WE or read enable signal OE of the memory 3 shown in FIG. 1, respectively.

In the above circuit, the decoder 17 decodes the address signal input from the address bus 15, and sets 1-bit data to be input to the D terminals of the flip-flops 12 and 22, and sets and resets the flip-flops 21 and 22. 1 to be input to the C terminal for controlling
It is configured to output a bit control signal. The flip-flops 21 and 22 are composed of D-type flip-flops and the like.

The above memory control section 9 operates as follows. First, when the system shown in FIG. 1 is powered on and the system initialization ROM 4 is executing a normal initialization process, the A signal 32 is valid (low level). As a result, the AND gates 24 and 25 are both closed, and signals input from the direction of the decoder 17 are blocked by the AND gates 24 and 25. Therefore, during the initialization process, the WE signal 31 and the OE signal 33, which are input at a predetermined timing, are directly input to the memory 3 shown in FIG. 1 through the OR gates 26 and 27. As a result, writing and reading of predetermined data is performed on the memory 3.

The reading of version information from each block by the version information reading unit 8 and the writing of the version information into the version information storage unit 7 of the memory 3 are executed during this initialization processing. That is, the version information is written in the memory 3 when the A signal 32 shown in FIG. 3 is at a low level. When the initialization process of the system is completed, the A signal 32 shown in FIG. 3 switches to the high level. As a result, the AND gates 24 and 25 are opened.

When an address for accessing the version information storage unit 7 of the memory 3 is input to the address bus 15, the decoder 17 carries out a masking control so as to prohibit the reading during normal operation. . That is, when an address for accessing the version information storage unit 7 is input from the address bus 15 to the decoder 17 and the ALE signal 16 (address latch enable signal) becomes valid, the decoder 17 outputs its output signals 17-1 to 17-. 4 are “0”, “0”, “0”, “0” to “0”,
Change to "0", "1", "1". The flip-flop 21 stores a signal of "0" at this timing, and the flip-flop 22 stores a signal of "1".

After the next clock, the flip-flop 22 outputs a signal having the content "1", and when it is sent to the AND gate 24 and the NAND gate 23, NA is output.
The output of the ND gate 23 becomes "1". This signal is AN
Since the D gate 25 is open, this AND gate 2
5 and further passes through the OR gate 27 and is sent to the memory 3. The output enable signal OE of the memory 3 is invalidated when it is at a high level, that is, "1". Therefore, the address signal for accessing the version information storage unit 7 of the memory 3 for reading is always invalidated during the normal operation.

On the other hand, when the output of the flip-flop 22 becomes "1", the output of the AND gate 24 becomes "1", which is inputted to the memory 3 as the write enable signal WE through the OR gate 26. Since this signal is also invalid at the high level “1”, the version information storage unit 7
Write access to is also disabled.

Next, in step S6 of FIG. 2, when a certain version read command is executed, a special prepared version information different from the address of the version information storage unit 7 is read from the decoder 17 in advance. Configure to enter the access permission address of.
This address is set in an area having a value different from that of a general memory access address. When such an address is input, the decoder 17 outputs its output 17-1 to 17-4.
Switch all contents to "1". As a result, the signal having the content “1” is stored in the flip-flop 21. The signal is input to the NAND gate 23 at the next clock. A signal having the content “1” is input from the flip-flop 22 to the other terminal of the NAND gate 23. Therefore, the output signal of the NAND gate 23 becomes "0", and the output of the AND gate 25 also switches to the low level "0".

This signal is input to the memory 3 through the OR gate 27. Therefore, the output enable signal of the memory 3 becomes valid, and the version information can be read from the memory 3. At this time, AND gate 24 and O
Since the output of the R gate 26 does not change, the write enable signal WE of the memory 3 remains invalid. Therefore,
Rewriting of version information is prohibited and protected. In addition, as described above, the access permission address is given to the decoder 17
Then, when the address of the version information storage section 7 of the memory 3 is output to the address bus 15 at the next timing, the version information can be read by the flip-flops 21 and 22 for just one clock.

FIG. 4 shows a timing chart showing the operation of such a device of the present invention. In the figure, (a) shows whether the power is on or off, and (b) shows the timing when the initialization process is executed. (C) shows whether the A signal is invalid or valid, and (d) shows whether the output enable signal of the memory 3 is invalid or valid. Further, (e) shows the timing when the access-permitted address is generated,
(F) shows the timing at which an address for reading the version information storage unit is generated.

When the power is turned on at time t1, time t2
The initialization process is executed up to. Only during this period, as described above, the A signal is valid and the version information is stored. When the initialization process ends at time t2 and the A signal becomes invalid, the output enable signal becomes invalid, and even if an access to the version information storage unit address occurs at time t3, the read operation is invalid. Becomes

Next, when an access-permitted address is generated at time t4, the output of the flip-flop 21 shown in FIG. 3 becomes "1" and the output enable signal becomes valid from time t5 to time t6 at the next timing. . When the version information storage unit address is output at this timing, the version information 1 is output from time t5 to time t6.
It can be read once.

As described above, if the version information reading unit reads the version information of each processing block when the system is powered on and stores it in the version information storage unit 7 on the memory 3, the operator is particularly complicated. It is possible to easily read the version information of each block from the memory 3 and use it without performing the read operation of the version information.

After the system initialization processing is completed as in the second embodiment, the version information is stored in the version information storage unit 7.
If the version information storage unit 7 is stored in the memory, and the version information storage unit 7 is separated from other storage areas of the system and masked, the existence of the version information storage unit 7 is recognized in the subsequent work such as memory mapping by software. You don't have to. Further, it is possible to prevent the version information from being destroyed carelessly.

Since the specially masked version information needs to be read during system maintenance and debugging, a special version read command is prepared to generate an access-permitted address. Then, the reading can be performed, and then the mask processing as described above can be executed again.

FIGS. 5 and 6 show comparative examples for comparing the apparatus of the present invention with the method of the conventional apparatus. FIG. 5 is a comparative example showing the conventional unit version confirmation method.
FIG. 6 shows a comparative example showing the same controller version confirmation method. That is, according to the conventional method, first, as shown in FIG. 5, the apparatus is powered on in step S1 and the system initialization ROM is started in step S2. Then, in step S3, the system initialization ROM is started. Various initial processes in are executed. Then, in step S4, the operator checks the version confirmation method of the unit, etc., and then in step S5, issues an I / O command, sends a command to read the version of the unit from the controller controlling the unit, and executes the reading. .

Further, in FIG. 6, as in the case of the process of FIG. 5, when the processes of steps S1 to S3 are executed, the address of the version management register of the controller is checked in step S4. And step S
5, the version control register address is I / O
Read by instruction.

In both cases of FIG. 5 and FIG. 6 described above, in step S5 and step S6, the operator must perform an operation requiring a certain amount of specialized knowledge. In the present invention, such a complicated operation is executed by the version information reading unit, and thereafter, the version information is immediately read by a certain version read command.

[Embodiment 3] FIG. 7 shows another operational flowchart of the apparatus of the present invention. The apparatus of the present invention preferably operates to store version information in the memory when the system is powered on as described above. However, depending on the system, the RO for initializing the system
Rewriting M may not be easy. Further, it is not always necessary to always provide the version information storage unit on the memory, and it may be sufficient to store the version information at an appropriate timing. In addition, it may be desirable to store version information at a timing different from the system initialization processing. In such a case, the third embodiment is executed.

That is, as shown in FIG. 7, first, step S
Before 1, normal operation is activated. And step S1
At, it is determined whether the command input during the operation is a version control command, and if it is another command, the process proceeds to step S2 and another process is executed. Then, if it is confirmed that it is a version management command, the version information of each processing block is read in step S3. This process itself is the same as that described in the first embodiment. Then, in step S4, the version information storage unit 7 is set in the memory 3 and the version information is stored. Thereafter, the version information storage unit 7 is subjected to the same mask processing as that of the first embodiment, if necessary.

The present invention is not limited to the above embodiments. In the above embodiment, the memory 3 is randomly accessed.
Although it is composed of a memory or the like, it may be replaced with another information storage means such as a hard disk. Further, although the embodiments have been described with reference to a circuit in which the memory control unit 9 and the version information output control unit 10 are combined, each of them has a circuit for controlling the mask of the memory and a circuit for canceling the mask of the memory to execute a certain instruction. A circuit for controlling reading of version information may be used. Further, these can be realized by hardware or software.

[0041]

The version management device of the present invention described above, when the power of the system is turned on, the version information reading section for reading the version information of each processing block constituting the system, and the version information read in this way is normally read by the system. It has a version information storage unit that stores and retains it in a predetermined area before the operation starts, so that the operator can make full use of specialized knowledge for each processing block during system maintenance management and debug processing. Therefore, the work of reading the version information is reduced. In addition, after the system power is turned on and normal operation starts, enter the version control command at any time,
It is also possible to read the version information and store it in a predetermined area.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the device of the present invention.

FIG. 2 is an operation flowchart of the device of the present invention.

FIG. 3 is a block diagram of a memory control unit.

FIG. 4 is an operation timing chart of the device of the present invention.

FIG. 5 is a flow chart of a version confirmation comparative example of the unit.

FIG. 6 is a flowchart of a controller version confirmation comparison example.

FIG. 7 is another operation flowchart of the device of the present invention.

[Explanation of symbols]

 1 Bus line 2 Processor 3 Memory 4 System initialization ROM 7 Version information storage unit 8 Version information reading unit 9 Memory control unit 10 Version information output control unit

Claims (3)

[Claims] 1. When the system is powered on, the version information reading unit that reads the version information of each processing block that configures the system and the version information of each block that is read by the version information reading unit are used for normal operation of the system. Prior to the start of the version management apparatus, the version management apparatus further comprising a version information storage unit that stores and holds the version information in a predetermined area. 2. A memory control unit that masks a version information storage unit that stores version information of each processing block separately from other storage areas of the system, and a mask of the memory control unit by inputting a predetermined version read command. 2. The version management device according to claim 1, further comprising a version information output control unit for canceling. 3. A version information reading unit for reading the version information of each processing block constituting the system by a version management command input at an arbitrary timing, and version information of each processing block read by the version information reading unit. And a version information storage section for storing and holding the same in a predetermined area.