JPH03228111A - Timer control system for data processor - Google Patents

Abstract

PURPOSE:To execute a time monitor processing without contention a program to which the time monitor processing is executed, with the other program by providing a system common data memory to be reloaded only from the specified program. CONSTITUTION:A timer interruption processing program is activated by an interruption signal to be generated by a timer circuit 10 and a CPU 1 reads time at each interruption generation time point from a a calendar circuit 5 and sets a write permission mode to a system common data memory 4. Further, after writing the read date and time from the calendar circuit 5 to the memory 4, a write inhibition mode is set to the memory 4 and the processing is finished. Therefore, the system common data memory 4 always stores the updated date and time information at a time interval for the timer circuit 10 to generate the interruption signal. Thus, without the danger of contention with the other program, the exact time information can be applied to all the programs to which the time monitor processing is executed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a timer management method for a data processing device in which a wide variety of programs are used, and particularly to a timer management method for a data processing device used by a program to perform time monitoring processing. Regarding timer management method.

[Conventional technology]

Conventionally, in a program executed on a normal data processing device, when monitoring the time until the occurrence of an event related to the result after performing a certain process, a software loop process is executed up to a predetermined number of times. death,
A method of checking the occurrence of the cue in the loop processing, a method of activating a timer circuit included in a data processing device and alternately checking the occurrence of an event and a count value of the timer circuit, or the basics of a data processing device. If the turnout program has a function to obtain time, there is a method of monitoring the elapsed time by calling the function of the basic turnout program, and also checking for the occurrence of an event.

[Problem to be solved by the invention]

The first method among the three conventional methods described above has the disadvantage that the number of loops to be executed must be changed depending on the processing speed of the CPU of the data processing device.

In addition, in the second method described above, the resources used by the program executed on the data processing device are completely managed, and there is no conflict with other software regarding the use of the timer circuit. However, if multiple programs created by multiple independent program developers are installed and executed simultaneously on one data processing device, the hardware used between the multiple programs may be Conflicts for hardware resources often occur.

However, if such a conflict occurs in the timer circuit,
There is a drawback that the timer circuit activated in the time monitoring process may be stopped by another program, resulting in an infinite loop. As mentioned above, a situation in which multiple programs created by multiple independent program developers are simultaneously installed and executed on one data processing device is a situation in which data processing devices called personal computers have become increasingly popular in recent years. This often happens in practice.

Furthermore, in the third conventional method described above, if the basic human output program cannot be re-inputted, the basic human output program cannot be inputted between other programs as in the second conventional method. This method has the disadvantage that conflicts occur between program function calls, resulting in problems.

An object of the present invention is to provide a timer management method for a data processing device that can solve all problems such as changes in loop circuits to be executed, conflicts with hardware resources, and competition between basic human output program function calls. It's about doing.

[Means to solve the problem]

The timer management method of the data processing device of the present invention includes a CPU that reads, interprets and executes a program stored and held on the memory, and a CPU that makes all the programs stored and held on the memory visible and that specifies a specific program. It has a system common data memory that is configured to be rewritable only, and a timer circuit that generates an interrupt signal to the CPU at fixed time intervals, and when rewriting the system common data memory, The timer interrupt processing program is activated by a generated interrupt signal and writes time information at the time of occurrence of the interrupt to a predetermined address in the system common data memory.

That is, in the present invention, a timer interrupt processing program activated by an interrupt signal generated by a timer circuit can be written into the system common data memory, and each time an interrupt occurs, time information at the time of occurrence of the interrupt is stored in the timer interrupt processing program. Since the process of writing to a predetermined address in the system common data memory is performed, a program attempting to perform time monitoring processing may have the problem of conflict with other programs by referring to the time information on the system common data memory. Time monitoring processing can be performed without

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data processing device for explaining one embodiment of the present invention.

As shown in FIG. 1, the data processing device 14 in this embodiment includes a CPU that reads, interprets and executes a program stored in a memory, a ROM 2 that stores an initial program when the CPU is reset, and a data processing device 14 that stores data. A RAM 3 for temporarily storing data, a system common data memory 4, a calendar circuit 5 for counting and holding date and time, and an external storage device for reading or writing programs and processing data to be executed on the data processing device 14. An FDD controller 6 that controls a floppy disk device (FDD) 11 and a keyboard input device (K
/B) To control 12, /B controller 7 and CRT
The CRT controller 8 includes a CRT controller 8 that controls a display device (CRT) 13, an interrupt controller 9 that controls a plurality of interrupt signals to the CPUI, and a timer nlO that generates interrupt signals at regular intervals.

FIG. 2 is a flow diagram of a timer interrupt processing program of the data processing apparatus shown in FIG.

As shown in FIG. 2, this timer interrupt processing program relates to a process of reading the current time when a timer interrupt occurs from the timer circuit 10 and the interrupt controller 9, and writing it to the system common data memory 4. That is, the CP LJ 1 reads the current time from the calendar circuit 5 and sets the write permission mode in the system common data memory 4. Thereafter, the CPUI writes the current time into the system common data memory 4, and sets the system common data memory 4 to a write-inhibited (disabled) mode.

Further, FIG. 3 is a configuration diagram of the system common data memory in FIG. 1.

As shown in FIG. 3, the system common data memory 4 has a RAM 23 connected to a data bus 21 and an address bus 22, and a memory address corresponding to the system common data memory 4 that is output to the address bus 22. An address decoder 24 that outputs the 11111 state when detected, a flip-flop 25 that maintains the permission/inhibition state of writing to the RAM 23, and a two-man NAN
D circuits 31 to 33, a two-man AND circuit 34, an inverter circuit 35, and an address decoder that outputs 1 when address information matching the I10 address assigned to the flip-flop 25 is detected on the address bus 22. It has 36. The output 26 of the two-man NAND circuit 31 is the chip select signal (C
3), the output 27 of the two-man NAND circuit 32 is the RAM 23
Write enable signal (WE
>, input 28 is the I10 write signal (IOW) generated when CPU 1 writes to the I10 board, input 2
One represents a memory write signal MW generated when the CPUI performs a memory write operation, and the input 30 represents a memory read signal MR generated when the CPUI performs a memory read operation.

FIG. 4 is a flow diagram of an application program that performs time monitoring processing using the timer management method shown in FIG.

As shown in FIG. 4, a portion of the communication procedure processing program in which a text is sent to a player and then waits for a response from the player is shown as an example.

Next, the operation of the above-mentioned embodiment will be explained with reference to FIGS. 1 to 4.

First, the data processing device 14 shown in FIG. 1 has a timer interrupt processing program of the interrupt controller 9 which is activated by an interrupt signal generated from the timer circuit 10 at regular time intervals. As explained in the flowchart shown in FIG. 2, the program reads the time at the time of occurrence of each interrupt from the calendar circuit 5, and sets the write permission mode in the system common data memory 4. Furthermore, after writing the date and time read from the calendar circuit 5 into the system common data memory 4, a write inhibit mode is set in the system common data memory 4, and the timer interrupt processing is ended. Therefore, the system common data memory 4 stores date and time information that is constantly updated at the time intervals at which the timer circuit 10 generates an interrupt signal.

For example, in the communication procedure control program shown in FIG. 4, when waiting for a response from the other station after sending a text to the other station, time information is programmed from the system common data memory 4 after sending the text to the other station. If you read it into the internal variable area and perform repetitive processing that alternately checks whether a response has been received from the other station and checks for response waiting timeout by comparing the time on the system common data memory 4 and the time of the internal variable. good.

At this time, since time information is acquired by memory reading (-), there is no need to consider the occurrence of competition with other application programs installed on the same data processing device.

In addition, in the system common data memory 4 shown in FIG. 3, when the address information output to the address bus 22 corresponds to the system common data memory 4, the address decoder 24 outputs °1°. At this time, MW
If two signals or the MR signal 30 are "00", the two-man NAND circuit 33 outputs 1°. Therefore, the two-man NAND circuit 31 outputs "0'°, and the RAM 2
The chip select signal 26 of No. 3 is activated.

Whether writing is possible in this RAM 23 is determined by the output state of the flip-flop circuit 25. That is, when writing to the RAM 23, the flip-flop 25
Bit O is °°1' for the 110 address corresponding to
By outputting the data of °, the output of the flip-flop circuit 25 becomes "1". Therefore, by the output of the inverter 35 that inverts the MW signal 29 and the two-man NAND circuit 32 that takes NAND logic, WE multiplies the RMA 23. The signal becomes o'', and writing to the RAM 23 is performed. In addition, the address decoder 36
When the address information output to the address bus 22 matches the address corresponding to the flip-flop 25, the two-manufactured AND circuit 34 propagates the data of bit O of the data bus 21 to the input signal of the flip-flop 25. It is for.

As mentioned above, the program 4 that writes to the system common data memory 4 writes data to the flip-flop 2.
It is necessary to know the I10 address of the flip-flop 25, so by making the I10 address of the flip-flop 25 private to the application program, it is possible to write to the system common data memory 4 and to prevent other application programs from writing to the system common data memory 4. can be made impossible.

〔Effect of the invention〕

As explained above, the timer management method of the data processing device of the present invention allows the timer interrupt processing program that processes interrupt signals that occur at regular time intervals to read the time at the time of interrupt occurrence in all programs. 10. Time monitoring processing is attempted by configuring data to be written to a system common data memory that is configured to be writable only from a specific program.
The advantage is that accurate time information can be given to all programs without the risk of conflict with other programs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data processing device for explaining one embodiment of the present invention, FIG. 2 is a flow diagram of a timer interrupt processing program of the data processing device shown in FIG. Configuration diagram of system common data memory in Figure 4.
This figure is a flowchart of an application program that performs time monitoring processing using the timer management method shown in FIG. ■...CPU, 2...ROM, 3...RAM, 4
... System common data memory, 5... Calendar circuit, 6... FDD controller, 7... K/B controller, 8... CRT controller I/roller, 9... Interrupt controller, 10... ...Timer circuit, 11...
FDD, 12...K/B, 13...CRT, 14...
・Data processing device, 21...Data bus, 22...
Address bus, 23...RAM, 24...address decoder, 25...flip-flop, 26...C
8 signal, 27...WE double signal 28...IOW signal,
29...MW signal, 30...MR double signal 31-33
... 2-person powered NAND circuit, 34... 2-person powered AND circuit, 35... Inverter circuit, 36... Address decoder.

Claims (1)

[Scope of Claims] 1. A CPU that reads, interprets and executes a program stored and held in a memory, and allows all programs stored and held in the memory to be referenced and rewritten only by a specific program. It has a system common data memory configured as such, and a timer circuit that generates an interrupt signal to the CPU at fixed time intervals, and when rewriting the system common data memory, the interrupt signal generated from the timer circuit is 1. A timer management method for a data processing device, comprising a timer interrupt processing program that is activated by an interrupt signal and writes time information at the time of occurrence of the interrupt to a predetermined address of the system common data memory. 2. A timer management system for a data processing device, wherein the system common data memory according to claim 1 stores time information that is constantly updated at time intervals of interrupt signals generated from a timer circuit. 3. The timer interrupt processing program according to claim 1 reads the current time, sets a write permission mode in the system common data memory, then writes the current time in the system common data memory, and then sets the write permission mode in the system common data memory. A timer management method for a data memory device characterized by setting a write inhibit mode in the data memory.