JPH0728570A - Power saving control device for microprocessor - Google Patents

Abstract

PURPOSE:To make an information processor like a personal computer small- sized and light-weight by efficiently saving the power while keeping the high performance. CONSTITUTION:This device consists of a current pattern recognizing part 104 which compares the output of a current detecting device 102, which detects the current consumption of a microprocessor, with the periodicity of the current value and registered current patterns, and the operating clock or the operating voltage of the processor is controlled. The device efficiently saves power while keeping the high performance to make the information processor like a personal computer small-sized and light-weight.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing power consumption of an information processing device having a microprocessor.

[0002]

2. Description of the Related Art First, a conventional technique will be described.

In recent years, in information processing devices such as personal computers, due to the popularization of graphic-based user interfaces, higher performance is required of processors.

Therefore, high-performance processing is realized by increasing the processor operating clock speed and installing a cache memory of SRAM structure which can be accessed faster than the main memory composed of DRAM.

On the other hand, in a portable information processing device having a built-in battery, such as a notebook type personal computer, it is desired to extend the operating time of the battery for use in the field and to reduce the weight for carrying.

[0006] Further, there is a strong demand for energy saving in order to secure resources and protect the environment, and information processing apparatuses have also been targeted.

Under such circumstances, it has become an important subject in developing an information processing apparatus such as a personal computer to save power while maintaining high performance.

As one of the solutions to this problem, when the user is not performing input / output processing such as keyboard input, it is assumed that the information processing apparatus is in an idle state, and the key input processing driver software turns off the backlight of the LCD panel. Therefore, a method of reducing power consumption is considered.

In addition to the above-mentioned backlight, a peripheral input / output device, for example, RS-232C for serial communication is also available.
It is also conceivable to perform processing for cutting off the power of the line driver.

Such a power saving control system is disclosed in
No. 78909.

In addition to this, I / O associated with input / output processing
The register access of the O controller is monitored, and when the adapter access is not performed for a predetermined time or longer, an interrupt is generated and the power of the I / O adapter is turned off.

However, in the above-mentioned conventional technique, there is a problem that the power consumption of the apparatus cannot be reduced by the processing that does not include the input / output processing such as the keyboard. In addition, I / O from the outside
When monitoring the access of the controller, it is not possible to distinguish whether the device is in an idle state or a process that does not include I / O access such as a large amount of data calculation processing, and the power saving control of the device can be appropriately performed. could not.

Further, due to the high speed clock of the processor and the low power consumption of the input / output control controller, the power consumption ratio of the processor portion is relatively increased, and even if the power saving control is performed, the great effect cannot be seen.

[0014]

As described above, the present invention aims to reduce the size and weight of the development of an information processing apparatus such as a personal computer by efficiently saving power while maintaining high performance. .

[0015]

In order to solve the above problems, the following means are considered.

Most of the small-sized information processing devices include a microprocessor composed of a CMOS device, a plurality of memory devices for storing execution codes and data, at least one input / output controller, the microprocessor, the memory device, and I. A constant voltage circuit that supplies power to the / O controller and a clock circuit that generates an operating clock for the microprocessor.

In the above information processing apparatus, the present invention has a current detection means and a current pattern recognition means of a microprocessor, and further has an operation clock lowering means or a voltage value changing means.

In the present invention, the power consumption is reduced by detecting the idle state of the process by the means described below and lowering the operating clock or operating voltage.

[0019]

In many small information processors, a CMOS microprocessor is used, and in a CMOS device, its power consumption changes in proportion to the operating clock, and also changes in proportion to the square of the operating voltage.

The current consumption of the microprocessor depends on the on / off state of the cell transistors that form the internal logic of the processor.
Proportional to the off number, and the operating cell transistors are dependent on the instruction sequence.

During the idle period of the microprocessor,
I / O controller polling, loop command processing, etc.
Repeatedly executing a certain address range.

Therefore, a constant operation sequence is executed inside the processor, and the cell transistors of the internal logic to be turned on / off also have a constant pattern, so that the current consumption becomes periodic.

The microprocessor current during operation is detected by the current detection means in synchronization with the processor clock, and when the current pattern recognition means confirms the periodicity of the current pattern, the processor recognizes that the processor is idle.

Power consumption is reduced by reducing the operating clock or operating voltage of the microprocessor by the operating clock lowering means or the voltage value changing means by the idle state recognition by the current pattern recognition means.

By registering in advance the current change pattern during the execution of the process of polling the data of the external input / output device such as waiting for keyboard input,
It is possible to detect the invalid instruction processing of the processor and control the power consumption efficiently.

Further, even in a multi-task OS in which there is no polling process for the I / O input / output device, power consumption can be controlled efficiently by registering the current change pattern during execution of the idle process.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the detailed structure of the present invention.

An information processing apparatus such as a personal computer comprises a memory device 106 for storing processing programs and data, an I / O device 107 for controlling input / output, and a microprocessor 101 for processing data.

In the embodiment of the present invention, the current detection device 102, the AD conversion device 103, and the current pattern recognition unit 104 are added to the above configuration.

The program code and data are read from the memory device 106, and the microprocessor 101
Is executed by.

At this time, inside the microprocessor 101, a plurality of cells that perform logical operation are synchronized with the clock supplied from the external clock generator 105 and are turned on / off according to the program code.

Next, the outline of the current consumption of the microprocessor 101 will be described with reference to FIG.

FIG. 2 shows the operating states of a plurality of logic cells constituting the microprocessor 101. Each logic cell is turned on / off at a different frequency according to a processing program in synchronization with the operation clock. ing.

As described above, the power consumption increases in a device having a CMOS structure in proportion to its operating frequency. This is because the power consumption of the logic cells constituting the device depends on the frequency. .

As shown in FIG. 2, the power consumption of the entire device is the sum of the power consumptions of the individual logic cells.

Since ON / OFF of the logic cell depends on the program code, the ON / OFF cycle changes with time, and the power consumption of the device also changes with time.

In the polling process and the idle process of the I / O device, the program execution sequence has a periodicity, and as a result, the power consumption of the device also has a periodicity.

The power consumption of the microprocessor 101 is detected by the current detection device 102.

The current detection device 102 is based on, for example, detection of induced electromotive force by a resistor or a winding coil whose voltage drop is negligible.

The power consumption value of the microprocessor 101 detected by the current detection device 102 is input to the current pattern recognition unit 104, and when the periodicity of the current pattern is confirmed, the processor recognizes that it is in the idle state.

By registering in advance the current change pattern during the execution of the processing for polling the data of the external input / output device such as waiting for keyboard input,
Detect processor invalid instruction processing.

By detecting the idle of the current pattern recognition unit 104, the clock generator 105 is controlled and the operation clock input to the microprocessor 101 is reduced to 1/2 or 1/4 to reduce the power consumption of the microprocessor 101.

Further, the input voltage may be lowered by controlling the voltage control circuit of the microprocessor 101.

According to this embodiment, since the external memory access does not occur in the processor incorporating the cache memory, the idle state can be detected even if there is no means for recognizing the operating state of the processor from the outside.

Also in the multiprocessor system, the individual processors can be independently controlled in power saving, which is effective in reducing the power consumption of the system unit.

[0047]

According to the present invention, by efficiently saving power while maintaining high performance, it is possible to reduce the size and weight of an information processing device such as a personal computer.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an operation state of a plurality of logic cells which form a microprocessor.

[Explanation of symbols]

Reference numeral 101 ... Microprocessor, 102 ... Current detection device, 103 ... AD conversion device, 104 ... Current pattern recognition unit, 105 ... Clock generator, 106 ... Memory device, 107 ... I / O device, 108 ... Cache memory.

Claims (3)

[Claims] 1. A microprocessor comprising a CMOS device, a plurality of memory devices for storing execution codes and data, at least one input / output controller, said microprocessor, memory device, and I / O.
A small-sized information processing device including a constant voltage circuit for supplying power to the O controller and a clock circuit for generating an operating clock of the microprocessor has means for detecting current consumption of the microprocessor and means for detecting a current pattern. And a power saving control device for a microprocessor, which controls an operating clock or an operating voltage of the microprocessor. 2. A power saving control method for a microprocessor according to claim 1, wherein the periodicity of the current change is detected and the operating clock or operating voltage of the microprocessor is controlled. 3. A power saving control method for a microprocessor according to claim 1, wherein matching with a current consumption pattern of the microprocessor registered in advance is detected, and an operation clock or an operation voltage of the microprocessor is controlled.