JPH0728876A - Delay time analyzer - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a delay time analyzing apparatus for analyzing a delay time between FFs on a circuit, and displays an error path and also another section shared by an arbitrary section in the error path. The effect on the path is clearly displayed in an easy-to-understand manner, eliminating the inconvenience of confirming the effect on other paths by looking at the conventional circuit diagram.
The purpose is to easily enable the design considering the influence on other paths. [Structure] A critical path determination process 2 for determining a critical path having a maximum integrated delay time of integrating delay times between elements existing between FFs, and having a maximum delay time in the determined critical path. A shared path extraction process 3 for extracting another path sharing the section,
It is configured to display the determined critical path and this shared other path together.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay time analyzing device for analyzing a delay time between FFs on a circuit.

With the progress of VLSI technology, it has become possible to manufacture higher performance and faster logic devices. In order to develop these devices, it is necessary to confirm the speed performance of the devices before manufacturing them. The delay time analysis device is used as a tool for verifying its performance in the design stage of a logic device. As a means for checking the target performance of the logic device to be designed, it is necessary to confirm whether the circuit between each FF operates correctly at the target cycle time of the device before actually manufacturing the device. At this time, it is desired to clarify the influence of an arbitrary section in the critical path that does not reach the target performance on other paths.

[0003]

2. Description of the Related Art A conventional delay time analyzer displays a path between FFs that does not reach a target performance as an error path. Hereinafter, a case where the target performance of the logic circuit of FIG. 8 is analyzed within the range of 14 to 20 will be briefly described. The critical paths to FF1, FF2 and FF3, FF4 and the delay time at that time are calculated as follows.

FF1-a-b-d-e-f-FF3: integrated delay time 2
2 FF1-a-b-d-e-FF4: integrated delay time 1
8 FF2-a-b-d-e-f-FF3: integrated delay time 1
9 FF2-a-b-d-e-FF4: integrated delay time 1
5 Of these, the ones that do not satisfy the target performances 14 to 20 are the FF1-a-b-d-e-f-FF3 of the integrated delay time 22, which is displayed as an error path in FIG. It was changed and displayed).

[0005]

As described above, the error paths between the FFs that do not satisfy the target performance are displayed. However, due to the large scale and complexity of the device, especially the error paths are shown in the verification at the design stage. Many may occur. In this way, when a large number of error paths are extracted by the delay time analysis device, the designer improves the delay time of a certain section so that the integrated delay time of the inter-FF paths satisfies the target performance. When the improved section is shared by other paths, the cumulative delay time also changes for those paths, so we decided to consider these as well.

For example, the logic circuit of FIG.
When delay time analysis is performed within the range of 0, FF1 to FF3
The target path exceeds the target performance and is displayed as an error path. The designer looks at the display of the error path and suppresses the delay time in the section b → d having the maximum delay time in the critical path (the path having the maximum integrated delay time) in the error path from 7 to 5. With this, the integrated delay time of the paths from FF1 to FF3 becomes 20, and the target performance can be satisfied.
However, by improving the delay time in the section of b → d, the integrated delay time of the paths from FF2 to FF4 becomes 13 and the target performance is not satisfied, resulting in an error path.

As described above, if the delay time of the section shared by a plurality of paths is corrected, the integrated delay time of a plurality of other paths is affected, and particularly in the large-scale system seen in recent years.
In a complicated circuit, it is difficult to judge them only by the displayed error paths.

The present invention solves these problems by
In addition to displaying the error path, the effect of any section in the error path on other shared paths was clearly displayed in an easy-to-understand manner, and the effect on other paths was confirmed by looking at the conventional circuit diagram. The purpose is to solve the inconvenience and to easily enable the design considering the influence on other paths.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, the critical path determination process 2 is for determining the critical path having the maximum integrated delay time of the integrated delay times between the elements existing between the FFs.

The shared path extraction processing 3 extracts another path sharing a section having the maximum delay time in the critical path, or another path sharing a section in which the other path passes the most in the critical path. Is extracted, or another path that shares a specified section is extracted from the critical path.

The integrated delay time calculation process 4 calculates the corrected integrated delay time or the like in response to the correction of the delay time of the shared path. The display process 5 displays a critical path and other shared paths.

[0012]

According to the present invention, as shown in FIG. 1, the critical path determination process 2 determines the critical path having the maximum integrated delay time of the integrated delay times between the elements existing between the FFs, and determines the shared path. The extraction processing 3 extracts other paths that share the section having the maximum delay time in the determined critical paths, and the display processing 5 displays the critical paths and the other shared paths together, and the accumulated delay of each path. I am trying to display the time.

Further, the critical path determination processing 2 is FF.
The critical path having the maximum integrated delay time of the integrated delay times between the elements is determined, and the shared path extraction processing 3 determines the section in which other paths pass the most in the determined critical paths. Other shared paths are extracted, and the display processing 5 displays the critical path and the other shared paths together, and also displays the accumulated delay time of each path.

Further, the critical path determination processing 2 is FF.
Another path that determines the critical path having the maximum integrated delay time among the integrated delay times between the elements, and the shared path extraction processing 3 shares the designated section from the determined critical paths. And the display processing 5 displays the critical path and other shared paths together, and also displays the accumulated delay time of each path.

In these cases, the display processing 5 displays the critical path and other shared paths in the order of the accumulated delay time. Further, the integrated delay time calculation process 4 calculates the corrected integrated delay time corresponding to the correction of the delay time of the displayed shared path, and the display process 5 also displays the corrected integrated delay time. I am trying to do it.

Accordingly, the error path is displayed, and at the same time, the influence of an arbitrary section in the error path on other shared paths is clearly displayed and the accumulated delay time of each path and the corrected accumulated delay time are displayed. By displaying it, the inconvenience of confirming the influence on other paths by looking at the conventional circuit diagram is eliminated, and the circuit design with the integrated delay time that satisfies the design target considering the influence on other paths. Can be easily performed.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle configuration of the present invention shown in FIG. 1 will be described. In FIG. 1, a delay time analysis device 1 analyzes a delay time between FFs on a circuit, and a critical path determination process 2 for determining a critical path which is a path having a maximum integrated delay time between FFs. Shared path extraction processing 3 for extracting other paths sharing a section in the critical path, integrated delay time calculation processing 4 for calculating the integrated delay time of the paths between the FFs, and display processing for displaying the critical path on the screen 7 5 and a control unit 6 that performs various controls.

The screen 7 is a screen for displaying a critical path, another path, and an accumulated delay time. The circuit database 8 is a database that stores various types of information about the circuit, and here stores elements (gates) existing between FFs on the circuit, delay times of sections, and the like.

The keyboard 9 is used to input various data and instructions. The mouse 10 is used to input various instructions on the screen 7, and here, for example, designates a section in the critical path for improving the delay time.

Next, the construction and operation of the embodiment of the present invention will be described in detail with reference to FIGS. 2 to 7. Hereinafter, description will be given based on the circuit diagram example of FIG. Here, the integrated delay time between the FFs is calculated using the circuit database 8 for delay time analysis, and the FFs that do not satisfy a certain target delay time.
Although the interval is conventionally displayed as an error path, in the present invention, in addition to the error path display, an embodiment in which the effect of the improvement section on a plurality of paths is obtained and displayed is shown in FIG.
From now on, it will be described in detail with reference to the flowchart of FIG.

FIG. 2 shows a maximum delay time section display flowchart of the present invention. This displays other paths that share the maximum delay time section of the critical paths.

In FIG. 2, S1 designates the start point FF. In the circuit diagram of FIG. 6A, the mouse 10 designates the FF that is the start point of the path for calculating the integrated delay time, for example, the mouse 10 designates FF1 and FF2.

S2 traces from the designated FF to the FF. This is the FF specified in S1
Trace from 1, FF2 to FF3, FF4. Then, the integrated delay times of the traced paths are calculated as shown below in the display example of FIG.

Path accumulated delay time 1 → (a → b → d → e → f →) → 3: 22 (error path) 1 → (a → b → d → e →) → 4: 18 2 → (a → b → d → e → f →) → 3: 192 → (a → b → d → e →) → 4: 15 ... S3 selects a critical path in the error path.
Here, since the target delay time is 14 to 20, 1 → (a → b → d → e → f →) → 3: 22 (error path) is an error path, and there is one here, so Select as a critical path.

In step S4, the maximum delay time section in the critical path is determined. Of the critical paths selected in S3, the section with the maximum delay time is changed from section (a) of FIG. 6 to section b.
→ Determined as d.

In step S5, a path having the maximum delay time section is searched for. S6 is displayed. These S5 and S6 are S
Other paths sharing the section b → d having the maximum delay time in the critical path determined in 4 are extracted as described on the right side, and the integrated delay time at that time is also displayed.
Here, the shared section b → d is underlined.

Path accumulated delay time 1 → (a → b → d → e → f →) → 3:22 (error path) 1 → (a → b → d → e →) → 4: 182 → (a → b → d → e → f →) → 3: 192 → (a → b → d → e →) → 4: 15 S7 corrects the maximum delay time section. Here, the delay time 7 in the section b → d is corrected to the delay time 5.

In step S8, the integrated delay time is recalculated. S
9 is displayed. These S8 and S9 are displayed as follows. The same is repeated thereafter.

Path cumulative delay time 1 → (a → b → d → e → f →) → 3: 22 → 20 1 → (a → b → d → e →) → 4: 18 → 162 → (a → b → d → e → f →) → 3: 19 → 172 → (a → b → d → e →) → 4: 15 → 13 (error path) As described above, the start point FF is designated on the circuit diagram. Correspondingly, tracing is performed from the designated FF until reaching FF, and the critical path in the error path is determined. Corresponding to determining the section with the maximum delay time among the determined critical paths and displaying other paths that share this section, and correcting the delay time of the maximum section of this delay time , Recalculate and calculate and display the resulting integrated delay time. As a result, it is possible to easily display the influence of the correction of the maximum delay time section of the critical path on other paths sharing the section.

FIG. 3 shows a flow chart for displaying the most passing sections according to the present invention. This is to display another path that shares the section through which the other path most passes among the critical paths.

In FIG. 3, S11 is a start point FF.
Instruct. In the circuit diagram of FIG. 6A, the mouse 10 designates the FF that is the start point of the path for calculating the integrated delay time, for example, the mouse 10 designates FF1 and FF2.

In step S12, tracing is performed from the designated FF to the FF. This is the F specified in S11.
Trace from F1, FF2 to FF3, FF4. Then, the integrated delay times of the traced paths are calculated as shown below in the display example of FIG.

Path accumulated delay time 1 → (a → b → d → e → f →) → 3: 22 (error path) 2 → (a → b → d → e → f →) → 3: 19 1 → ( a → b → d → e →) → 4: 181 → (a → b → c → f →) → 3: 17 2 → (a → b → d → e →) → 4: 15 2 → (a → b → c → f →) → 3: 14 S13 selects a critical path in the error path. Here, since the target delay time is 14 to 20, 1 → (a → b → d → e → f →) → 3: 22 (error path) is an error path, and there is one here, so Select as critical path.

In step S14, the most passing section in the critical path is determined. Among the critical paths obtained in S13, the most passing section is determined as the section a → b from (a) of FIG.

In step S15, a path having the most passing section is searched for. S16 is displayed. These S15 and S16
Displays other paths that share the most passing section a → b in the critical path determined in S14 as described on the right side, and also displays the integrated delay time at that time. Here, the shared section a → b is underlined.

Path integration delay time 1 → ( a → b → d → e → f →) → 3: 22 (error path) 2 → ( a → b → d → e → f →) → 3: 19 1 → ( a → b → d → e →) → 4: 181 → ( a → b → c → f →) → 3:17 2 → ( a → b → d → e →) → 4:15 2 → ( a → b → c → f →) → 3: 14 S17 corrects the most passing section. Here, for example, the delay time 5 of the section a → b is corrected to the delay time 3.

In step S18, the integrated delay time is recalculated.
S16 is displayed. The following is displayed by S17 and S18. The same is repeated thereafter.

Path accumulated delay time 1 → ( a → b → d → e → f →) → 3: 22 → 202 → ( a → b → d → e → f →) → 3: 19 → 171 → ( a → b → d → e →) → 4:18 → 16 1 → ( a → b → c → f →) → 3:17 → 15 2 → ( a → b → d → e →) → 4:15 → 13 (error path) 2 → ( a → b → c → f →) → 3:14 → 12 (error path) As described above, in response to the instruction of the start point FF on the circuit diagram, the designated FF To FF to determine the critical path in the error path. Among the determined critical paths, the most transit section is determined and other paths that share this section are displayed, and the delay time of this most transit section is corrected, and the recalculation is performed. Calculate and display the resulting cumulative delay time. As a result, it is possible to easily display the effect of the correction of the most-passing section of the critical path on other paths sharing the section.

FIG. 4 shows a designated improvement section display flowchart (No. 1) of the present invention. This is to display other paths that share the specified improvement section from the critical paths.

In FIG. 4, S21 is a start point FF.
Instruct. In the circuit diagram of FIG. 6A, the mouse 10 designates the FF that is the start point of the path for calculating the integrated delay time, for example, the mouse 10 designates FF1 and FF2.

In step S22, tracing is performed from the designated FF to the FF. This is the F specified in S21.
Trace from F1, FF2 to FF3, FF4. Then, the integrated delay time of this traced path is calculated as follows, which is shown in the display example of FIG.

Path accumulated delay time 1 → (a → b → d → e → f →) → 3: 22 (error path) 2 → (a → b → d → e → f →) → 3: 19 1 → ( a → b → d → e →) → 4: 18 2 → (a → b → d → e →) → 4: 15 ... S23 selects a critical path in the error path. Here, since the target delay time is 14 to 20, 1 → (a → b → d → e → f →) → 3: 22 (error path) is an error path. Since there is one here, Select.

In S24, the critical path selected in S23 is displayed on the screen. On this screen, the user specifies the section to be improved (here, section “b → d”) with the mouse 10.

In step S25, a path having the designated improvement section is searched for. S26 is displayed. These S25 and S
On the screen, 26 searches for another path sharing the improvement section “b → d” on the critical path designated by the user, and displays it as shown on the right side ((d) of FIG. 6).

At S27, the improvement section is corrected. This corrects the delay time of the underlined improvement section displayed on the screen as described on the right side, for example, "7" to "5".
In step S28, the integrated delay time is recalculated. And S26
Then, as shown in FIG. 6E, the integrated delay time after improvement and the error path are displayed on the screen. Repeat below.

From the above, the starting point FF on the circuit diagram
In response to the instruction of, the trace is performed from the instructed FF until reaching the FF, and the critical path in the error path is determined. Among the determined critical paths, other paths that share the improvement section specified by the user are found and displayed together, and the accumulated delay time of each path is displayed in response to the correction of the delay time of the improvement section. Recalculate and display, and if there is an error path, display it accordingly. As a result, it is possible to easily display the influence of the critical path on other paths sharing the designated improvement section.

FIG. 5 shows a designated improvement section display flowchart (No. 2) of the present invention. This is to display other paths that share the specified improvement section from the critical paths. Here, S31 to S34
Is the same as S21 to S24 in FIG.

In FIG. 5, in step S35, a path having a designated improvement interval is searched for, and the integrated delay time is recalculated based on the input interval delay time. This is because the user specifies the improvement section (here, section “b → d”) with the mouse 10 and the improvement delay time (here, “7” to “5”) in the critical path displayed on the screen in S34. ), The designated improvement interval “b →
While searching for another path that shares d ″, the delay time of this improvement section is corrected and the integrated delay time is recalculated.

In step S36, the display is made. This is because the path sharing the improvement section “b → d” found in S35, the integrated delay time after improvement, and the error path, if any, are shown on the right side ((e) of FIG. 6) as follows. To display. Then, the process returns to S35 and is repeated.

Path integrated delay time 1 → (a → b → d → e → f →) → 3: 22 → 202 → (a → b → d → e → f →) → 3: 19 → 171 → ( a → b → d → e →) → 4:18 → 162 → (a → b → d → e →) → 4:15 → 13 (error path) As described above, the start point FF is designated on the circuit diagram. Correspondingly, tracing is performed from the designated FF until reaching FF, and the critical path in the error path is determined. Among the determined critical paths, in response to the user's instruction to modify the improvement section and the delay time of the improvement section, another path sharing the specified improvement section is found and the accumulated delay time is recalculated. If there is a display and error path, that fact is also displayed. As a result, it is possible to easily display the influence of the critical path on other paths sharing the designated improvement section.

FIG. 6 shows an operation explanatory diagram of the present invention. Figure 6
(A) of (a) shows an example of a circuit diagram. This is obtained by extracting the circuit diagram data from the circuit database 8 of FIG. 1 and displaying it on the screen 7 as an image that is easy to understand. Here, FF represents a flip-flop, which is an element serving as a starting point and an ending point for calculating the integrated delay time.

The gates a to f are elements (logic elements, etc.) that make up the circuit. -The line segment connecting each gate a to gate f represents a section,
Numbers represent delay times (relative values).

The maximum delay time section and the section indicated by the arrow represent the section having the maximum delay time among the critical paths having the maximum integrated delay time among the paths from FF1, FF2 to FF3, FF4.

· The most passing section and the section indicated by the arrow are F
Among the paths from F1, FF2 to FF3, FF4, it is the section having the largest number of other shared paths among the critical paths having the longest integrated delay time.

FIG. 6B is a display example (display example of a path sharing the maximum delay delay time section in the critical path). This shows the example displayed in S6 of FIG.
The underlined portion represents the section sharing the maximum delay time in the critical path.

FIG. 6C is a display example (display example of a path sharing the most passing section in the critical path).
This shows the example displayed in S16 of FIG. The underlined portion represents the most passing section in the critical path.

FIG. 6D is a display example (display example of a path sharing a designated improvement section in the critical path). This shows the example displayed in S26 of FIG. The underlined part represents the improvement section in the critical path.

FIG. 6E is a display example (display example of a path sharing a designated improvement section in the critical path). This shows the example displayed in S36 of FIG. The underlined part represents the improvement section in the critical path. Also,
After improvement, the accumulated delay time is recalculated and displayed at the right end. This allows the designer to easily display the integrated delay time after improvement.

FIG. 7 shows a net explanatory diagram between LISs.
This shows a state of a path passing through the inter-LSI net between LSI-1 and LSI-2. In particular, when the printed circuit board is the target of delay time analysis, the inter-LIS net is an improvement section in order to improve the delay time without recreating the LSI. Then, all FF paths that pass through the LIS net in the error path are automatically displayed as described above, the affected paths are clearly displayed, and the accumulated delay time of each path at that time is displayed. The display and the like can be handled in the same manner as described above.

[0060]

As described above, according to the present invention,
In addition to displaying the error path, the effect of any section in the error path on other shared paths is clearly displayed and the accumulated delay time of each path and the corrected accumulated delay time are displayed. Since it is adopted, not only the path that did not achieve the target performance is displayed as an error path, but also the improvement section (maximum delay time section in the critical path, maximum passing section, specified improvement section, etc.) is shared. The influence can be displayed easily by displaying the other paths and the accumulated delay time. This eliminates the inconvenience of checking the effect on other paths by looking at the conventional circuit diagram, and makes it easy to design a circuit with an integrated delay time that satisfies the design goal by considering the effect on other paths. And it became possible to do it quickly.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a maximum delay time interval display flowchart of the present invention.

FIG. 3 is a flow chart for displaying the most passing sections according to the present invention.

FIG. 4 is a designated improvement section display flowchart (No. 1) of the present invention.

FIG. 5 is a designated improvement section display flowchart (No. 2) of the present invention.

FIG. 6 is an operation explanatory diagram of the present invention.

FIG. 7 is an explanatory diagram of a network between LISs of the present invention.

FIG. 8 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1: Delay time analysis device 2: Critical path determination processing 3: Shared path extraction processing 4: Integrated delay time calculation processing 5: Display processing 6: Control unit 7: Screen 8: Circuit database 9: Keyboard 10: Mouse

Claims (5)

[Claims] 1. A critical path determination process (2) for determining a critical path having a maximum integrated delay time of integrating delay times between respective elements existing between FFs, and a maximum value in the determined critical paths. A delay time analysis comprising: a shared path extracting process (3) for extracting another path sharing a section having a delay time, and displaying the determined critical path and the other shared path together. apparatus. 2. A critical path determining process (2) for determining a critical path having a maximum integrated delay time of integrating delay times between respective elements existing between FFs, and in the determined critical path, And a shared path extraction process (3) for extracting another path sharing a section in which the other path passes the most, and displaying the determined critical path and the other shared path together. Delay time analyzer. 3. A critical path determining process (2) for determining a critical path having a maximum integrated delay time of integrating delay times between elements existing between FFs, and in the determined critical path, Shared path extraction processing that extracts other paths that share the specified section (3)
And a delay time analysis apparatus, which displays the determined critical path and other paths that share a designated section. 4. The delay time analyzing apparatus according to claim 1, wherein the paths are displayed in order of accumulated delay time. 5. The delay time according to claim 1, wherein the corrected cumulative delay time is displayed in correspondence with the correction of the delay time of the displayed shared path. Analyzer.