JPH08213468A - Automatic layout method for semiconductor integrated circuits - Google Patents

Abstract

(57) [Abstract] [Purpose] When a critical block is automatically replaced with a block having a high driving capability in a placement method that takes delay into account, it is necessary to replace the critical block that is most effective for the wiring delay until the delay is satisfied. A process for replacing blocks and an arrangement that minimizes the number of blocks to be replaced are performed. [Configuration] After performing automatic placement, the wiring length is calculated, the wiring delay value is calculated, the critical path is extracted, the critical block is extracted, and the path density of the critical block is calculated. The high critical block is automatically replaced with a block with high driving ability (called "buffer sizing"), the wiring length and the wiring delay value are calculated, it is judged whether the delay constraint is satisfied, and if it is not satisfied, the path is passed. The critical block with the next highest density is extracted and buffer sizing is performed again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement system for semiconductor integrated circuits, and more particularly to an automatic placement system in consideration of a connection delay between functional blocks.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have become highly integrated and large-scaled, and the reduction of the wiring width accompanying this has increased the wiring resistance. Therefore, the delay time of the wiring, which is proportional to the product of the wiring resistance and the wiring capacitance, is also increasing.

There is a risk of malfunction due to an increase in the delay time of the wiring, especially in a net where timing is important. In order to prevent this, it is necessary to place and route the blocks on the net in which timing is particularly important while paying attention to the wiring delay value.

As a conventional automatic placement system, for example, in Japanese Patent Laid-Open No. 3-266082, a wiring delay value is calculated by extracting a critical block on a critical path before placement and then placing the critical block interactively. Disclosed configurations have been disclosed.

That is, as shown in FIG. 4, first, the connection information indicating the connection relationship between the functional blocks is stored (step 21), and the critical path (the source pin of the starting block and the load pin of the ending block) is designated (step 21). Step 22).

Next, all the paths connected to the source pins are traced based on the stored connection information, and the critical paths connected to the load pins are extracted from the paths (step 23).

Then, a block on the critical path is extracted as a critical block (step 2
4).

The extracted critical blocks are arranged interactively in the order of connection so that the circuit constraint conditions are satisfied (step 25).

Next, the predicted wiring length is calculated from the arrangement information of the critical block and the connection relationship (step 26), and the wiring delay value is calculated (step 27).

When the blocks can be arranged so that the wiring delay value becomes equal to or less than the limit value of the circuit constraint condition, automatic placement is performed for the remaining (that is, a normal block where the circuit constraint is not severe) (step 28).

However, as in the above-mentioned conventional example, even if the wiring delay value is taken into consideration only at the placement stage, the result of executing the wiring may be different from the result at the placement stage and may not satisfy the wiring delay value. In this case, consider the process up to wiring,
The wiring delay value is satisfied by performing the placement and routing after weighting the critical paths.

Further, in Japanese Patent Laid-Open No. 2-1208845, the delay information obtained from the virtual line length simulation and the required delay time information of the critical path between the signals obtained from the timing verification are input to input the delay information. There has been proposed a device for automatically placing and wiring so as to satisfy the operating speed of an IC.

That is, referring to FIG. 5, after designating a critical path (step 31), weighting is applied to the critical path (step 32), automatic placement is performed (step 33), and rough wiring is performed (step 34). ).

Next, it is judged whether or not all the placement and routing can be performed (step 35). When all the placement and routing are not possible, virtual delay and timing information are input (step 36), and the placement and routing result is requested. It is compared whether the delay is satisfied (step 37).

Then, as a result of judging whether or not the delay request is satisfied (step 38), if it is satisfied,
Place and outline wiring again under the same conditions, and repeat until placement and wiring are completed.

If the delay requirement is not satisfied, the signal weighting is changed (step 39), and then the placement and the rough wiring are performed again, and the process is repeated until the delay is satisfied and the placement and routing can be performed.

Then, when the placement and rough wiring satisfying the delay requirement are completed, the detailed wiring is executed (step 4).
0).

Next, it is judged whether or not all the detailed wirings have been made (step 41). If all the detailed wirings have not been made, whether or not the delays required by the detailed wiring results are satisfied. Are compared (step 42) and it is determined whether the delay requirement is satisfied (step 43). If they are satisfied, detailed wiring is executed again under the same conditions (step 40) until wiring is possible. repeat.

If the delay requirement is not satisfied, the wiring order and weight of the signals are changed (step 44), the detailed wiring is performed again, and the processing is repeated until the wiring is completed.

In the above two conventional examples, when the wiring delay was not satisfied, the wiring delay was satisfied by manually replacing the critical block with a block having a high driving ability.

[0021]

In the conventional placement method considering the wiring delay value, the wiring delay must be taken into consideration for all the extracted critical blocks. There is also a problem that TAT increases, such as manually replacing blocks. Further, when the blocks are replaced, there is a possibility that the blocks may be replaced more than necessary, and the chip area increases.

Therefore, the present invention solves the above-mentioned problems, and in a placement method considering delay, a critical block effective for delay is automatically replaced with a block having a high driving ability, and a block to be replaced until the delay is satisfied. It is an object of the present invention to provide an automatic placement method that reduces the number of devices and suppresses the reduction of TAT and the increase of chip area.

[0023]

In order to achieve the above object, the present invention calculates the path density of functional blocks (referred to as "critical blocks") forming a critical path, and selects the path density from among the critical blocks. (EN) Provided is an automatic placement method of a semiconductor integrated circuit, characterized in that a critical block is replaced with a block having a high driving ability in the order of a high-density critical block so that a wiring delay satisfies a predetermined delay constraint value.

In the semiconductor integrated circuit automatic placement method of the present invention, preferably, a step of calculating a wiring length, a step of calculating a wiring delay value from the wiring length, and a target circuit in which the wiring delay value is predetermined A critical path is extracted by comparing with a constraint condition of No. 1, a step of extracting functional blocks constituting the critical path, a step of calculating a path density of each of the functional blocks, From the step of selecting the functional block with the highest path density, the step of automatically replacing the block with respect to the functional block, and the step of calculating the wiring length again after the block replacement, And a step of calculating a wiring delay value from the wiring length, and a step of comparing the wiring delay value with a limit value indicated in the circuit constraint condition. That.

[0025]

According to the present invention, a block having a high drive capacity is sequentially replaced with a block having a high driving ability in the order of a high block density among the critical blocks, and the block effective for the wiring delay value is replaced.
The block replacement process performed until the delay is satisfied is minimal, and TAT is shortened. Further, according to the present invention, the number of blocks to be replaced can be minimized, so that the increase of the chip area is avoided.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

[0027]

Embodiment 1 FIG. 1 is a flow chart for explaining an embodiment of the present invention.

Referring to FIG. 1, first, functional blocks are automatically arranged (step 1), a predicted wiring length is calculated (step 2), and a wiring delay value is calculated from the predicted wiring length (step 3).

The wiring delay value obtained in step 3 is compared with a predetermined limit value of the target circuit, and a path having a wiring delay value equal to or larger than the limit value (referred to as "critical path") is extracted (step 4). .

Next, all the functional blocks on the critical path are extracted as critical blocks (step 5).

Then, all the paths connected to the source pins of the critical block are traced, and step 5
The density of paths is calculated from the number of paths passing over all the critical blocks extracted in step (step 6).

Based on the path densities calculated in step 6, the critical block with the highest path density is extracted (step 7).

A process (referred to as "buffer sizing") for automatically replacing the critical block extracted in step 7 with a block having high driving capability is performed (step 8).

The wiring length is calculated based on the result of the buffer sizing (step 9), and the wiring delay value is calculated from the obtained predicted wiring length (step 10).

The wiring delay value obtained in step 10 is compared with the limit value of the circuit constraint condition (step 11). If the delay is not satisfied, the critical block having the next highest path density is extracted (step 7). ), And buffer sizing (step 8).

The process is repeated as described above until the delay is satisfied.

As described above, in this embodiment, since the block effective for the wiring delay value is replaced, the block replacement process performed until the delay is satisfied is the minimum necessary, and the TAT is shortened. . Further, according to the present embodiment, the number of blocks to be replaced can be minimized, so that an increase in area can be prevented.

FIG. 2 is an example of a circuit diagram showing the functional blocks and their connection relationships. The present embodiment will be described more specifically with reference to FIG.

In FIG. 2, 201 to 214 are functional blocks, N01 to N14 are source pins, and H01 to H.
Reference numerals 17 respectively indicate load pins.

In the example shown in FIG. 2, the source pin N01 of the functional block 201 to the load pin H of the functional block 214.
It is assumed that the paths up to 13 are extracted as critical paths.

Next, the functional blocks 201 to 213 on the critical path are extracted as critical blocks. Then, all the paths connected to the source pins of the critical block are traced, and the density of the paths is calculated from the number of paths passing over the critical block.

For example, the path connected to the source pin N01 of the critical block 201 is the block 20.
2, 204, 205, 207, 209, 211,
The path to the load pin H13 of the block 212 and the source pin N0 of the blocks 202, 204, 205 and 208
8, the path from the blocks 210 and 211 to the load pin H13 of the block 212, and the blocks 202 and 20
Source pin N09 of 4, 205, 208, block 21
Paths from 0, 211 to the load pin H13 of the block 212, and blocks 202, 204, 206, 208
Of the source pin N08 of the blocks 202, 204, 206 and 208, and the source pin N0 of the blocks 202, 204, 206 and 208 through the source pin N08 of the blocks 210 and 211 to the load pin H13 of the block 212.
9. The path from the block 210, 211 to the load pin H13 of the block 212, and the blocks 203, 21
Source pins N08 of 3, 208, blocks 210, 21
1 to the load pin H13 of the block 212 and the source pin N of the blocks 203, 213, and 208.
09, blocks 210 and 211, and then block 212
There are a total of 7 paths to the load pin H13.

Similarly, there are 5 passes through the critical block 202, 2 passes through 202, 5 passes through 204, and 20 passes.
5 is 3; 206 is 2; 208 is 2; 210 is 2
There is one book, and each of 209 to 214 is one.

Of these, the block 201 having the largest number of passes, that is, having the highest pass density, is extracted and buffer sizing is performed.

The predicted wiring length is calculated based on the result of buffer sizing, and the wiring delay value is calculated. And
Compare the obtained wiring delay value and the limit value of the circuit constraint condition,
If the delay limit value is satisfied, the processing ends.

If the limit value is not satisfied, the critical block 202 having the next highest path density is extracted and buffer sizing is performed so as to satisfy the delay.

In this way, until the delay is satisfied, the critical block having a high path density, that is, effective for the wiring delay is replaced. When the delay is satisfied, the processing ends.

[0048]

Second Embodiment FIG. 3 is a flow chart showing the second embodiment of the present invention.

In this embodiment, after the detailed wiring, the critical block effective for the wiring delay is replaced.

After performing rough routing (also called "global routing") (step 101), detailed routing is performed (step 102), and the actual wiring length is calculated (step 103).

Next, a wiring delay value is calculated from the actual wiring length (step 104).

Then, the wiring delay value calculated in step 104 is compared with a predetermined limit value of the target circuit to extract a critical path (step 105).

A block on the critical path is extracted as a critical block (step 106).

All the paths connected to the source pins of the first block on the critical path are traced, and the density of the paths of all the critical blocks extracted in step 106 is calculated (step 107).

Next, the critical block having the highest path density is extracted (step 108).

Buffer sizing is performed on the extracted critical block having the highest path density (step 109).

Then, rewiring is performed only in the area where the block is replaced (step 110).

The wiring length is calculated again based on the result of buffer sizing (step 111), and the wiring delay value is calculated from the wiring length (step 112).

The calculated wiring delay value is compared with the limit value of the circuit constraint condition. If the delay is not satisfied, a critical block having the next highest path density is extracted (step
108) and buffer sizing (step 109).

As described above, until the delay is satisfied,
Repeat the process.

Although the present invention has been described with reference to the above-described embodiments, the present invention is not limited to the above-mentioned embodiments, and it is needless to say that various embodiments according to the principle of the present invention are included.

[0062]

As described above, according to the present invention, a critical block effective for delay is automatically replaced with a block having a high driving ability. Therefore, the number of blocks to be replaced is the minimum until the delay is satisfied. , TAT is shortened and the chip area is prevented from increasing.

[Brief description of drawings]

FIG. 1 is a flow chart for explaining an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a circuit automatically arranged according to an embodiment of the present invention.

FIG. 3 is a flow chart for explaining a second embodiment of the present invention.

FIG. 4 is a flowchart for explaining a conventional example.

FIG. 5 is a flowchart for explaining another conventional example.

[Explanation of symbols]

1 Step of executing automatic placement 2 Step of calculating predicted wiring length 3 Step of calculating wiring delay value 4 Step of extracting critical net 5 Step of extracting critical path 6 Step of extracting critical block 7 Step of critical block path Step 8 to calculate the density Step 8 to extract the block with the highest path density 9 Step to replace the block with the highest driving ability 10 Step to calculate the predicted wiring length 11 Step 12 to calculate the wiring delay value Satisfy the delay Step 21 of determining whether or not there is a connection 21 Step of storing connection information between functional blocks 22 Step of specifying a critical path 23 Step of extracting a critical path 24 Step of extracting a critical block 25 Critical block Interactively place step 26 step of calculating predicted wiring length 27 step of calculating wiring delay value 28 step of executing automatic placement for the remaining blocks 31 step of designating critical path 32 weighting of critical path Attaching step 33 Performing automatic placement 34 Step executing general routing 35 Step determining whether all placement / wiring has been completed 36 Step inputting virtual delay and timing information 37 Delay requesting placement / wiring results Step 38 to determine whether or not the requirement is satisfied Step 39 to determine whether or not the requirement is satisfied 39 Step to change the weight of the signal so as to satisfy the requirement 40 Step to execute the detailed wiring 41 Is all the detailed wiring completed? Determining step 42 Step 43 of comparing whether or not the result of the fine wiring satisfies the required delay 43 Step of determining whether the requirement is satisfied 44 Step of changing the wiring order and weight of the signals so as to satisfy the requirement 101 General wiring Step 102 for executing detailed wiring Step 103 for calculating detailed wiring 103 Step for calculating wiring length 104 Step for calculating wiring delay value 105 Step for extracting critical path 106 Step for extracting critical block 107 Calculate density of path of critical block Step 108 Extracting a block with the highest path density Step 109 Performing a process of replacing with a block having a high driving capability 110 Step calculating a wiring length 111 Step calculating a wiring delay value 112 Whether the delay is satisfied Sectional steps 201-214 function block N01~N14 source pin H01~H17 load pin

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Claims (3)

[Claims] 1. A density of paths of functional blocks (referred to as "critical block") forming a critical path is calculated, and the critical blocks having a high path density are arranged in descending order of the driving ability of the critical blocks. An automatic placement method for a semiconductor integrated circuit, characterized in that the wiring delay is replaced with a block so that a wiring delay satisfies a predetermined delay constraint value. 2. A step of calculating a wiring length, a step of calculating a wiring delay value from the wiring length, and a step of comparing the wiring delay value with a predetermined constraint condition of a target circuit to extract a critical path. A step of extracting a functional block forming the critical path, a step of calculating a path density of each of the functional blocks, a step of selecting a functional block with the highest path density from the functional blocks, A step of automatically replacing a block with respect to the selected functional block; a step of calculating a wiring length again after the replacement of the block; a step of calculating a wiring delay value from the wiring length; A method for automatically arranging a semiconductor integrated circuit, comprising: comparing the wiring delay value with a limit value indicated by the circuit constraint condition. . 3. A step of calculating a wiring length after performing rough wiring and a detailed wiring, a step of calculating a wiring delay value from the wiring length, and a constraint condition of a target circuit in which the wiring delay value is predetermined. A step of comparing and extracting a critical path, a step of extracting a functional block that constitutes the critical path, a step of calculating the path density of each of the functional blocks, and the most path density of the functional blocks A step of selecting a high functional block, a step of automatically replacing a block with respect to the selected functional block, a step of rewiring the area where the block is replaced, and a wiring length calculation again And a step of calculating a wiring delay value from the wiring length, and comparing the wiring delay value with a limit value indicated in the circuit constraint condition. A method for automatically arranging a semiconductor integrated circuit, comprising: