JPH0732193B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0732193B2 JPH0732193B2 JP63023082A JP2308288A JPH0732193B2 JP H0732193 B2 JPH0732193 B2 JP H0732193B2 JP 63023082 A JP63023082 A JP 63023082A JP 2308288 A JP2308288 A JP 2308288A JP H0732193 B2 JPH0732193 B2 JP H0732193B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- intermediate layer
- film
- stress
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置に関し、特に半導体基板上の多層配
線構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a multilayer wiring structure on a semiconductor substrate.
従来の技術 従来、層間膜としては、プラズマ酸化膜、パッシベーシ
ョンとしては、PSG（リンガラス）やプラズマ窒化膜な
どを配線上に直接堆積する方法がとられていた。2. Description of the Related Art Conventionally, a method of directly depositing a plasma oxide film as an interlayer film and a PSG (phosphorus glass) or plasma nitride film as a passivation on a wiring has been used.
又、形成方法についても、平坦化を目的として、レジス
と用いたエッチバック法、SOG（スピンオングラス）を
用いた塗布法などがとられていた。Further, as a forming method, an etchback method using a resist and a coating method using SOG (spin on glass) have been adopted for the purpose of flattening.
ここで層間膜は、第１層配線上を平坦化し、第２層配線
との絶縁を図る目的で用いられるものであり、パシベー
ション膜は、外部からの水分や不純物から、下部のデバ
イスを守る働きで用いられるものである。Here, the interlayer film is used for the purpose of flattening the first-layer wiring and insulating it from the second-layer wiring, and the passivation film serves to protect the lower device from moisture and impurities from the outside. Is used in.
発明が解決しようとする課題 従来法では、配線上に直接絶縁膜を堆積するため、絶縁
膜中のストレスが配線に加わり、ストレスマイグレーシ
ョンが生じ、断線不良が起こっていた。これは膜中のス
トレス（応力）により、それを緩和しようとする方向に
配線中の原子が移動し、その結果として断線不良が発生
するものである。Problems to be Solved by the Invention In the conventional method, since the insulating film is directly deposited on the wiring, stress in the insulating film is applied to the wiring, stress migration occurs, and disconnection failure occurs. This is because the stress in the film causes the atoms in the wiring to move in a direction to alleviate the stress, resulting in a disconnection failure.
課題を解決するための手段 本発明は上述の課題にかんがみて、パシベーション膜や
層間膜の間に、ストレスを緩和する中間層を形成するも
のである。これにはまず、配線上に、完全な埋め込みの
不可能なラインとスペースで、凹凸を作る。この上に、
層間膜やパシベーションとは別の膜を形成するが、当
然、ここでキーホールと呼ばれる「す」ができる。Means for Solving the Problems In view of the above problems, the present invention is to form an intermediate layer for relieving stress between a passivation film and an interlayer film. To do this, first make irregularities on the wiring with lines and spaces that cannot be completely embedded. On top of this,
A film different from the interlayer film and the passivation film is formed, but naturally, there is a "hole" called a keyhole here.
さらにこの上に層間膜かパシベーションを堆積する。Further, an interlayer film or passivation is deposited on this.
作用 前述の手段をとることにより、配線と層間膜やパシベー
ションの間にキーホールを持つ中間層が形成され、膜の
応力が直接配線に加わることがないため、断線不良が減
少する。Action By taking the above-mentioned means, the intermediate layer having the keyhole is formed between the wiring and the interlayer film or the passivation, and the stress of the film is not directly applied to the wiring, so that the disconnection defect is reduced.
実施例 本発明に係る実施例を第１図および第２図を用いて説明
する。Embodiment An embodiment according to the present invention will be described with reference to FIGS. 1 and 2.
まず、配線100が形成された後、配線の上に選択的に第
１の中間層10を堆積する。ここで、第１の中間層10は第
１図に示される様にある一定のラインとスペースを持つ
ようにパターン形成を行う。次にこの上に、第２の中間
層20を堆積する。ここで、第１の中間層のラインとスペ
ースを、第２図に示すように、キーホール30が作られる
ような間隔に調整する。First, after the wiring 100 is formed, the first intermediate layer 10 is selectively deposited on the wiring. Here, the first intermediate layer 10 is patterned so as to have certain lines and spaces as shown in FIG. A second intermediate layer 20 is then deposited thereover. Here, the lines and spaces of the first intermediate layer are adjusted so that the keyholes 30 are formed, as shown in FIG.
最後に、パッシベーション膜200を堆積する。Finally, the passivation film 200 is deposited.
具体的には、配線100は、アルミニウムで形成し0.8ミク
ロンの厚さ、第１の中間層としても、アルミニウムを用
いて、厚さを0.8ミクロン、ラインとスペースを両方1.0
ミクロン、第２の中間層としてPSG（リンガラス）を0.5
ミクロン用いると、第２図の様なキーホールができる。
さらにパッシベーション膜としてプラズマ窒化膜を0.8
ミクロン程度堆積する。Specifically, the wiring 100 is made of aluminum and has a thickness of 0.8 μm. The first intermediate layer is also made of aluminum and has a thickness of 0.8 μm and both lines and spaces are 1.0 μm.
Micron, PSG (phosphorus glass) 0.5 as the second intermediate layer
If micron is used, a keyhole as shown in Fig. 2 is created.
Furthermore, a plasma nitride film is used as a passivation film.
Deposit about a micron.
ここで生じるキーホールは、窒化膜のストレスを吸収す
ることになり、配線のアルミニウムに伝わらず、従っ
て、ストレスによる断線が減少することになる。The keyhole generated here absorbs the stress of the nitride film and is not transmitted to the aluminum of the wiring, so that the disconnection due to the stress is reduced.
発明の効果 以上のように本発明によれば、配線と層間膜の間に、ス
トレスを緩和する中間層を形成することにより、ストレ
スマイグレーションの少ない多層配線構造を作ることが
でき、信頼性の高い集積回路を作ることができる。EFFECTS OF THE INVENTION As described above, according to the present invention, by forming the intermediate layer for relieving stress between the wiring and the interlayer film, a multilayer wiring structure with less stress migration can be formed, and the reliability is high. Integrated circuits can be made.
第１図は本発明の一実施例における半導体装置の第１の
中間層形成部を示す斜視図、第２図は同実施例装置の断
面図である。 10……第１の中間層、20……第２の中間層、30……キー
ホール、100……配線、200……パシベーション膜。FIG. 1 is a perspective view showing a first intermediate layer forming portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of the same embodiment device. 10 ... First intermediate layer, 20 ... Second intermediate layer, 30 ... Keyhole, 100 ... Wiring, 200 ... Passivation film.
Claims (2)
上に選択的に形成された第１の中間層と、前記第１の中
間層が形成された前記配線上に形成された第２の中間層
と、前記第２の中間層上に形成された保護層とを有し、
前記配線上の前記第１の中間層が選択的に形成されない
部分に周囲が前記第２の中間層により囲まれたキーホー
ルが形成されていることを特徴とする半導体装置。1. A wiring formed on a semiconductor substrate, a first intermediate layer selectively formed on the wiring, and a second intermediate layer formed on the wiring on which the first intermediate layer is formed. An intermediate layer and a protective layer formed on the second intermediate layer,
A semiconductor device, wherein a keyhole surrounded by the second intermediate layer is formed in a portion of the wiring where the first intermediate layer is not selectively formed.
とを特徴とする特許請求の範囲第１項に記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the first intermediate layer is made of the same material as the wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63023082A JPH0732193B2 (en) | 1988-02-02 | 1988-02-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63023082A JPH0732193B2 (en) | 1988-02-02 | 1988-02-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01196857A JPH01196857A (en) | 1989-08-08 |
| JPH0732193B2 true JPH0732193B2 (en) | 1995-04-10 |
Family
ID=12100494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63023082A Expired - Lifetime JPH0732193B2 (en) | 1988-02-02 | 1988-02-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732193B2 (en) |
-
1988
- 1988-02-02 JP JP63023082A patent/JPH0732193B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01196857A (en) | 1989-08-08 |
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