JPH0732464B2 - PLL circuit - Google Patents

Description

The present invention relates to a PLL circuit that generates a clock synchronized with a video signal having jitter such as a VTR reproduction signal.

[Outline of Invention]

A PLL circuit in which a VCO is configured with a re-trigger type mono-multi, an input burst is injected into its trigger input for phase synchronization, and the VCO oscillation frequency is controlled by the phase difference between the VCO oscillation output and the input horizontal synchronization signal. Jitter followability with respect to is good, and the pulling speed is fast.

[Conventional technology]

In the time base collector that corrects the time base fluctuation (jitter) of the output of the VTR, a clock synchronized with the input video signal is created, A / D conversion and writing to the memory are performed based on this clock, and the reference clock is used. Based on this, reading from memory and D / A conversion are performed.

4 and 5 show a clock generating circuit using a conventional PLL circuit. In FIG. 4, the horizontal synchronizing signal H in the input video signal is separated by the synchronizing separating circuit 20, and this horizontal synchronizing signal and VCO22 are separated. The output of is compared with the signal dropped to the horizontal frequency f _H by the frequency divider 23 by the phase comparator 21, the VCO 22 is controlled, and the clock f _CK that follows the jitter of the input (for example, 4 times the subcarrier frequency 4 f _SC ).

In FIG. 5, the burst signal is separated from the input video signal by the burst separation circuit 24, and the divided output of the VCO 22 is compared with the phase comparator 21 in the burst gate section to control the VCO 22 as in FIG. .

[Problems to be solved by the invention]

The clock generation circuit of FIG. 4 has a problem in that the follow-up speed is slow because the synchronization pull-in is performed in the horizontal cycle, and the output phase changes in response to the noise of the horizontal synchronization signal and the change of the slice level. The clock generation circuit shown in FIG. 5 has few malfunctions due to noise, but has a problem that the tracking speed is slow because it uses the burst signal for each 1H, and that it only follows the jitter within one burst wave. That is, if there is a jitter of exactly one wave (360 °) of the burst wave at 1H intervals, the phase comparator 21 cannot discriminate the phase as having a phase error, and the PLL mislocks.

The present invention solves this problem, and follows performance (pull-in performance).
Good, no mislocking, and simple circuit
The object is to provide a PLL circuit that can be easily integrated into an IC.

[Means for solving problems]

As shown in FIG. 1, the PLL circuit of the present invention includes re-trigger type mono-multivibrators MM2 and MM3 as oscillating elements, and injects a burst of the input video signal into the trigger input to lock the VCO1 in its phase. It has. The phase comparison circuit 11 compares the phases of the pulse obtained by dividing the output of the VCO1 to the horizontal synchronization frequency and the horizontal synchronization signal of the input video signal, and controls the oscillation frequency of the VCO1 based on the phase comparison output.

[Work]

Since the VCO is injection-locked to the input burst, the phase lock performance (followability) for the input video is good, and the frequency control is performed by following the phase error with the horizontal sync signal. A clock with a frequency that follows the deviation of 360 ° (jitter) can be obtained.

〔Example〕

FIG. 1 is a block diagram of a PLL circuit to which the present invention is applied, in which mono-multi vibrators 2 and 3 are connected in cascade, and the output of the subsequent stage is fed back from the OR gate 5 to the preceding mono-multi 2 via the differentiating circuit 4 to obtain VCO1. Configured. Mono Multi 2, 3
Is a re-trigger type, and a burst signal obtained from the input video signal through the burst separation circuit 6 and the comparator 7 is injected into the VCO1 through the OR gate 5, whereby the VCO1 is forcibly locked to the input burst phase. Output of VCO1 (f
_SC ) is multiplied by, for example, 4 in the multiplier 8 and taken out as the clock f _CK .

This clock is dropped to the horizontal frequency f _H by the frequency divider 9 and then compared with the input horizontal sync signal obtained from the sync separation circuit 10 by the phase comparison circuit 11. The phase error voltage is given to the CR time constant circuits of the monomultis 2 and 3 to control the oscillation frequency of VCO1. As a result, a clock whose phase is locked to the input burst phase and whose frequency follows jitter (a variation of the horizontal phase) can be obtained.

Since the re-trigger type injection oscillator is used for the VCO1 in this way, the followability to the input phase is good, and the sync pull-in is fast even when the input video is intermittent due to jog search during tape editing. Further, since the oscillation frequency control is performed based on the phase error with the input horizontal synchronization, there is an advantage that the problem of miss clock as shown in FIG. 5 does not occur. It is also easy to integrate VCO1 into an IC.

2 and 3 are operation time charts of the VCO 1,
The figure shows the case where the input burst phase leads the oscillation output.
FIG. 3 shows the case of delay.

As shown in FIG. 2, when the input burst pulse B is input to the monomulti 2 through the OR gate 5 as in C,
A rising trigger is applied and an output with a duty of 50% is obtained at a frequency f _SC (3.58MHz) that is synchronized with the input burst as in D. This output becomes the input of Mono Multi 3 and the falling trigger is applied as shown in Fig. 2E, and the frequency
A pulse output with f _SC and 50% duty can be obtained. This pulse E is differentiated as shown by A in the falling differentiation circuit 4 and re-inputted to the monomulti 2 through the OR gate 5, so that an oscillation output injection-locked to the burst phase is obtained as shown in FIG. 2E. The oscillation frequency is adjusted by the horizontal phase error.

When the input burst has a delayed phase as shown in FIG. 3, the preceding stage monomulti 2 outputs the differential output A as shown in FIG. 3D.
Immediately after being triggered by, it is re-triggered by the rising edge of the input burst. Therefore, the oscillation phase of VCO1 thereafter is locked to the input burst.

〔The invention's effect〕

According to the present invention, as described above, the VCO of the PLL circuit is locked to the input burst phase, and the VCO oscillation frequency is controlled by the phase error between the output and the input horizontal synchronizing signal. It is possible to obtain a frequency output that can follow the jitter of 360 ° or more of the burst wave without mislocking because the deviation of one wave cannot be discriminated.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit showing an embodiment of the present invention, FIGS. 2 and 3 are time charts, and FIGS. 4 and 5 are block diagrams of a conventional PLL circuit. In the reference numerals used in the drawings, 1 ... VCO 2,3 ... monomulti 4 ... differential circuit 5 ... OR gate 6 ... burst separation circuit 7 ... comparator 8 ... multiplier 9 ... divider 10 …… Synchronous separation circuit 11 …… Phase comparison circuit.

Claims (1)

[Claims] 1. A VCO locked to a burst phase by injecting a burst of an input video signal into a trigger input, comprising a re-trigger type mono multivibrator as an oscillating element, and the output of the VCO is divided to a horizontal synchronizing frequency. And a phase comparison circuit for comparing the phase of the input video signal with the horizontal synchronizing signal, and controlling the oscillation frequency of the VCO based on the phase comparison output.