JPH0681045B2 - Phase synchronization circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit which performs stable lock pull-in at the start of a phase comparison operation.

2. Description of the Related Art In recent years, in digital communication, in order to expand the time-axis compressed digital data in the time axis, a phase locked loop circuit that generates a clock of M / N times the input bit rate is often used.

An example of the conventional phase locked loop circuit described above will be described below with reference to the drawings. FIG. 2 is a block diagram of a conventional phase locked loop circuit. 1 is a frequency divider that divides the input clock by N, and F _R2 is a comparison frequency that is the output of the frequency divider 1.
On the other hand, 6 is a voltage controlled oscillator which outputs an output clock,
2 is a frequency divider for dividing the output clock by M, and F _V2 is a comparison frequency which is the output of the frequency divider 2. 3 is the comparison frequency F _R2 , F
Φ _R is a phase comparator that compares the phases at the rising edge of _V2 , and φ _R is the phase of the comparison frequency F _{R2 in} the phase comparator.
_This is a control signal output when the phase of _V2 is advanced, and φ _V is a control signal output when the phase of the comparison frequency F _R2 is delayed from the phase of the comparison frequency F _{V2 in} the phase comparator 3. is there. Reference numeral 4 denotes a charge pump, 5 denotes a low-pass filter (hereinafter referred to as LPF), and the charge pump 4 gives the LPF 5 a change in charge based on the control signals φ _R and φ _V. V _C is a control voltage output from the LPF 5 to the voltage controlled oscillator 6, and the control voltage V _C is used to control the voltage controlled oscillator 6.
To synchronize the output clock with the input clock.

The operation of the phase locked loop configured as above will be described below. 3 and 4 are out of sync,
Alternatively, it is a time chart of the synchronization pull-in operation in which the input is once cut off and resynchronization is performed, and two types of results in both figures can occur depending on the initial state of the phase comparator 3. Each figure shows the comparison frequencies F _R2 , F _V2 control signals φ _R and φ _V, and the control voltage V _C.

First, FIG. 3 shows a case where the phase comparator 3 operates so as to delay the phase of the comparison frequency F _V2 . That is, in the phase comparator 3, the clock waveforms a ₁ b _{1 of} the comparison frequencies F _R2 and F _V2 ,
The phases are compared at the rising edge of each clock as in a ₂ b ₂ ……. In the phase relationship of a ₁ b ₁ , since the comparison frequency F _R2 is delayed in phase from the comparison frequency F _V2 , the control signal φ _V is output from the phase comparator 3 and the voltage of the control voltage V _C is lowered to control the voltage. The frequency of the output clock of the oscillation 3 is lowered. Since the comparison frequency F _R2 lags behind the phase of the comparison frequency F _V2 in a ₂ b ₂ as well, the control signal φ _V is output from the phase comparator 3, the control voltage V _C is further lowered, and the frequency of the output clock is changed. Lowered, a ₃ b ₃ is in phase,
After that, the operation is performed in the synchronized state.

Next, FIG. 4 shows the case where the phase comparator 3 operates so as to advance the phase of the comparison frequency F _V2 . That is, the phase comparator 3 shows a case where the phases are compared at the rising edge of each clock as in the comparison frequencies F _R2 and F _V2 , such as c ₁ d ₁ , c ₂ d ₂ ... In this case, the comparison frequency F _R2 is
_{Since the} phase is ahead of _V2 , the control signal φ _R is output from the phase comparator 3 and acts to increase the control voltage v _C. However, the limit voltage v _c does not change because it is at the upper limit,
The frequency of the output clock does not change either. The phase of the comparison frequency F _V2 advances from the comparison frequency F _{R2 in} the phase relationship of c _n d _n , the control signal φ _V is output from the phase comparator 3, and the control voltage v _C is lowered. Then, a synchronous pull-in operation similar to that shown in FIG. 3 is performed, and a synchronous state is established at c _{n + 2} d _{n + 2} .

Problems to be Solved by the Invention However, in the above configuration, as shown in FIGS. 3 and 4, the initial phases of the comparison frequencies F _R2 and F _V2 are a ₁
It is shown that even if the same as b ₁ and c ₁ d ₀ , a phase comparison of c ₁ d ₁ may be performed as the operation of the phase comparator 3. Therefore, the operations shown in FIG. 3 and FIG. 4 and those in the middle occur randomly, so that there is a problem that the synchronization pull-in time is long on average and the synchronization is not performed promptly. In particular, the division ratio M of the frequency divider 2 that divides by M
However, when the frequency division ratio is increased and the frequency division ratio in the loop is increased, the loop gain of the phase locked loop is reduced, and thus there is a problem that the synchronization pull-in time increases and it takes time to synchronize.

In view of the above problems, the present invention provides a phase locked loop circuit capable of significantly shortening the initial sync pull-in time when the frequency division ratio in the loop is large.

Means for Solving the Problems In order to solve the above problems, the phase locked loop circuit of the present invention is
A first AND circuit that receives the input clock as one input, a first divider that divides the output signal of the first AND circuit, and a second that receives the output clock of the voltage controlled oscillator as one input AND circuit, the second frequency divider for frequency-dividing the output signal of the second AND circuit, and the phases of the frequency-divided outputs of the first and second frequency dividers are compared to determine the first The first control signal output when the frequency division output of the frequency divider leads the phase of the frequency division output of the second frequency divider, and the second control signal which is output when the frequency division output is delayed.
And a phase comparator for outputting the control signal of
And a low-pass filter for smoothing the fluctuation due to the output of the charge pump,
A voltage-controlled oscillator that oscillates an output clock according to the output of the low-pass filter, and inputs the first control signal of the phase comparator to the other input of the first AND circuit to output the second AND circuit. The second control signal of the phase comparator is input to one input of the circuit, and the output clock of the voltage controlled oscillator is input to the other input of the second AND circuit.

Effect of the Invention With the above-described configuration, the present invention is a frequency divider that outputs a frequency-divided output that is judged to be in phase with a control signal output from the phase comparator for a period corresponding to the phase difference of the frequency-divided output. The AND circuit on the side acts so that the input clock is not output from the AND circuit, and forcibly delays the phase of the divided output by the amount by which it has advanced, and it is close to the synchronized state in the next phase comparison operation. By setting the phase relationship, it is possible to stably perform the synchronization pull-in regardless of the phase relationship.

Embodiment A phase locked loop circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a phase locked loop circuit according to an embodiment of the present invention. Common numbers and symbols used in FIGS. 1 and 2 are the same. In FIG.
Reference numeral 7 is a first AND circuit that receives the input clock as one input, 1 is a first frequency divider that divides the signal output from the AND circuit 7 by N, and F _R1 is output from the frequency divider 1. The comparison frequency to be used. On the other hand, 6 is a voltage-controlled oscillator that outputs an output clock. 8 is a second which uses the output clock as one input
Is a second frequency divider that divides the signal output from the AND circuit 8 by M, and F _V1 is a comparison frequency output from the frequency divider 2. 3 is a phase comparator that compares the phases of the comparison frequencies F _R1 and F _V1 , and φ _R is the first control that is output when the comparison frequency F _R1 is ahead of the comparison frequency F _V1 in the phase comparator 3. Φ _V is a signal, and φ _V is a second control signal output in the phase comparator 3 when the comparison frequency F _R1 lags behind the comparison frequency F _{V1 in} phase. Reference numeral 4 is a charge pump, 5 is an LPF, and V _C is a control voltage for controlling the oscillation frequency of the voltage controlled oscillator 6. When the control signal φ _R is input, the charge pump 4 operates to raise the control voltage V _C by sending charges to the LPF 5, and works to increase the oscillation frequency of the voltage controlled oscillator 6, and the charge pump 4 is controlled. When the signal φ _V is input, it operates so as to absorb the charge from the LPF 5 and lower the control voltage V _C , and works to lower the oscillation frequency of the voltage controlled oscillator 6.

However, the relationship between the operation of the control voltage V _C and the oscillation frequency of the voltage controlled oscillator 6 may differ depending on the polarity of the voltage controlled oscillator 6.

The operation of the phase locked loop configured as described above will be described with reference to FIG. FIG. 5 is a time chart of the synchronization pull-in operation for resynchronization from loss of synchronization or loss of input, comparing frequencies F _R1 , F _V1 , control signals φ _R , φ _V and control voltage.
This is for V _C.

FIG. 5 shows a case where the phase comparator 3 works so as to advance the phase of the comparison frequency F _V1 . This is the comparison frequency F
_R1, F _V2 of e ₁ f ₁ phase comparator 3 in the phase that is due to perform the phase comparison. At this time, the control signal φ _R falls at the rising edge of e ₁ and the control signal φ _R rises at the rising edge of f ₁ . That is, the comparison frequency F _R1 is compared to the comparison frequency F _{V1 by the} control signal φ _R
Indicates that the phase is advanced by the period of low level (hereinafter abbreviated as “L”). Therefore, by prohibiting the AND circuit 7 and the control signal φ _{R from} inputting the input clock to the frequency divider 1 while the control signal φ _R is “L”, the phase of the comparison frequency F _R1 is delayed equivalently. Set to position e ₂ . As a result, the phase comparison is performed at e ₂ f ₂ , which is close to the synchronized state. Then, at e ₄ f ₄ , the input clock and output clock are synchronized.

When the phase comparator 3 works so as to delay the phase of the comparison frequency F _V1 , the comparison frequencies F _R2 and F _{V2 of} the time chart shown in FIG. 3, the control signals φ _R and φ _V , and the control voltage V _C Same operation as.

In this way, by performing processing for delaying the phase of the comparison frequency of the one that is forcibly advanced by an amount corresponding to the amount of advance, it is possible to bring the state close to the synchronization state by 2 clocks of the comparison frequency at worst.

EFFECTS OF THE INVENTION As described above, the present invention forcibly delays the phase of the comparison frequency in which the phase is advanced based on the control signal output from the phase comparator. This is because an AND circuit that takes the logical product of the control signal and the clock is provided for the clock that is the input of the divider that outputs the comparison frequency, It controls the number of input clocks.

As a result, the phase of the comparison frequency that leads the phase is forcibly delayed even when synchronization is lost, the loop division ratio is large, and the loop gain is small, and the oscillation frequency of the voltage controlled oscillator is controlled. It is possible to establish synchronization in a very short time with the two operations of doing and AND
It can be realized with a very simple circuit configuration in which only two circuits are added.

[Brief description of drawings]

FIG. 1 is a block diagram of a phase locked loop circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional phase locked loop circuit, and FIG.
4 and 5 are time charts showing the operation of the conventional phase locked loop, and FIG. 5 is a time chart showing the operation of the phase locked loop of the present invention. 1,2 ...... Frequency divider, 3 ...... Phase comparator, 6 …… Voltage controlled oscillator, 7, 8 …… AND circuit, F _R1 , F _R2 , F _V1 F _V2 …… Comparison frequency, φ _R , φ _V: Control signal, V _C: Control voltage.

Claims (1)

[Claims] 1. A first AN having an input clock as one input.
A D circuit and a first frequency divider for dividing the output signal of the first AND circuit
Frequency divider, a second AND circuit that receives the output clock of the voltage controlled oscillator as one input, a second frequency divider that divides the output signal of the second AND circuit, and the first and second The phases of the frequency-divided outputs of the second frequency divider are compared, and output when the phase of the frequency-divided output of the first frequency divider leads the phase of the frequency-divided output of the second frequency divider. And a second control signal output when the phase of the frequency-divided output of the first frequency divider is delayed from the phase of the frequency-divided output of the second frequency divider. And a charge pump that outputs the charge fluctuation based on the first and second control signals by inputting the first and second control signals, and a fluctuation caused by the output of the charge pump. And a voltage controlled oscillator that oscillates an output clock according to the output of the low pass filter. The first control signal of the phase comparator is input to the other input of the first AND circuit, and the second control signal of the phase comparator is input to one input of the second AND circuit, A phase locked loop circuit, wherein the output clock of the voltage controlled oscillator is input to the other input of the second AND circuit.