JPH07326767A - Thin film transistor and liquid crystal display device using the same - Google Patents

Abstract

(57) [Summary] [Object] The present invention provides a thin film transistor capable of reducing a leak current in an element area equivalent to that of a single thin film transistor, and using the thin film transistor as a switching transistor of an LCD, an aperture ratio of a pixel portion is reduced. To improve. An active layer 21, a gate insulating film 13, and a gate electrode 14 are stacked, and a source region 23 is provided on one side of the active layer 21,
Thin film transistor 1 having drain region 25 on the other side
The active layer 21 is separated into a plurality of active layers (for example, the first and second active layers 21A and 21B) by the isolation region 31 having the same conductivity type as the source / drain regions 23 and 25. The separation region 31 is composed of a high-concentration diffusion layer, a low-concentration diffusion layer, or a high-concentration diffusion layer sandwiched between low-concentration diffusion layers. Further, in a liquid crystal display device (not shown), the thin film transistor 1 is used as a switching transistor in a pixel portion.
Is used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a liquid crystal display device using the thin film transistor as a switching transistor.

[0002]

2. Description of the Related Art As a switching transistor of a liquid crystal display device, a thin film transistor [TFT (Thin Film)
Abbreviation of Transistor)] is used. When the thin film transistor is used alone, it is difficult to reduce the leak current. Further, when the thin film transistor is damaged, the pixel switched by the thin film transistor becomes a defective pixel. Therefore, multiple thin film transistors are connected in series, or multiple LDDs (Lightly D
A structure in which thin film transistors having an (oped drain) structure are connected in series is adopted.

A pixel portion of a liquid crystal display device having a switching transistor having a structure in which two thin film transistors are connected in series will be described as an example with reference to a schematic layout diagram of a main portion of FIG.

As shown in the figure, the liquid crystal display device 201 is
Gate line 211 (shown by a chain double-dashed line) and signal line 221
(The portion indicated by the one-dot chain line) and are arranged in a substantially lattice pattern. For example, the gate line 211 is arranged in the horizontal direction, and the signal line 221 is arranged in the vertical direction. The switching transistor portion 231 is formed near a part of each gate line 211, and each gate line 211 and each signal line 221 is formed.
A pixel electrode portion 241 (a portion indicated by a thin line) is formed in a region surrounded by and.

In the thin film transistor (switching transistor) 251, which is formed in the switching transistor portion 231, a part of the gate line 211 is formed in an inverted V shape, and the gate electrode 25 is formed on both sides of the inverted V shaped bent portion.
It is 2,253. The inverted V-shape is an example, and there are other shapes. Each gate electrode 252, 25
Active layers 254 and 255 are provided below 3 via a gate insulating film (not shown).

On one side of the active layer 254, a drain region 256 made of an n ⁺ type diffusion layer is provided. Further, between the other side of the active layer 254 and the active layer 255,
An n ⁺ type diffusion layer 257 is provided. In addition, the active layer 25
On the other side of 5, the source region 25 made of an n ⁺ type diffusion layer is formed.
8 are provided. In the source region 258, the transparent electrode of the pixel electrode portion 241 [for example, ITO (Indium Tin O
xide) electrode] 242 is connected. A signal line 221 is connected to the drain region 256.

[0007]

However, in both the structure in which a plurality of thin film transistors are connected in series and the structure in which a plurality of thin film transistors having an LDD structure are connected in series, the element area occupied by the thin film transistor is large, so that the pixel The aperture ratio of the area becomes small. Therefore, it is difficult to form a bright display element.

It is an object of the present invention to provide a thin film transistor which has an element area similar to that of a single thin film transistor and is excellent in reducing leak current.

[0009]

The present invention is a thin film transistor made to achieve the above object. That is, a thin film transistor in which an active layer, a gate insulating film, and a gate electrode are laminated, a source region is provided on one side of the active layer, and a drain region is provided on the other side of the active layer. , A plurality of active layers are separated by a separation region having the same conductivity type as the source region and the drain region. The isolation region is composed of a high concentration diffusion layer having the same impurity concentration as the source region and the drain region. Alternatively, it is composed of a low concentration diffusion layer having an impurity concentration lower than that of the source region and the drain region. Alternatively, the first isolation region includes a low concentration diffusion layer having an impurity concentration lower than that of the source region and the drain region, and a high concentration diffusion layer having an impurity concentration similar to those of the source region and the drain region. The second isolation region is joined to the region, and the third isolation region is made of a low-concentration diffusion layer having an impurity concentration lower than that of the source region and the drain region and joined to the second isolation region.

A liquid crystal display device using a thin film transistor as a switching transistor of a pixel, wherein the switching transistor is formed of a thin film transistor having any one of the above configurations.

[0011]

In the above thin film transistor, the active layer is separated into a plurality of active layers by the isolation regions having the same conductivity type as the source region and the drain region. Therefore, for example, when one active region is provided in the active layer. Is separated into the first and second active layers by the separation region. Therefore, it is equivalent to two thin film transistors connected in series. Moreover, the element area is almost the same as that of one thin film transistor. Further, since the separation region is composed of the high-concentration diffusion layer, the low-concentration diffusion layer, or the first, second, and third separation regions in which the high-concentration diffusion layer is sandwiched by the low-concentration diffusion layers, it is active in any of the separation regions The layers are separated into multiple layers.
Further, since the active layer is separated by the separation region in which the first, second, and third separation regions are joined in order, each thin film transistor having each separated active layer is LDD (Lightly Doped).
Drain) structure.

In the liquid crystal display device in which the switching transistor of the pixel is formed by the thin film transistor having any one of the above configurations, the area occupied by the thin film transistor is smaller than that in which a single thin film transistor is connected in series. Therefore, it is possible to increase the area of the pixel by the amount of reduction of the area occupied by the thin film transistor, thereby increasing the aperture ratio of the pixel.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the schematic sectional view of FIG. In the figure, (1) shows a schematic sectional view of a planar type thin film transistor, and (2) shows a schematic sectional view of an inverted staggered type thin film transistor.

As shown in (1) of FIG. 1, the thin film transistor 1 has, for example, the following configuration. That is, the semiconductor layer 12 is provided on the substrate 11. A gate electrode 14 is formed on a part of the semiconductor layer 12 via a gate insulating film 13. On the semiconductor layer 12 below the gate electrode 14, an active layer 21 made of, for example, an impurity-doped p ⁻ type polycrystalline silicon layer is formed. In addition, the semiconductor layer 12 on one side of the gate electrode 14 has n ⁻
An LDD diffusion layer 22 made of a type semiconductor and a source region 23 made of an n ⁺ type semiconductor are formed. The gate electrode 1 is formed on the semiconductor layer 12 on the other side of the gate electrode 14.
From the 4 side, the LDD diffusion layer 24 made of n ⁻ type semiconductor and n ⁺
A drain region 25 made of a type semiconductor is formed.

In the active layer 21, the source and drain regions 23, 23 are formed so as not to be directly joined to the source region 23 and the drain region 25 and to be separated into a plurality (two in the figure) of the active layer 21. An isolation region 31 having the same conductivity type as 25 is provided. Therefore, the isolation region 31 separates the active layer 21 into the first active layer 21A connected to the source region 23 and the second active layer 21B connected to the drain region 25.

In the thin film transistor 1, the isolation region 3
By 1, the active layer 21 is separated into a first active layer 21A and a second active layer 21B. Therefore, the thin film transistor 1
Is equivalent to one in which two thin film transistors are connected in series.

In the above description, the LDD diffusion layers 22 and 2 are
Although the thin film transistor 1 in which 4 is formed is shown, for example, L
Even with the structure in which the DD diffusion layers 22 and 24 are not formed, the active layer 21 can be separated by the separation region 31.

Next, an inverted staggered thin film transistor will be described as an example. In the figure, the same components as those described in (1) above are designated by the same reference numerals.

As shown in FIG. 1B, the thin film transistor 2 has the following structure. That is, at least on the surface of the insulating substrate 11, the gate electrode 14 is formed.
Are formed. Further, a gate insulating film 13 is formed so as to cover the gate electrode 14. The active layer 2 is formed on the gate insulating film 13 above the gate electrode 14.
1 is formed. The active layer 21 is made of, for example, amorphous silicon that is not doped with impurities. On one side of the active layer 21, a source region 23 made of an n ⁺ type semiconductor layer is formed in a state of being connected to the active layer 21. On the other side of the active layer 21, the active layer 21
A drain region 25 made of an n ⁺ type semiconductor layer is formed in a state of being connected to the.

An LDD diffusion layer (not shown) may be formed between the active layer 21 and the drain region 25. Further, the active layer 21 and the source region 2
An LDD diffusion layer (not shown) may also be formed between the layers 3 and 3.

In the active layer 21, the source and drain regions 23, 23 are formed so as not to be directly connected to the source region 23 and the drain region 25 and to separate the active layer 21 into a plurality (two in the figure). An isolation region 31 having the same conductivity type as 25 is provided. Therefore, the isolation region 31 separates the active layer 21 into the first active layer 21A on the source region 23 side and the second active layer 21B on the drain region 25 side.

In the thin film transistor 2 having the above-mentioned structure, the active layer 21 is separated from the first active layer 21A and the second active layer 21A by the isolation region 31 having the same conductivity type as the source / drain regions 23 and 25.
It is separated into an active layer 21B. Therefore, the thin film transistor 2 is equivalent to one in which two thin film transistors are connected in series.

Next, an embodiment of the layout of the active layer and the isolation region for the gate electrode will be described with reference to the layout diagram of FIG. In the figure, the active layer 21 and the isolation region 31 of the thin film transistor 1 are shown as a representative. The structure of the active layer and the isolation region described here is the same as that of the inverted staggered thin film transistor 2 described in (2) of FIG.
It is also applicable to.

As shown in FIG. 2A, the gate line 11
The active layer 21 is provided below the gate electrode 14 (the portion indicated by the two-dot chain line) connected to 1 (the portion indicated by the two-dot chain line). A source region 23 is provided on one side of the active layer 21 via the LDD diffusion layer 22, and a drain region 25 is provided on the other side of the active layer 21 via an LDD diffusion layer 24. An isolation region 31 is formed in the active layer 21 so as to cross the gate width direction. Therefore, the active layer 2 is separated by the isolation region 31.
1 is separated into a first active layer 21A and a second active layer 21B.

Although not shown, the gate electrode 1
A gate insulating film (13) is formed between the active layer 21 and the active layer 21. Further, the LDD diffusion layers 22 and 24 may be omitted.

Next, as shown in (2) of FIG. 2, one side below the gate electrode 14 (the portion indicated by the two-dot chain line) connected to the gate line 111 (the portion indicated by the two-dot chain line) is provided. The first active layer 21A is provided. This first active layer 21
A source region 23 is connected to A. On the other side below the gate electrode 14, the first active layer 21A is formed.
The second active layer 21B is provided without being joined to. The drain region 25 is connected to the second active layer 21B. The first and second active layers 21A and 21
On the gate line 111 side of B, for example, an isolation region 31 that is joined to the first and second active layers 21A and 21B is provided.

Although not shown, the gate electrode 1
A gate insulating film (13) is formed between the active layer 21 and the active layer 21. In addition, the second active layer 21B and the drain region 25
It is also possible to provide an LDD diffusion layer (not shown) between and. Further, an LDD diffusion layer (not shown) may be provided between the first active layer 21A and the source region 23.

Next, the structure of the separation area described in FIG. 2A will be described with reference to the layout diagram of FIG. In the figure, the active layer and the isolation region of the thin film transistor 1 are shown as a representative. The configuration of the active layer and the isolation region described here is also applicable to the inverted staggered thin film transistor 2 described in (2) of FIG.

As shown in FIG. 3A, the active layer 21
Is doped with, for example, p ⁻ type impurities. Alternatively, it is made of amorphous silicon which is not doped with impurities. The active layer 21 includes the first and second active layers 21.
An isolation region 31 is formed along the gate width direction, which is separated into A and 21B and is composed of an n ⁺ -type high-concentration diffusion layer having an impurity concentration substantially equal to that of the source and drain regions (23, 25).

As shown in FIG. 3B, the active layer 21
Is doped with, for example, p ⁻ type impurities. Alternatively, it is made of amorphous silicon which is not doped with impurities. The active layer 21 includes the first and second active layers 21.
A separation region 31 is formed along the gate width direction, which is separated into A and 21B and is composed of an n ⁻ -type low-concentration diffusion layer having an impurity concentration lower than that of the source / drain regions (23, 25). The impurity concentration of the isolation region 31 is, for example, approximately the same as that of the n ⁻ type low concentration diffusion layer having the LDD structure.

As shown in FIG. 3C, the active layer 21
Is doped with, for example, p ⁻ type impurities. Alternatively, it is made of amorphous silicon which is not doped with impurities. The active layer 21 includes the first and second active layers 21.
An n ⁻ -type first isolation region 31A for separating into A and 21B and having an impurity concentration lower than that of the source / drain regions (23, 25) is provided in the gate width direction.
Further, the source, in a state of being bonded to the first isolation region 31A,
An n ⁺ -type second isolation region 31B having an impurity concentration similar to that of the drain region (23, 25) is provided. Furthermore, the source is connected to the second isolation region 31B,
An n ⁻ -type third isolation region 31C having an impurity concentration lower than that of the drain regions (23, 25) is provided. Therefore, the first, second and third separation regions 31A, 31B,
31C is provided substantially in parallel along the gate width direction. The impurity concentration of the first and third isolation regions 31A and 31C is set to be approximately the same as the impurity concentration of the LDD diffusion layer (not shown), for example.

Next, the structure of the separation area described in FIG. 2B will be described with reference to the layout diagram of FIG. In the figure, the active layer and the isolation region of the thin film transistor 1 are shown as a representative. The configuration of the active layer and the isolation region described here is also applicable to the inverted staggered thin film transistor 2 described in (2) of FIG.

As shown in FIG. 4A, the first and second active layers 21A and 21B are doped with, for example, p ⁻ type impurities. The isolation region 31 is composed of an n ⁺ -type high-concentration diffusion layer having an impurity concentration substantially equal to that of the source / drain regions (23, 25), and includes the first and second active layers 2
It is formed in the gate length direction by joining to 1A and 21B.

As shown in FIG. 4B, the first and second active layers 21A and 21B are doped with, for example, p ⁻ type impurities. The isolation region 31 is composed of an n ⁻ -type low-concentration diffusion layer having an impurity concentration lower than that of the source / drain regions (23, 25), and includes the first and second active layers 2
It is formed in the gate length direction by joining to 1A and 21B. The impurity concentration of the isolation region 31 is, for example, approximately the same as that of the n ⁻ type low concentration diffusion layer having the LDD structure.

As shown in FIG. 4C, the first and second active layers 21A and 21B are doped with, for example, p ⁻ type impurities. The isolation region 31 is composed of the first, second and third isolation regions 31A, 31B and 31C, and the first isolation region 31A and the third isolation region 31C are arranged substantially along the gate length direction without being joined to each other. And the second separation regions 31B arranged in parallel with each other.
Is joined to. The first active layer 21A is joined to the first isolation region 31A. Further, the second active layer 21B is joined to the third isolation region 31C.

The first isolation region 31A has an impurity concentration n lower than that of the source / drain regions (23, 25).
^- consists -type diffusion layer, a second isolation region 31B is the source, consists of n ⁺ -type diffusion layer having an impurity concentration substantially equal to that of the drain region (23, 25). Further, the third separation region 31C is
Source / drain regions (2
3, 25) and an n ⁻ type diffusion layer having an impurity concentration lower than that of the above. The impurity concentrations of the first and third isolation regions 31A and 31C are set to be approximately the same as the impurity concentration of the LDD diffusion layer (not shown), for example.

In any structure of the isolation region 31 described with reference to FIGS. 3 and 4, the first and second active layers 21A and 21B).
Is separated into Therefore, the thin film transistor 1 (2)
Is equivalent to connecting a single thin film transistor in series. Further, in a case where the first and third impurity regions 31A and 31C having a lower concentration than the impurity concentration of the second isolation region 31B are provided, each of the separated thin film transistors is LDD (Ligh.
It becomes a thin film transistor of tly Doped Drain structure.

In FIGS. 1 to 4, the n-channel thin film transistor 1 (2) has been described as an example. As described above, the structure in which the active layer is separated by the separation region is
It can also be applied to a p-channel thin film transistor. In that case, in the above description, the conductivity type is changed from n type to p type,
The p type may be replaced with the n type.

Next, a structure using the thin film transistor 1 (2) as a switching transistor of a liquid crystal display device is
This will be described with reference to the schematic layout diagram of the main part of FIG. In the figure, a liquid crystal display device 101 in an active matrix type display device will be described. Then, as a representative, description will be made by using the thin film transistor 1 having the isolation region having the configuration described in (3) of FIG.

As shown in FIG. 5, the liquid crystal display device 101
Indicates the gate line 111 (shown by a chain double-dashed line) and the signal line 1
21 (portion indicated by a one-dot chain line) are arranged in a grid pattern. For example, the gate line 111 is arranged in the horizontal direction and the signal line 121 is arranged in the vertical direction. A switching transistor section 131 and a pixel electrode section 141 (portion indicated by a thin line) are formed in a region surrounded by each gate line 111 and each signal line 121.

The thin film transistor (switching transistor) 1 formed in the switching transistor portion 131 has a gate electrode 14 connected to the gate line 111.
And a gate insulating film (not shown) and an active layer 21 formed thereunder. On one side of the active layer 21, a source region 23 made of an n ⁺ type diffusion layer is provided via an LDD diffusion layer 22 made of an n ⁻ type diffusion layer. Further, on the other side, an LDD composed of an n ⁻ type diffusion layer
A drain region 25 formed of an n ⁺ type diffusion layer is provided via the diffusion layer 24. In the source region 23, a transparent electrode of the pixel electrode portion 141 [for example, ITO (Indium Ti
n Oxide) electrode] 142 is connected. A signal line 121 is connected to the drain region 25.

The active layer 21 is provided with an isolation region 31 along the gate width direction. This separation area 31
Consists of first, second and third isolation regions 31A, 31B and 31C provided in parallel along the gate width direction. The first isolation region 31A includes the source region 23 and the drain region 25.
And an n ⁻ type diffusion layer having a lower impurity concentration.
The second isolation region 31B is composed of an n ⁺ -type diffusion layer having the same impurity concentration as the source region 23 and the drain region 25, and is joined to the first isolation region 31A. The third isolation region 31C includes the source region 23 and the drain region 25.
An n ⁻ -type diffusion layer having a lower impurity concentration than
It is joined to the second isolation region 31B. In addition, the first,
The impurity concentration of the third isolation regions 31A and 31C is, for example, L
It is set to the same level as the impurity concentration of the DD diffusion layer (not shown).

Next, another configuration example of the liquid crystal display device will be described with reference to the layout diagram of the main part of FIG. In the figure, FIG.
The same reference numerals are given to the same components as those described in.

As shown in FIG. 6, the liquid crystal display device 101
Indicates the gate line 111 (shown by a chain double-dashed line) and the signal line 1
21 (portion indicated by a one-dot chain line) are arranged in a grid pattern. For example, the gate line 111 is arranged in the horizontal direction and the signal line 121 is arranged in the vertical direction. A switching transistor section 131 and a pixel electrode section 141 (portion indicated by a thin line) are formed in a region surrounded by each gate line 111 and each signal line 121.

The thin film transistor (switching transistor) 1 formed in the switching transistor portion 131 has a gate electrode 14 connected to the gate line 111.
(A portion indicated by a two-dot chain line) is provided. The first active layer 21A is provided on one side below the gate electrode 14. The source region 23 is connected to the first active layer 21A. On the other side below the gate electrode 14, a second active layer 21B is provided without joining to the first active layer 21A. The drain region 25 is connected to the second active layer 21B. And the above first,
On the gate line 111 side of the second active layers 21A and 21B, for example, an isolation region 31 that is joined to the first and second active layers 21A and 21B is provided.

The separation area 31 is composed of first, second and third separation areas 31A, 31B and 31C. The first isolation region 31A and the third isolation region 31C are arranged substantially along the gate length direction without being joined to each other, and are joined to the second isolation region 31B arranged in parallel with each other. The first active layer 21A is joined to the first isolation region 31A. Further, the second active layer 21B is joined to the third isolation region 31C.

The first isolation region 31A has an impurity concentration lower than that of the source / drain regions (23, 25).
^- consists -type diffusion layer, a second isolation region 31B is the source, consists of n ⁺ -type diffusion layer having an impurity concentration substantially equal to that of the drain region (23, 25). Further, the third separation region 31C is
Source / drain regions (2
3, 25) and an n ⁻ type diffusion layer having an impurity concentration lower than that of the above. The impurity concentrations of the first and third isolation regions 31A and 31C are set to be approximately the same as the impurity concentration of the LDD diffusion layer (not shown), for example.

A pixel electrode portion 141 is formed in the source region 23.
Transparent electrodes [eg ITO (Indium Tin Oxide) electrodes]
142 is connected. A signal line 121 is connected to the drain region 25.

In the liquid crystal display device 101, by using the thin film transistor 1 having the above structure as the switching transistor, the cell area of the switching transistor can be reduced as compared with the structure in which two single thin film transistors are connected in series. . For example, the aperture ratio of the pixel can be increased by about 20% as compared with the conventional two thin film transistors connected in series. Further, instead of the thin film transistor 1 described above, the thin film transistor 2 described in (2) of FIG. 1 can be used. The example of the arrangement of the active layer 21 and the isolation region 31 has been described above with reference to (1) and (2) of FIG. 2, but the arrangement design is not limited to these, and the effect of the invention is also described above. Obtained as in the example. Further, as the structure of the separation region 31, any of the structures described in FIGS. 3 and 4 may be adopted.

[0050]

As described above, according to the present invention,
Since the active layer is divided into a plurality of regions by the isolation region having the same conductivity type as the source region and the drain region, it is equivalent to connecting a plurality of thin film transistors in series. Therefore, the leak current of the thin film transistor can be reduced. Further, even if one of the separated thin film transistors is damaged, it is compensated by the other thin film transistor. Therefore, pixel defects can be reduced. Further, since the active layer of the single thin film transistor is provided with the isolation region to divide the active layer into a plurality of layers, the area occupied by the thin film transistor becomes almost equal to that of the single thin film transistor. Therefore, the aperture ratio of the pixel area does not decrease. Therefore, a bright display element can be formed.

In the liquid crystal display device in which the switching transistor of the pixel is formed by the thin film transistor of the present invention, the area occupied by the thin film transistor is smaller than that in which a single thin film transistor is connected in series. Therefore, it is possible to increase the area of the pixel by the amount of reduction of the area occupied by the thin film transistor, thereby increasing the aperture ratio of the pixel. Therefore, the screen of the liquid crystal display device can be brightened.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of an embodiment of the present invention.

FIG. 2 is a layout diagram of an active layer and an isolation region for a gate electrode.

FIG. 3 is a layout diagram of a configuration of a separation region.

FIG. 4 is a layout diagram of a configuration of a separation region.

FIG. 5 is a schematic layout diagram of a main part of a liquid crystal display device.

FIG. 6 is a schematic layout diagram of main parts of another liquid crystal display device.

FIG. 7 is a schematic layout diagram of a main part of a conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 thin film transistor 2 thin film transistor 13 gate insulating film 14 gate electrode 21 active layer 23 source region 25 drain region 31 isolation region 31A first isolation region 31B second isolation region 31C third isolation region 101 liquid crystal display device 131 switching transistor unit

Claims (5)

[Claims] 1. A thin film transistor comprising an active layer, a gate insulating film, and a gate electrode, which are stacked, and which has a source region on one side of the active layer and a drain region on the other side of the active layer. Is separated into a plurality of active layers by an isolation region having the same conductivity type as the source region and the drain region. 2. The thin film transistor according to claim 1, wherein the isolation region includes a high-concentration diffusion layer having an impurity concentration similar to that of the source region and the drain region. 3. The thin film transistor according to claim 1, wherein the isolation region includes a low concentration diffusion layer having an impurity concentration lower than those of the source region and the drain region. 4. The thin film transistor according to claim 1, wherein the isolation region is a first isolation region formed of a low-concentration diffusion layer having an impurity concentration lower than those of the source region and the drain region, and the source region and the drain. A second isolation region formed of a high-concentration diffusion layer having an impurity concentration similar to that of the region and joined to the first isolation region; and a low-concentration diffusion layer having an impurity concentration lower than those of the source region and the drain region. A thin film transistor comprising a third isolation region that is joined to the second isolation region. 5. A liquid crystal display device using a thin film transistor as a switching transistor of a pixel, wherein the switching transistor is any one of claims 1 to 4.
A liquid crystal display device comprising the thin film transistor according to claim 1.