JPH07336320A - Frame synchronization circuit in TDMA multiplex transmission - Google Patents

Abstract

(57) [Summary] [Object] Regarding a frame synchronization circuit for TDMA transmission, a frame for TDMA transmission capable of flexibly responding to fluctuations in frame pattern detection error factors and changes in synchronization protection conditions, and capable of reducing hardware scale Provide a synchronization circuit. A frame position prediction memory corresponding to a user, a frame position generation circuit that determines a frame position from the output of the memory and a burst frame counter, and a ± n window that creates a window based on the frame position determined by the frame position generation circuit Creation circuit, frame pattern detection circuit for detecting frames within the window, sync state storage memory for reading sync state number, user sync state storage memory for reading previous sync state numbers of all users, and sync state number And a synchronization state detection circuit corresponding to the user supplied with the output of the storage memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit in TDMA multiplex transmission, and more particularly, it is capable of flexibly coping with fluctuations in frame pattern detection error factors and changes in synchronization protection conditions. The present invention relates to a frame synchronization circuit in TDMA multiplex transmission capable of reducing the wear scale.

In TDMA multiplex transmission, bidirectional transmission is performed by dividing a time zone, performing downlink transmission in a certain time zone, and performing uplink transmission in the remaining time zone. .

FIG. 7 shows a TD with user line transmission in mind.
It is a structure (schematic diagram) of a burst frame in MA multiplex transmission. In FIG. 7, data transmission from the terminal station to the user and control information for transmission from the user to the terminal station are performed in the time zone indicated as “station → user”.
On the other hand, data is transmitted from the user to the terminal station during the time zone displayed as “user → station”.

What is important in the transmission from the user to the terminal station is that the data is transmitted from the user terminal in time with the timings T ₁ to T _n at the beginning of the data in the burst frame. Then, for that purpose, the control information designating which timing should be selected and transmitted is transmitted from the terminal station during the transmission time zone from the terminal station to the user.

However, since the transmission timing of data from the user terminal is determined from the burst control information of the station → user, the actual transmission timing may be deviated, and the propagation time of the user line may have an error. Occurs, the data from the user terminal does not always arrive in time from T ₁ to T _n .

Nevertheless, at the terminal station, it is necessary to process the data from the user terminal at a fixed time. Therefore, the frame synchronization circuit in TDMA multiplex transmission plays an important role.

[0007]

2. Description of the Related Art FIG. 6 shows a conventional frame synchronization circuit. In FIG. 6, 3 is a burst frame counter for generating timing (frame position) in the burst frame, 4 is a frame pattern detection unit, and 5 is a synchronization protection unit. Further, 41 is a frame position latch circuit for holding the timing within the frame, 42 is a frame position generation circuit for generating a frame position other than hunting, and 43 is a frame detection position for switching the frame detection position between hunting and non-hunting. A selection circuit, 44 is a frame position detection circuit for detecting a frame, 45 is a latch timing generation circuit for generating a frame detection position during hunting, 51 is an OK counter for counting the detection of a frame, and 52 is a frame detection An NG counter that counts that the synchronization has not been performed, and 53 is a synchronization state detection circuit that determines the synchronization state. The frame pattern detection unit 4 and the synchronization protection unit 5 are fixedly provided to the user.

In the configuration of FIG. 6, the frame position detected during hunting is used as a reference, and the frame is detected within the fixed frame detection window during non-hunting.
When the frame is detected, the OK counter is advanced, and when the frame cannot be detected, the NG counter is advanced to perform the synchronization protection, and the synchronization protection state is fixedly determined by the count value of the counter.

Therefore, in the conventional frame synchronizing circuit, the frame detecting circuit is flexible against the error in the position for detecting the frame caused by the error in the transmission timing at the user terminal or the propagation time in the user line, and the change of the synchronization protection condition. I cannot respond.

There is also a problem that the circuit scale becomes large because a frame pattern detection section and a synchronization protection section must be provided for each user.

[0011]

SUMMARY OF THE INVENTION The present invention can cope with such a problem and flexibly deal with a change in frame pattern detection error factor and a change in synchronization protection condition.
Moreover, it is an object of the present invention to provide a frame synchronization circuit in TDMA multiplex transmission capable of reducing the hardware scale.

[0012]

FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1 is a frame pattern detection unit,
Reference numeral 2 is a synchronization protector, and 3 is a burst frame counter. Further, 11 is a frame position prediction memory that stores a predicted value of the frame position for each user, 12 is a frame position generation circuit that generates a pulse corresponding to the frame predicted position, and 13 is a reference based on the output signal of the frame position generation circuit. A ± n window generating circuit for generating a window, 14 is a frame pattern detecting circuit for detecting a frame pattern in the created ± n window, 21 is a synchronization state number storage memory for determining a synchronization state, and 22 is a plurality of users. In contrast, a user synchronization state storage memory for storing the previous synchronization state, 23, 24 and 25 are a synchronization state detection circuit # 1 and a synchronization state detection circuit # 1 for determining the synchronization state of each user.
2. Synchronous state detection circuit #m.

The feature of the configuration of FIG. 1 is that the frame pattern detection unit and the synchronization state number storage memory and the user synchronization state storage memory of the synchronization protection unit are shared by a plurality of users, and only the synchronization state detection circuit is unique to each user. Is the point.

[0014]

In the configuration of FIG. 1, the predicted value of the frame position in consideration of the propagation time of the line connected to the user is read from the frame position prediction memory with the user number as an address, and the read value is used as the count value of the burst frame counter. A frame position generation circuit generates a predicted position of the frame. A window of ± n bits is created based on this frame predicted position, and a frame pattern is detected from the data within this range. (More specific description will be given in the section of the embodiment.) A predetermined synchronization state number is written in the synchronization state number storage memory. The user synchronization status storage memory stores the previous synchronization status for a plurality of users, and the previous synchronization status is read with the user number as an address.

The synchronization state number stored in the synchronization state number storage memory is the frame detection position number detected by the frame pattern detection circuit and the number indicating the previous synchronization state stored in the user synchronization state storage memory. Is read as. The frame position detection number indicates whether or not a frame is detected at the correct position, and by combining this with the previous synchronization state, the current synchronization state can be determined. Therefore, if the read synchronization state number is supplied to the synchronization state detection circuit provided for each user to determine the synchronization state, the synchronization state can be grasped for each user. The read sync status number is written in the user sync status storage memory and used as reference data for the next sync status determination.

In this way, the frame position in the window of ± n bits is detected using the propagation time data for each user, and the new synchronization state is determined from the combination of this and the previous synchronization state. In addition to being able to flexibly respond to fluctuations in frame detection error and protect synchronization, the sync status number can be externally written to the memory, so it can flexibly respond to changes in sync protection conditions. be able to.

Further, since the circuit unique to the user is only the synchronization state detection circuit, the scale of the frame synchronization circuit can be reduced.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The frame position generation circuit comprises a subtraction circuit and a coincidence detection circuit. And in the subtraction circuit,
Times (T _{1 to} T _n in FIG. 7) at the beginning of data sent from the user to the station in the burst frame, which the frame prediction position memory outputs in consideration of the propagation time between the station and the user
From which the time corresponding to n bits is subtracted. This value is compared with the count value output from the burst frame counter by the match detection circuit, and when a match is found, a pulse is output and supplied to the ± n bit window creation circuit.

The ± n bit window forming circuit is composed of a (2n + 1) bit shift register having a width of ± n bits from the reference timing. The output pulse of the coincidence detection circuit is applied to the serial input terminal of the shift register and is shifted by the clock. Then, a pulse shifted by one bit is output from the parallel output terminal of the shift register. Since the frame pattern detection circuit detects the frame pattern based on this output pulse, the frame pattern is detected at n bits before and after the reference phase.

With this detection result as a part of the address, the number indicating the synchronization state is read from the synchronization state number storage memory, and the synchronization protection operation is performed. This will be described in detail next.

FIG. 2 is a state transition diagram in the embodiment of the present invention. In the state transition diagram of FIG. 2, as the synchronization protection condition, one stage of rear protection and two stages of front protection are shown as an example. Then, with respect to the synchronous state, 0 is defined for hunting, 1 is defined for the synchronous state, and 2 is defined for the asynchronous state.

In the state transition diagram of FIG. 2, if the frame pattern cannot be detected during hunting, the hunting state is restored again. If the frame pattern can be detected during hunting, the backward protection is set to the first stage, and the state transits to the synchronized state. In the synchronized state, if the frame pattern can be detected, it stays in the synchronized state. When the frame pattern cannot be detected in the synchronous state, the front protection is entered and the state becomes asynchronous. If the frame pattern can be detected in this state, the state returns to the synchronized state. Then, when the frame pattern cannot be detected twice in a row, the process returns to hunting.

FIG. 3 shows the frame pattern detection position numbers in the present invention. In FIG. 3, the window width n is displayed as 3. Then, the detection position number is defined as 0 for the window position +3 where the frame pattern is detected, and the detection position number is incremented by 1 while the window position is decreased by 1, and the window position is detected for the window position -3. Is defined as 6. The detection position is defined as 7 when the frame pattern cannot be detected.

A synchronization status number is defined by the combination of the detected position number and the previous synchronization status number, and is written in the synchronization status number storage memory. FIG. 4 shows the contents (1) of the synchronization status number storage memory. In the table, the "synchronization state number" in the address column is a number indicating the previous synchronization state stored in the user synchronization state storage memory.
The "frame pattern detection position number" in the address column is the number shown in FIG. 3 output by the frame pattern detection circuit. Then, the frame pattern detection allowable error is ± 1
Indicates the synchronization status number when set to.

For example, it is assumed that the previous synchronization state number for a certain user is 0, that is, hunting is in progress.
If the frame pattern detection position at this time is from 2 to 4, it indicates that the frame pattern is detected within an allowable range of ± 1 bit with respect to the predicted position of the frame. Since the backward protection is assumed to be one stage, 1 indicating synchronization is stored in the address determined by the previous synchronization state number and the current frame pattern detection position number in the synchronization state number storage memory. 1 indicating this synchronization is read from the synchronization state number storage memory and supplied to the synchronization state detection circuit of the user, and the output of the synchronization state detection circuit performs data processing of the user and synchronization state monitoring. When the previous sync state number is 0 and the frame pattern detection position numbers are 0, 1, 5, 6, and 7, the frame pattern could not be detected within the allowable range by hunting, so 0 is specified to stop hunting. Is read.

If the previous synchronization state number is 1, that is, if the detected position of the frame pattern is within the range of ± 1 bit when synchronized, the synchronization state number read out is 1 which means synchronization. , Out of ± 1 bit, 2 which means that the synchronization is about to be lost is output, and the synchronization protection unit enters the forward protection state.

If the previous sync state number is 2, that is, if the frame pattern can be detected within the range of ± 1 bit when the sync is about to be lost, 1 which means that the sync can be confirmed is read, and ± 1 When the frame pattern is not detected within the range of bits, it means that the synchronization is lost, and therefore 0 indicating hunting is read.

FIG. 5 shows the contents (part 2) of the synchronization state number storage memory. FIG. 5 shows the case where the frame pattern detection allowable error is ± 2 bits. The stored synchronization status number is the same as that in FIG. 4, and thus a duplicated description will be omitted. However, the point here is that the synchronization status number for the frame pattern detection permissible error can be written in the synchronization status number storage memory. is there. If it is desired to change the frame pattern detection permissible error, the synchronization protection number corresponding to the new detection permissible error can be realized by writing the sync state number corresponding to the detection permissible error into the synchronization state number storage memory. That is, it is possible to realize a flexible synchronization protection function against fluctuations in error factors of the frame pattern detection position. Similarly, when it is desired to change the protection condition, that is, the number of steps of the forward protection and the backward protection, by rewriting the number stored in the synchronization state number storage memory, it is possible to respond flexibly.

Further, the scale of the frame pattern detection unit in the conventional frame synchronization circuit and the frame pattern detection circuit in the frame synchronization circuit of the present invention, the OK counter, the NG counter of the synchronization protection unit in the conventional frame synchronization circuit, and the present invention. The scale of the synchronization state number storage memory of the synchronization protection unit in the frame synchronization circuit is almost the same. That is, the circuit required for the user in the conventional frame synchronization circuit is only required for a plurality of users in the frame synchronization circuit of the present invention. Therefore, the circuit scale can be reduced by the present invention.

In the above description, the condition of the synchronous protection is explained as the backward protection 1 stage and the forward protection 2 stages, but this is because the state transition diagram of FIG. 2 can be simply expressed.
The above restrictions have nothing to do with the essence of the present invention. That is, when the number of synchronization protection stages is larger, the method of determining the synchronization status numbers in FIGS. 4 and 5 is complicated, and the synchronization status number storage memory is used with the previous synchronization status number and the current frame detection position number as addresses. There is no difference in that the synchronization state number may be read out from and supplied to the synchronization state detection circuit of the user.

[0031]

As described above, according to the present invention, it is possible to flexibly deal with the fluctuation of the frame pattern detection error factor and the change of the synchronization protection condition, and the hardware scale can be reduced. A frame synchronization circuit for transmission is realized, and it is possible to improve the performance of a system to which TDMA multiplex transmission is applied and reduce the cost and reliability by reducing the circuit scale.

[Brief description of drawings]

FIG. 1 is an embodiment of the present invention.

FIG. 2 is a state transition diagram.

FIG. 3 is a frame pattern detection position number.

FIG. 4 shows the contents (1) of the synchronization status number storage memory.

FIG. 5 shows the contents (2) of the synchronization status number storage memory.

FIG. 6 is a conventional frame synchronization circuit.

FIG. 7 shows a structure of a burst frame (schematic diagram).

[Explanation of symbols]

 1 frame pattern detection unit 2 synchronization protection unit 3 burst frame counter 11 frame position prediction memory 12 frame position generation circuit 13 ± n window creation circuit 14 frame pattern detection circuit 21 synchronization state number storage memory 22 user synchronization state storage memory 23 synchronization state detection Circuit # 1 24 Synchronous state detecting circuit # 2 25 Synchronous state detecting circuit #m

Claims (1)

[Claims] 1. A frame synchronization circuit in TDMA multiplex transmission, comprising a frame position prediction memory (11) for storing a propagation time for each user, an output of the frame position prediction memory and an output of a burst frame counter (3). A frame position generating circuit (12) for determining a frame position predicted by the above, and a window of ± n (n is a positive integer) bits based on the frame position determined by the frame position generating circuit ±
an n window creating circuit (13) and a frame pattern detecting circuit (1) for detecting a frame pattern from data input within the window range of ± n bits.
4), and a synchronization state storage memory (21) for reading out the synchronization state number written in advance, using the number read from the output of the frame pattern detection circuit and the user synchronization state storage memory described later as an address, and all users. About the user, the user sync status storage memory (22) for storing the previous sync status number and reading the sync status number stored in the address of the user number, and the sync status number storage provided for each user. A synchronization state detection circuit (23, 2) supplied with the output of the memory
4, 25), and a frame synchronization circuit in TDMA multiplex transmission.