JPH0453328A - Multi-frame alignment circuit - Google Patents

Abstract

PURPOSE:To reduce a circuit scale by implementing multi-frame synchronization and multi-frame alignment with one RAM. CONSTITUTION:A multi-frame counter 15 in which reception input phase information written and read in/from a RAM (random access memory) 1 is detected and is active according to a phase difference with given output phase information reads a reception data from the RAM 1. Thus, a multi-frame synchronization memory and a multi-frame alignment memory are used in common. Thus, a small circuit scale is enough and the device cost is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-frame alignment circuit, and more particularly to a multi-frame alignment circuit in which the circuit scale is reduced.

[Conventional technology]

An example of a conventional multi-frame alignment circuit is shown in FIG. 6 and will be described.

FIG. 6 is a block diagram showing a multi-frame alignment circuit using a conventional multi-frame synchronization circuit disclosed in, for example, Japanese Unexamined Patent Publication No. 1-276839.

In the figure, reference numeral 1 denotes a random access memory (hereinafter referred to as RAM) for temporarily storing a data stream, and this RAM 1 has a capacity to store at least one multiframe worth of received data. 2 is a frame counter RAMI for RAMI that works at an arbitrary phase.
4 is a protection circuit that performs forward protection and backward protection; 5 is a reception phase 7 frame counter; 6 is a reception phase multiframe counter; 1 8 is a multi-frame alignment memory, 9 is a multi-frame counter for external phase addresses, and 10 is a switching circuit between a received phase address and an external phase address.

Next, the operation of the multi-frame alignment circuit shown in FIG. 6 will be explained with reference to FIG. 7.

FIG. 7 is a frame configuration diagram for explaining the operation of FIG. 6. Here, a case of 20 frames multi-frame will be explained.

The frame counter 5 shown in FIG. 6 is a 193-stage ring counter. Then, when 193 clocks are counted, a carried output that becomes a frame reference is generated. Furthermore, the multi-frame counter 6 is a 20-stage ring counter, and by counting 20 clocks in synchronization with the carrier output supplied from the frame counter 5, it generates a carrier output that is the standard of the multi-frame. do. That is, if you look at the frame counter 5 and multi-frame counter 6 together, there are 386
It can be regarded as a 0 (193×20) stage counter. Here, the configuration is such that the detection pulse a is output when the (193X19+1-)3668th count is detected using the output of the multi-frame counter 6.

When the synchronization is lost, a detection pulse a indicating that a count of 3668 has been detected is supplied to the gate 1 to prevent the frame counter 5 from counting up.

Therefore, the frame counter 5 continues to stop counting at the 3668th count.

Next, the data stream when entering the hunting operation is taken into an arbitrary address in RAM1. The data once taken into RAM1 is transferred to D19 shown in FIG. 7 by a data shift circuit (not shown).
→D18→...DO, the data is shifted one bit at a time to the LSB side of the input port of RAM1 and re-captured. That is, in addresses containing the synchronization pattern F bit, the synchronization pattern F bit is rotated within the same address.

Next, the comparator 3 that detects the received synchronization pattern constantly monitors the data output from RAM1, and detects the synchronization button included in the F bit or when the desired arrangement is reached. and outputs a synchronization pattern detection pulse b. Then, by supplying this synchronization pattern detection pulse b to gate 7, detection pulse a corresponding to the 3668 count that continues to be output from gate 1
- Temporarily prohibits transmission of. At this time, the frame counter 5 and the multi-frame counter 6 restart counting from the 3668th count. Here, the frame counter 5 and the multi-frame counter 6 start from exactly the first bit of the 20th frame.

Here, the synchronization pattern detection pulse b in the hunting state is also at the same position as the detection pulse a indicating 3668 counts. Therefore, the gate 7 does not output the count-up prohibition pulse.

Further, after the synchronization is pulled in, the output of the protection circuit 4 prevents the output of the count-up inhibit pulse from the gate 7.

That is, after correctly detecting the synchronization pattern, the frame counter 5 and multiframe counter 6 are always
It keeps counting up.

Then, it continues to operate in this state in synchronization with the first bit of the carrier output multiframe of the multiframe counter 6.

Therefore, since multiframe synchronization has been established for the data stream, the outputs of multiframe counters 6 and 7 frame counters 5 can be input as write addresses of multiframe alignment memory 8, and synchronized with the internal bus phase as read addresses. If the output of the multi-frame counter 9 is input and the input data is a data stream, a data stream synchronized with the multi-frame phase of the internal bus is obtained as the output.

Here, since the multi-frame synchronization circuit and the internal multi-frame phase are clock synchronized, it is possible to divide one clock cycle and write in the first half cycle and read out in the second half cycle. At this time, the multi-frame alignment memory 8 can be realized by a normal 1-board memory.

[Problem to be solved by the invention]

In the conventional multi-frame alignment circuit described above,
There was a problem in that it was necessary to prepare both a memory for the multi-frame synchronization circuit and a memory for multi-frame alignment, resulting in a large circuit scale.

The present invention has been made to solve such problems, and an object of the present invention is to provide a multi-frame alignment circuit that can perform multi-frame synchronization detection and multi-frame alignment using only one memory.

[Means to solve the problem]

The multi-frame alignment circuit according to the present invention receives data in which predetermined multi-frame synchronization patterns are distributed at regular intervals in a multi-frame consisting of a plurality of frames, and uses the synchronization patterns in this data to perform multi-point monitoring. A circuit that detects received input phase information and performs frame alignment and multi-frame alignment based on the detected information includes a random access memory having a capacity to store received data for at least one multiframe, and this random access memory. an input phase-synchronized multiframe counter that is driven by the output of the comparator to generate an input phase-synchronized multiframe pulse; A latch circuit that stores input/output phase difference information based on input phase synchronized multiframe pulses from a multiframe counter, and an output data address designating multiframe counter that operates according to the input/output phase difference information stored in this latch circuit. , an output phase-synchronized multi-frame counter, a switching circuit that switches between the output of the multi-frame counter for output data addressing and the output of the output phase-synchronized multi-frame counter, and an output from the random access memory that is 7-frame aligned. This includes a selection circuit that selects data that matches the multi-frame phase.

[Effect]

In this invention, by detecting the received input phase information that is being written to and read from the RAM, and reading the received data from the RAM using a multi-frame counter that operates according to the phase difference with the given output phase information, By performing multi-frame synchronization and multi-frame alignment with one RAM, the circuit scale can be reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a multi-frame alignment circuit according to the present invention.

In FIG. 1, the same reference numerals as in FIG.
It is configured to compare whether the data stored in the synchronization pattern matches the synchronization pattern. 12 is an output phase-synchronized multi-frame counter that operates with an externally given phase; 13 is an input phase-synchronized multi-frame counter that generates an input phase-synchronized multi-frame pulse by being driven by the output of the comparator 11; and 14 is this counter. A latch circuit that stores information on the phase difference between input and output using the input phase synchronization multiframe pulse from the input phase synchronization multiframe counter 13, and 15 is an output data address that operates according to the phase difference information between input and output stored in the latch circuit 14. A multi-frame counter for designation, 16 a switching circuit for switching between the output of the multi-frame counter 15 for output data address designation and the output of the output phase-synchronized multi-frame counter 12, and 17 for loading into the 7-frame counter 5 and the multi-frame counter 13; 18 is a selection circuit for switching between the previous multi-frame data and the current multi-7 frame data; 19 is a selection circuit for switching between the previous multi-frame data and the current multi-7 frame data; and 19 is a selection circuit for selecting data that has been synchronized with the frame and is in the desired multi-frame phase from the output parallel data, that is, appropriate multi-frame data. This selection circuit 19 is a selection circuit for selecting frame phase data, and is configured to select data that has been frame aligned and is in the output multi-frame phase from the output of the 7'c RAM 1.

FIG. 2 is a diagram showing the correspondence between memory addresses and multi-frame counters in the embodiment shown in FIG. 1, and FIG. 3 is a diagram showing memory input/output. Yes, 伽) is the operation clock φ2, (C) is the input data stream, (d) is the RAM 10 manual address, (e) is the read (READ)/write (WRITE).
) and (f) show data. Figure 4 is the first
FIG. 3 is a diagram showing the operation of the multi-frame counter 15 in the figure, in which (a) shows a multi-frame pulse;
1(b) is the output of the multi-frame counter 12, (C)
(d) shows the reception synchronization pattern detection pulse, (d) shows the 1-bit delay of reception synchronization pattern detection, (e) shows the output of the latch circuit 14, and (f) shows the output of the multi-frame counter 15. FIG. 5 is a diagram showing a reception synchronization pattern to be detected by the comparator 11 in FIG.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 2 to 5. Here, a case of 20 multiframes will be explained.

First, in FIG. 1, the multi-frame counter 12.
15 is composed of 20x193=3860 stages of ring counters, of which 12 multi-frame counters
The bit phase of matches the bit phase of the desired multiframe. The multi-frame counter 15 is a ring counter with 20×193=3860 stages that can operate at any bit phase.

The frame counter 5 is a 193-stage ring counter that takes an initial value of O when loaded, and generates a carrier when the value reaches 192. The multi-frame counter 13 is composed of a 20-stage ring counter, and when it counts 20 and the count enable becomes significant, it generates a carrier signal that becomes a reference for the multi-frame. That is, the frame counter 5 and the multi-frame counter 13 are combined to generate 193
The counter has X20=3860 stages.

The clock is the same for the input and output of the data stream, and there are 20×193=3860 multi-frame phases of the data stream. That is, there are also 3860 phase differences between the desired output multi-frame phase and the input multi-frame phase. In order to absorb this phase difference, RAM1 requires a capacity of 193 words x 20 bits - 3860 bits. FIG. 2 shows how this data is stored in the memory. The reason why one word is 20 bits is to simplify the operation of the comparator 11.

The write address of the data stream to RAM1 is determined by the multiframe counter 1 operating at the desired output phase.
This is performed using a data line representing θ to 192 of the frame counter output of No. 2. The selection circuit 18 selects the write bits of the boot stream from the multi-frame counter 12.
This is done by the data line representing 0 to 19 of the output of the multi-frame counter unit, and the data of the designated bit replaces new data. For the remaining nine data that were not specified, the read data is written as is. In this way, it operates as if it were a 3860 word x 1 bit memory. In this case, since it is a one-boat memory, reading and writing must be performed within the operating cycle. Therefore, as shown in Figure 3,
3/4 of the operating cycle is used to operate as if writing to an 860 word x 1 bit memory.

The 20-bit data read for the above operation is also output to the comparator 11. This comparator 11 temporarily holds the 20-bit data read out in the 1/4th cycle until the 1/4th cycle data read out in the next operating cycle. The data shown in FIG. 5 is compared with 20 sets of data in which the multi-frame synchronization pattern as shown in FIG. 5 is rotated. I do this all the time. Then, the carrier pulse A from the multiframe counter 13 is input to the comparator 11, and when the carrier pulse A and the comparison output pulse match, the carrier pulse A becomes significant. Output on time. Further, when the carried pulse A and the comparison output pulse do not match, the mismatch pulse D is outputted at the timing when the carried pulse A becomes significant.

Here, first, when the synchronization is lost and the hunting state is entered, the synchronization pattern detection pulse B from the comparator 11 passes through the gate 17, which is opened by the hunting state signal E, to the frame counter 5 and the multi-frame counter 13. Initially load the . Then, each clock counts up. If the synchronization pattern detection pulse B is absent for one multiframe after a certain synchronization pattern detection pulse is loaded, the multiframe counter 1
Carried pulse A is output from 3.

If the last loaded synchronization pattern detection pulse B is the result of real synchronization pattern detection, the carrier pulse A and the synchronization pattern detection pulse B should have the same timing at which they become significant. If they match, a matching pulse C is output to the protection circuit 4 at the timing when the carried pulse A becomes significant. Even if the last loaded carrier pulse A is based on a pseudo synchronization pattern, a carrier pulse A based on a real synchronization pattern is generated during one multiframe and the frame counter 5 is generated again. It should be loaded with the multi-frame counter 13.

When the coincidence pulse C is input to the protection circuit 4, the backward protection counter therein counts up from "0" to "1", and the hunting state signal E becomes insignificant. Then, the gate 1T closes in response to the synchronous slam detection pulse B and is no longer loaded. Then, the 7-frame counter 5 and the multi-frame counter 13 operate as ring counters. At the same time, the forward protection counter is reset. If the matching pulses continue as many times as the number of backward protection stages, the synchronization state signal F becomes significant. Of course, if the mismatch pulse D is input between the coincidence pulses and the coincidence pulses are input, the rear protection kakunta will be reset, and it goes without saying that the synchronization will be restored from the initial hunting state. .

Furthermore, when the current synchronization phase changes due to data slip etc., the timing at which the carried pulse A from the multi-frame counter 13 becomes significant does not coincide with the synchronization pattern detection pulse B, so the comparator 11 detects a mismatch. Pulse D is output. If this mismatch pulse D continues for the number of forward protection stages, the synchronization state signal F
becomes out of sync. Then, the hunting state signal E becomes significant under the AND condition of the out-of-synchronization state and the backward protection counter value of O, and therefore enters the hunting state. Then, the process returns to the synchronized state using the procedure described above.

Next, the ζ multi-frame alignment operation will be explained.

In the synchronized state, the phase in which the carrier cloud pulse A becomes significant is the beginning of the multi-frame phase in the data stream I, so the desired data stream output phase when this carrier cloud signal becomes significant is memorized. Then, when the desired data stream output phase becomes the first, the address of the next phase of the previously memorized output phase is set to RA.
If the data is read out by inputting it to M1, the data at the beginning of the desired multi-frame will be found among the data.

As shown in FIG. 4, the latch circuit 14 at the next timing after the carry-out pulse A becomes significant.
The phase of the 3860-stage multiframe counter 12 operating at the desired multiframe phase is latched. G is a frame pulse of an external output multi-frame. Next, the latched counter value is loaded into the multi-frame counter 15 at a desired multi-frame pulse timing.

Then, the switching circuit 16 selects the output of the multi-frame counter 12 for the first half period of the data frame period, and selects the output of the multi-frame color counter 12 for the second half period.
It operates to select the output of 5.

If this operation is performed, frame-aligned data will be output in the second half period. this"
Selecting ``1'' bit from among ``20'' bits of output data is a multi-frame alignment operation.

And this selection is the top of the multi-frame counter.
This is done by inputting the code "19" from rOJ represented by "5" bits to the selection circuit 19. It can be seen that the multi-frame synchronization operation and the multi-frame alignment operation are performed as described above.

In the above embodiment, the frame counter 5, the multi-frame counter 13, and the gate 17 perform υ multi-frame synchronization detection using the counter reset method, but these detect multi-frame synchronization using the counter 1-bit shift method. Detection may also be performed.

[Effects of the Invention] As explained above, the present invention includes 9. a multi-frame counter that detects the received input phase information being written to and read from the RAM and operates according to the phase difference with the given output phase information; By reading out the received My'-Y from the RAM, the multi-frame synchronization memory and the multi-7 frame alignment memory can be used together, so the circuit scale can be small and the device cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-frame alignment circuit according to the present invention, FIG. 2 is a diagram showing the correspondence between memory addresses and multi-frame counters in the embodiment shown in FIG. 1, and FIG. Diagram showing the input and output of
The figure shows the operation of the multi-frame counter 15 in Fig. 1, Fig. 5 shows the reception synchronization pattern to be detected by the comparator in Fig. 1, and Fig. 6 shows an example of the conventional multi-frame alignment circuit. The block diagram shown in FIG. 7 is a frame configuration diagram for explaining the operation of FIG. 6. i 11@Fist/RAM (7 random access memory), 1
1-... Comparator, 12, 13... Multi-frame counter, 14... Latch circuit, 15... Multi-frame counter, 16... Switching circuit, 17...
... game), 18.19... selection circuit.

Claims (1)

[Claims] Receive data in which a predetermined multi-frame synchronization pattern is distributed at regular intervals in a multi-frame consisting of a plurality of frames, detect received input phase information from the synchronization pattern in this data by a multi-point monitoring method, Based on the detected information, a circuit that performs frame alignment and multiframe alignment selects a random access memory that has a capacity to store at least one multiframe worth of received data, and a synchronization pattern that is being output from this random access memory. an input phase-locked multiframe counter that is driven by the output of the comparator to generate an input phase-locked multiframe pulse; and an input phase-locked multiframe counter that is driven by the output of the comparator to generate an input phase-locked multiframe pulse. A latch circuit that stores phase difference information between input and output using pulses, a multi-frame counter for specifying an output data address that operates according to the phase difference information between input and output stored in this latch circuit, and an output phase synchronized multi-frame counter. , a switching circuit that switches between the output of the multi-frame counter for output data addressing and the output of the output phase-synchronized multi-frame counter, and selecting data that matches the output multi-frame phase from the output of the frame-aligned random access memory. A multi-frame alignment circuit comprising: a selection circuit for selecting a frame;