JPH0734246B2 - Peak shift error detection circuit - Google Patents

Description

The present invention relates to a peak shift error detection circuit for a head for a magnetic disk device, and a peak shift error detection circuit for a head for a magnetic disk device, for the purpose of simplifying detection of a peak shift amount and facilitating judgment. A peak shift error detection circuit for detecting an error, which controls a head output waveform to a constant amplitude and then creates pulsed raw data. Equipped with an integrating circuit that divides each pulse for a certain period and calculates the peak shift amount from the difference between the charged voltages, and determines the quality of the peak shift by the quantitative value obtained by integrating about one round of the magnetic disk. To configure.

[Industrial application field]

The present invention relates to a peak shift error detection circuit for a magnetic disk device head.

In computer systems, magnetic disk devices are often used as external storage devices. The magnetic disk device is usually composed of a cylinder in which a plurality of magnetic disks are coaxially laminated, and information of each magnetic disk is written and read by a head provided for each magnetic disk.

In this case, a thin-film head having a small inductance and excellent high-frequency-high-density writing performance is used as the recording density becomes higher, but the thin-film head has a pole length (opposed to the medium of the head) compared to the conventional monolithic head due to its structure. It has a unique leakage magnetic field distribution because the ratio of the length of the part) to the gap length is extremely small. This affects recording and playback,
A phenomenon called a negative edge in which the edge of a solitary wave is depressed in the reproduced waveform and a peak shift as a phase shift are likely to occur. If this head has a large peak shift amount, a read error occurs due to the peak shift caused by the magnetic disk. Therefore, it is necessary to suppress the head shift amount to a certain amount or less.

[Conventional technology]

First, the cause of the peak shift caused by the thin film head will be described below.

5 (a), (b) and (c), (a) is an ideal flux pattern when a magnetic layer having a finite size is magnetized, and (b) is a magnetization pattern of actual write data, (C) is an output pattern read by the head. As shown in (b), the repulsive force that obstructs the magnetization always acts in the opposite direction as a demagnetizing action. This is because the magnetic fields of the N-pole and the S-pole appearing at both ends of the magnetized portion act in the magnetic layer in the direction opposite to the magnetization direction to cause magnetization reversal. As shown in (c), the reduction of the residual magnetization due to the demagnetization action causes not only the reduction of the reproduction output from the head but also the so-called peak shift that increases the phase shift of the output signal. As is apparent, the waveform of (c) is a composite waveform in which the waveform of (b) is added above and below, PS indicates the peak shift amount, AR indicates the amplitude decrease amount, and φ indicates the flux size. .

Normally, the peak shift amount of the head is evaluated by the waveform when the reference waveform recorded on the master magnetic disk is read by the head under test, but conventionally, this output waveform was visually checked using an oscilloscope or the like. It is observed and evaluated.

[Problems to be Solved by the Invention]

The peak shift of the read waveform by such a thin film head is particularly remarkable in a thin film head with a narrow gap applied to a medium recorded with high density, and conventionally, a circuit for detecting the peak shift amount is a magnetic disk. Although it exists, it is not related to the head, and the output waveform from the thin film head is visually observed and evaluated with an oscilloscope or the like as described above. However, if the output waveforms are individually observed and evaluated each time, it will take time and will not be applied to a mass production line. Further, since this output waveform is a read waveform from the medium, variations due to the medium also overlap, and it is not easy to evaluate the characteristics of individual heads by observing the individual output waveforms.

[Means for Solving the Problems]

The present invention is a peak shift error detection circuit for detecting a peak shift error of a head for a magnetic disk device,
A raw data creation circuit that creates pulsed raw data after controlling the output waveform of the head to a constant amplitude, and divides the raw data into a positive side and a negative side by a gate signal and charges each pulse for a fixed period to charge it. It is characterized in that an integrating circuit for obtaining a peak shift amount from the voltage difference is provided, and whether the peak shift is good or bad is judged by a quantitative value obtained by integrating about one round of the magnetic disk.

[Work]

After controlling the output waveform of the thin film head to a constant amplitude, pulse-shaped raw data is created, and the raw data is divided into positive and negative sides by a gate signal, and each pulse is charged for a certain period and the difference between the charged voltages is obtained. The peak shift amount is obtained by, the peak shift amount is integrated about one round of the magnetic disk, the integration result is A / D converted and detected as a quantitative value, and the quality of the peak shift is determined by the obtained quantitative value. . This makes it possible to eliminate the influence of the state of the surface of the magnetic disk in evaluating the peak shift of the thin film head, and to easily and accurately evaluate the performance.

〔Example〕

FIG. 1 is a basic configuration block diagram of a peak shift error detection circuit. H is a magnetic head, 11 is a reed switch, 12
Is a read amplifier, 13 is an AGC circuit, 14 is a filter, 15 is a low data creation circuit, 16 is a position gate creation circuit, 17
Is an error voltage generation circuit, 18 is an A / D conversion circuit, 19 is an addition circuit, and 20 is a shift register.

The output waveform RD read from the head is the reed switch
After being amplified by the read amplifier 12 via 11, the AGC circuit 13
The gain is automatically controlled to a constant amplitude with. AGC circuit 13
Is output to the raw data creation circuit 15 and the position gate creation circuit 16 through the filter 14, the raw data creation circuit 15 outputs pulsed raw data RAWDATA, and the position gate creation circuit 16 divides the raw data. The gate signal POSGT is output, and the signal GP resulting from the gate of these signals for the low data is input to the error voltage generation circuit 17. The error voltage generation circuit 17 converts the peak shift amount of each pulse of the raw data, that is, the shift amount into a voltage determined by the charge amount of the capacitor for a fixed period, and then integrates the voltage. The A / D conversion circuit 18 converts the integration result PSV into a digital value, which is added by the addition circuit 19 and then stored in the shift register 20. This stored data shows the measurement result TD of the quantitative value.

FIG. 2 is a circuit diagram of an essential part of one embodiment of the present invention, and particularly shows the circuits 15, 16 and 17 of FIG. 1 in detail. These circuits are collectively referred to as a peak shift integration circuit 21. In the peak shift integration circuit 21, 211 is a differentiating circuit, 212 is a comparator (CMP), 213 is a delay circuit (DL), 214 is an exclusive OR circuit (EXOR), 215 is a zero cross comparator (ZCMP), and 216 is an AND circuit. , 217 is a flip-flop circuit (FF), 218, 219 and 221 are differential amplifier circuits, and 220 is an arithmetic circuit. Further, PG is a positive side gate signal, MG is a negative side gate signal, S is a reset signal, RS is a reset signal, PP is a positive side pulse, and PM is a negative side pulse.

The read signal whose level is constant by the AGC circuit 13 is differentiated by the differentiating circuit 211, then pulsed by the comparator 212, pulsed by the comparator 212, and input to the exclusive OR circuit (EXOR) 214. It The EXOR 214 also takes in the output from the delay circuit 213 and creates raw data from them. Further, the raw data RAWDATA, the positive-side gate signal PG and the negative-side gate signal MG from the zero-cross comparator 215 are input to the AND gate 216, and the matching of these signals is taken by each AND gate 216, and each AND gate 216.
The flip-flop 217 operates by the set signal S and the reset signal RS from the gate, and the positive side pulse PP and the negative side pulse P
Get M.

The zero cross comparator 215 divides the output of the AGC circuit into a positive side gate signal PG and a negative side gate signal MG to create a gate signal. These signals PG and MG are position gate signals
It is input to each AND gate 216 as POSGT. As a result, the gate at the peak interval T1 and the gate at the peak interval T2 of the read waveform RD are gated.

The peak shift integration circuit 21 switches the positive side pulse PP and the negative side pulse PM output from the flip-flop 217.
Switch with SW1 and SW2 and charge with each operational amplifier. In this embodiment, one measurement is raw data RAWDAT
Since it is 256 pulses of A, the capacitor is charged for 256 pulses. The variable volume of the operational amplifier 219 is for adjustment to make it equal to the charge speed of the operational amplifier 218.

In such a configuration, the basic operation is as follows.

The signal for which the peak shift amount is measured is F1 (3.28MH
It is the read waveform RD of z). Two consecutive peak intervals T1 and T2 of the read waveform shown in the figure are measured, and the average value of one round of the magnetic disk is determined as the measurement result. The peak shift is the absolute value | T1-T2 | of the difference between T1 and T2.

In this circuit, raw data RAWDATA is created from the read waveform RD and pulsed by the differentiating circuit 211.
TA is obtained, and the shift amount (peak shift amount) of each RAW DATA pulse is converted into a voltage and integrated, and then A / D converted to obtain a measurement result as a quantitative value. In this case, since the unit of the peak shift amount is time, it is converted into voltage at a ratio of 10 nsec / v. A / D
8bit converter is used and the reference voltage is 5v
Input with 2.5v offset applied. That is, it is possible to measure up to ± 25 ns. Since it is 5v / 256bit, it is 0.02v / bit, that is, 0.2ms / bit.

As described above, in FIG. 1 and FIG. 2, the read signal RD puffed by the read amplifier 12 is controlled to a constant amplitude level by the AGC circuit 13, passes through the filter 14, and becomes the raw data RAWD.
ATA and gate signal POSGT are created. RAWDATA is gated by POSGT to be on the positive side and the negative side, and as a result, it is input to the error voltage generation circuit as a gated pulse.

In the error voltage generation circuit 17, the phase shift of the gated pulse, that is, the peak shift amount is set to 25 as a unit of measurement.
A / D conversion is performed after charging 6 pulses (cycle).
This sequence can be repeated 2n times by software, and the measured value for each time is added by the adder circuit 19. Then, after the measurement of 2n times is completed, the addition result is downshifted n times from the shift register 20 to obtain an average value. This result is read by a computer and the read voltage is converted into time for evaluation (judgement).

In the present embodiment, the measurement is performed 16 times while the magnetic disk makes one revolution, and the average value of 16 times is the measurement result by the adder circuit and the shift register. Since the characteristic of the error voltage generating circuit is greatly influenced by the characteristic of the internal capacitor, it is necessary to use the one having excellent characteristics such as temperature change and aging change.

FIGS. 3 and 4 are signal time charts at respective points in FIGS. 1 and 2.

In FIG. 3, the solid line of the read waveform is the ideal waveform,
The dotted line is the shifted waveform. Read waveform as described above
Raw data RAW DATA is a pulsed version of RD. The peak shift of the read waveform RD is a shift between the peak intervals T1 and T2 caused by the use of a thin film head as the recording density on the magnetic disk becomes high and factors such as the material of the surface of the magnetic disk. Therefore, the peak shift is raw data.
It is also a shift of RAW DATA, and as mentioned above, this T1 and T2
The absolute value of the difference | T1−T2 | is the peak shift amount.

The position gate signal POSGT is, as described above, this RAW
The zero cross comparator 215 divides DATA into a positive side gate signal PG and a negative side gate signal MG to create a gate signal. These signals PG and MG are input to each AND gate 216. As a result, the gate of the T1 portion and the gate of the T2 portion are performed.

The positive side pulse PP and the negative side pulse PM output from the flip-flop 217 are switched by the switches SW1 and SW2 and charged by the respective operational amplifiers. In this embodiment, since one measurement is 256 pulses of raw data RAWDATA, 256
Charge for the pulse. The variable volume of the operational amplifier 219 is for adjustment to make it equal to the charge speed of the operational amplifier 218.

If the pulse widths of T1 and T2 are equal, the charge amounts are naturally equal, and the sum of the charge amounts becomes zero. On the other hand, if either pulse width is wide, the difference in charge amount appears on the positive side or the negative side. Since this difference in charge amount is the difference in voltage, the shift amount can be determined from this voltage difference. In addition, TEDGE is a rising edge pulse of T1 of RAWDATA, and REDGE is a rising edge pulse of T2 of RAWDATA. The pulse TEDGE is inverted G as indicated by the arrow in the figure.
P rises and pulse REDGE rises pulse GP.

FIG. 4 is a diagram for explaining integration in the error detection circuit. As described above, when the capacitor is charged with the gate pulse GP for a certain period, the waveform thereof becomes V volt by gradually increasing the voltage of the capacitor like PSV. A peak shift amount can be obtained by calculating and comparing this voltage on the positive side and the negative side.

〔The invention's effect〕

As described above, according to the present invention, it is possible to detect the peak shift of the head for the magnetic disk device, shorten the evaluation time, and average, and reduce the variation error due to the medium or the like, and easily determine the quality by the quantitative value. Become.

[Brief description of drawings]

1 is a block diagram of the basic configuration of the present invention, FIG. 2 is a block diagram of the essential parts of an embodiment of the present invention, FIG. 3 is a signal time chart of the present invention, and FIG. FIG. 5 is a diagram for explaining the integration of the peak shift amount, and FIG. 5 is a diagram for explaining the peak shift. (Explanation of symbols) 11 …… Reed switch, 12 …… Reed amplifier, 13 …… AGC circuit, 14 …… Filter, 15 …… Low data creation circuit, 16 …… Position gate creation circuit, 17 …… Error voltage creation Circuit, 18 ... A / D conversion circuit, 19 ... adding circuit, 20 ... shift register, 21 ... peak shift integrating circuit.

Claims (1)

[Claims] 1. A peak shift error detection circuit for detecting a peak shift error of a head for a magnetic disk device, the raw data creation circuit for creating pulsed raw data after controlling an output waveform of the head to a constant amplitude. The raw data is divided into a positive side and a negative side by a gate signal and charged for a fixed period of each pulse, and a peak shift amount is obtained by a difference between the charged voltages. A peak shift error detection circuit that determines the quality of peak shift based on the obtained quantitative value.