JPH0736268B2 - Memory board identification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A method for identifying mounted memory boards in a system in which memory can be added in units of memory boards such as computers, and is required to identify mounted / unmounted type of memory boards. For the purpose of reducing the number of signal lines for various interfaces, a memory board identification signal line pulled up on the main unit side is provided between the main unit and the mounted memory board via the above connector. Information indicating the type is set on the memory board by coupling the RAS signal supplied from the main unit to the memory board identification signal line, or by grounding the memory board identification signal line instead of coupling the RAS signal. However, the main unit sends the RAS signal to the above connector at the time of refreshing the dynamic memory, and at the same time, on the memory board identification signal line. Read the items, by the signal state,
It has a configuration that identifies whether or not a memory board is mounted and the type of the mounted memory board.

[Industrial application field]

The present invention relates to a method of identifying mounted memory boards in a system capable of adding memory in units of memory boards such as computers.

When there are multiple types of expandable memory boards with different memory capacities and access methods, the system identifies whether or not the memory board is installed, and if so, identifies the type and implements the corresponding access control. There is a need to do.

The present invention enables the presence / absence of the mounting of the memory board and the identification of the type of the memory board with a small number of interface signal lines.

[Conventional technology]

FIG. 4 is an explanatory diagram of a conventional method for identifying a memory board.

In FIG. 4, reference numeral 24 is a memory control circuit provided in the main unit such as a computer. 25 to 26 are connectors for inserting and inserting a memory board, which are connected to a bus for adding memory. 28, 30, 32 are signal lines for identifying the type of memory board (hereinafter referred to as type). Reference numerals 29, 31, and 33 are signal lines for identifying whether or not the memory board is mounted. 34 to 39 are pull-up resistors for pulling up the signal lines 28 to 33 to H level (logic "1" level) respectively. Reference numerals 40 and 41 denote type 1 and type 2 memory boards mounted and mounted on the connectors 25 and 26, respectively.

MiD ₀ , MiD ₁ and MiD ₂ (typically represented by MiDn) are memory board type identification signals on signal lines 28, 30 and 32, respectively, and SRPLY ₀ , SRPLY ₁ and SRPLY ₂ (typically SRPLYn Represents the mounting identification signals on the signal lines 29, 31, and 33, respectively.

Correspondence between the H and L levels of the MiDn signal and the type is determined in advance as follows.

Correspondence between the H and L levels of the SRPLYn signal and the mounting state is determined in advance as follows.

The H level of VCC is applied to the signal lines 28 to 33 by pull-up resistors 34 to 39, respectively.

However, if any of these signal lines 28 to 33 is grounded in the memory board, that signal line is lowered to the L level.

The memory board to be mounted uses this to set each signal of MiDn and SRPLYn to the corresponding level according to each type, and to the memory control circuit 24 of the main unit,
The presence and type of the mounted memory board can be identified.

For example, in the case of the memory board 40 of the connector 25 shown in the figure, the signal lines 28 and 29 are both grounded (GND), so that MiD ₀ = L, SRPLY ₀ = L and the type 1 memory board is Show that it is implemented.

In the case of memory board 41 with connector 26, signal line 30
Is open (OPEN), the signal line 31 is grounded (GND),
Therefore, MiD ₁ = H and SRPLY ₁ = L, indicating that the type 2 memory board is mounted.

Then, at the connector 27, since both the signal lines 32 and 33 are opened, MiD ₂ = H and SRPLY ₂ = H are displayed, indicating that the memory board is not mounted.

In this way, there are two types of memory boards, type 1 and type 2. Therefore, in a system where it is necessary to distinguish the type of mounted memory board from the mounted / not mounted type, two dedicated signal lines are used. Signal state detection is performed for
According to the result, the memory control is executed.

When there are three or more types of memory boards, it is necessary to increase the number of type identifying signal lines for each connector.

[Problems to be Solved by the Invention]

In the conventional memory board identification method, a separate dedicated signal line is provided in the interface between the main unit and the memory board in order to identify the type of memory board and whether it is mounted or not, for each connector for adding a memory board. Had to be provided.

It is an object of the present invention to reduce the number of interface signal lines necessary for distinguishing whether a memory board is mounted or not mounted and its type.

[Means for Solving the Problems]

The present invention uses a RAS signal sent from a main unit to a memory board at the time of refresh in a system using a memory board equipped with a dynamic memory to determine whether the memory board is mounted / not mounted and the type of the memory board. Create a signal in the memory board that can identify
It is made readable by the main unit. This eliminates the need for separate dedicated signal lines to distinguish between mounted and unmounted types of memory boards, and in the simplest case where there are only two types of memory boards, one memory board identification signal for each connector. The memory board can be identified simply by providing a line.

FIG. 1 shows the principle of the present invention.

In FIG. 1, reference numeral 1 denotes a main unit such as a computer, which has a function of performing access control and refresh control of a memory and a function of discriminating between mounted / unmounted and a type of a memory board for an extended memory.

Reference numerals 2 to 4 are connectors for inserting a memory board, and connect signal lines between the additional memory bus (not shown) of the main unit 1 and the memory board.

Reference numerals 5, 7 and 9 are RAS signal lines, which supply RAS signals RAS ₀ , RAS ₁ and RAS ₂ to the memory board via connectors 2, 3 and 4 at the time of access and refresh. The other memory control signals are not shown because they are not directly related to the present invention.

6,8,10 are the memory board identification signal lines, and the connector 2,
Transfer the memory board identification signal from the memory board via 3 and 4.

Reference numerals 11, 12 and 13 are pull-up resistors for pulling up the memory board identification signal lines 6, 8 and 10 to H level, respectively.

Reference numerals 14 and 15 denote memory boards inserted into the connectors 2 and 3, respectively. In the illustrated example, the type of the memory board 14 is a type.
1, the type of memory board 15 is type 2.

16 is the ground (GND) for the memory board identification signal line 6
It is a connection and specifies the memory board identification signal in the type 1 memory board.

Reference numeral 17 is a loop connection that connects the RAS signal line 7 and the memory board identification signal line 8 and defines the memory board identification signal in the type 2 memory board.

The signal waveforms on the right side of FIG. 1 are for the signals on the signal lines 5 to 10, and (5,7,9) is the RAS signal RASn (n supplied to the RAS signal lines 5,7,9, respectively. = 0,1,2),
Reference numerals (6), (8), and (10) denote memory board identifications RPLY ₀ , RPLY ₁ , and RPLY ₂ on the memory board identification signal lines 6, 8 and 10, respectively.

[Action]

In FIG. 1, the main body device 1 performs refresh control on the memory boards of the connectors 2, 3, and 4 at a predetermined timing. For example, for a RAS only refresh type dynamic memory element, refresh is performed only by controlling the row address and the RAS signal.

As a result, when refreshing, each memory board 14,15
Receives RAS signals RAS ₀ and RAS ₁ , respectively. However, in the case of the memory board 14, since the RAS signal RAS ₀ is not coupled to the memory board identification signal line 6 and the signal line 6 is grounded, the memory board identification signal RPLY ₀ is held at the L level.

In the case of the memory board 15, since the RAS signal RAS ₁ is transferred to the memory board identification signal line 8, the memory board identification signal RPLY ₁ coincides with RAS ₁ .

In the case of the connector 4 in which the memory board is not mounted, the memory board identification signal RPLY ₂ is the pull-up resistor 1
It is held at H level by 3.

At the time of refreshing, the main body device 1 has the timing t ₀ immediately before the transmission of the RAS signal RASn and the central timing t ₁ at the H level of RASn at each of the memory board identification signals RPLY ₀ , RPLY ₁ , RP.
The level of LY ₂ is read, and the combination of the levels is used to identify the mounted / not mounted memory board and the type of memory board.

In the example of FIG. 1, the following determination is made according to the level H / L at the timings t ₀ and t ₁ .

[Embodiment] The details of the present invention will be described with reference to an embodiment shown in FIGS. 2 and 3.

FIG. 2 is a block diagram of an embodiment of the memory control circuit in the main unit, and FIG. 3 is a signal timing chart thereof.

In FIG. 2, reference numeral 18 denotes a refresh control circuit, which is a refresh timing signal shown in FIGS. 3 (a) and 3 (b).
The refresh control signal RFSH shown in FIG. 3 (c) is generated in response to either RFTiM or the power-up signal PRDY.

Reference numeral 19 denotes a memory timing control circuit, which is used for accessing the RAS timing signal TRAS, CAS timing signal TCAS,
The write enable signal TWE is generated, but when the refresh control signal RFSH is input, it is shown in Fig. 3 (e).
Generates RAS timing signal TRAS.

Reference numeral 20 denotes a memory ID control circuit, which sets the timing for identifying the ID (type) of the memory board when the power-up signal PRDY and the refresh control signal RFSH are simultaneously input, and is shown in FIG. 3 (d). Memory ID set signal IDSET
Is output.

Reference numeral 21 is an AND gate, which takes AND logic with IDSET and TRAS as inputs and outputs only TRAS generated during the IDSET period.

22 and 23 are flip-flops, and AND gates respectively
At each rising timing of the output signal of 21 and its inverted signal, the memory board identification signal RPLY of FIG.
Two values of n are sampled and each is held.

The status output of the flip-flop 22 is a signal MiDn (H level =
Type 2, L level = type 1), and similarly, the status output of the flip-flop 23 becomes the signal SRPY indicating whether the memory board is mounted or not mounted.

In the circuit of this embodiment, the memory board is identified only when the system is started up by turning on the power, and the identification result is used during the subsequent system operation.

〔The invention's effect〕

According to the present invention, if there are two types of memory boards to be added, it is sufficient to prepare only one memory board identification signal, which can be halved compared to the conventional case where two memory boards were required. it can.

Therefore, the number of terminals of the connector and the number of wires of the cable that connect the main unit and the memory board can be reduced, and the wiring in the memory board can be simplified.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of a memory control circuit according to the present invention, FIG. 3 is a signal timing diagram of the embodiment circuit shown in FIG. 2, and FIG. FIG. In Fig. 1, 1: Main unit 2-4: Connector 5,7,9: RAS signal line 6,8,10: Memory board identification signal line 11-13: Pull-up resistor 14,15: Memory board

Claims (1)

[Claims] 1. One of a plurality of types of memory boats (14,15) equipped with a dynamic memory is inserted into a common connector (2,3,4) connected to an extension memory bus of a main unit (1). In a system that can be mounted arbitrarily by wearing the main unit (1) and mounted memory boards (14, 15)
And the memory board identification signal line (6,8,10) pulled up on the main unit (1) side between the above connector (2,3,4)
The RAS signal supplied from the main unit (1) is provided to each memory board (14, 15) via the memory board identification signal line (6, 8, 1).
0) or, instead of connecting the RAS signal, ground the memory board identification signal line to set the information indicating the type, and the main unit (1) uses the above connector (2) when refreshing the dynamic memory. , 3,4) at the same time when the RAS signal is sent to the memory board identification signal line (6,8,10) at the L level and H level of the waveform of the RAS signal Depending on the combination of signal states,
A method for identifying a memory board, which comprises identifying whether or not a memory board is mounted and the type of the mounted memory board.