JPH0736548B2 - Spread spectrum receiver - Google Patents

Description

The present invention relates to a receiver used in spread spectrum communication (hereinafter abbreviated as SSC in the present specification).

[Outline of the Invention] Received pseudo noise (hereinafter abbreviated as PN in the present specification) code included in a received signal and a reference PN generated at the receiving side
A correlator that takes a correlation with a code is provided, and a sampling pulse is generated before and after the correlation pulse generated from the correlation spike output from the correlator, thereby sampling the correlation pulse and its deviation direction. And the amount of deviation and detect the reference PN by the corresponding phase control pulse.
In the SSC receiver that controls the phase of the code to maintain the synchronization of both codes, a means for counting the number of detections of the deviation direction and the deviation amount, and when the difference between the count values reaches a predetermined value. An SSC receiver comprising means for changing the phase control amount of the phase control pulse.

[Prior Art] As a conventional method, there is Japanese Patent Application No. 62-283056 filed by the applicant on November 11, 1987.

In the above method, a correlator that takes a correlation between the received PN code included in the received signal and the reference PN code generated on the receiving side is provided,
A sampling pulse is generated before and after the correlation pulse generated from the correlation spike output from the correlator, the correlation pulse is sampled by this, the deviation direction and the deviation amount are detected, and the corresponding deviation is detected. The phase of the reference PN code is controlled by the phase control pulse to carry out the synchronization holding operation for both codes.

[Problems to be Solved by the Invention] However, when the error of the code clock frequencies of both codes is significant, the phase control amount of the phase control pulse corresponding to the detection of the deviation direction and the deviation amount by both sampling pulses becomes unsuitable, There is a problem that the normal synchronization holding operation is not performed.

[Object of the Invention] An object of the present invention is to provide an SSC receiver capable of performing a normal synchronization holding operation even when the error in the code clock frequencies of both codes is significant.

[Means for Solving the Problems] In order to achieve the above object, the present invention includes a correlator that correlates a received PN code included in a received signal with a reference PN code generated on the receiving side, Sampling pulses are generated at timings temporally before and after the correlation pulse generated from the correlation spike output from the correlator, and a shift signal indicating the shift direction and shift amount based on the correlation pulse and the sampling pulse is generated. The spread spectrum receiver that detects and outputs the shift signal is provided with phase control means for controlling the phase of the reference PN code by the phase control pulse corresponding to this shift signal, and holds the synchronization of both codes. And counting means for changing the phase control amount of the PN code for the phase control pulse of the phase control means based on the counting means. To.

[Operation] The number of times of detecting the deviation direction and the deviation amount of the correlation pulse is counted, and the phase control amount of the phase control pulse is changed when the difference between the count values reaches a predetermined value.

[Examples] Hereinafter, the present invention will be described in more detail using examples with reference to the drawings. However, these are merely examples, and various modifications and improvements can be made without departing from the scope of the present invention. Of course it is possible.

FIG. 1 is an embodiment of an SSC receiver according to the present invention, in which 1 is a correlator, 2 is a binarization circuit, 3 is a first matched filter, 4 is an up / down counter, 5 is a reference PN code generator, 6 is a sampling pulse and window pulse generator, 7 is a digital phase locked loop circuit, 8 is a PN code phase control pulse generation circuit, 9 is a demodulation circuit, 10 is a second matched filter, 41 is a comparison circuit, and 42 is an external circuit. Is.

In FIG. 1, the binarization circuit 2 changes its polarity to the positive side and the negative side from the correlation spike (d) that appears when the received PN code and the reference PN code (h) match in the correlator 1 and in the vicinity thereof. The separated correlation pulse (e) is generated. First
The matched filter 3 outputs a pulse (f) (initial synchronization detection signal) when the pattern of the correlation pulse (e) output from the binarization circuit 2 matches a predetermined determination pattern.

The up-down counter 4 is initialized by the strobe pulse (re) output from the reference PN code generator 5 and performs up-counting from the offset value (a) set by the external circuit 42 such as a microprocessor. When the pulse (f) is output from the matched filter 3 of 1,
This triggers the counter to down-count and generate a borrow pulse (g).

The reference PN code generator 5 is a reference PN set from the external circuit 42.
Based on the initial information (C) of the code, the reference PN code (H) and the strobe pulse (L) indicating the head bit thereof are output.

The sampling and window pulse generator 6 outputs a sampling pulse (nu) and a window pulse (le) for sampling and extracting the correlation pulse (e) output from the binarization circuit 2. The digital phase-locked loop circuit 7 receives the received PN code included in the received signal (b) input to the correlator 1 and the reference included in the reference signal.
Holds the PN code (h) in synchronism.

The PN code phase control pulse generation circuit 8 is triggered by the pulses (g) and (g) output from the up / down counter 4 and the digital phase locked loop 7 to generate a reference signal.
The phase control pulse (Y) of the PN code (H) is output. The demodulation circuit 9 outputs the correlation pulse (e) output from the binarization circuit 2.
Also, the sampling and demodulation to binary data is performed by the window pulse output from the window pulse generator 6. The second matched filter 10 outputs a pulse (re) when the binary data (ta) output from the demodulation circuit 9 matches a predetermined pattern.

The above circuits are triggered by the reception operation start pulse output from the external circuit 42 and start their respective operations.

Next, the operation of the above-described embodiment of the present invention will be described in more detail. To facilitate the explanation, one period of the PN code and the data bit length are equal, and the integration interval by the correlator 1 and the PN An example will be taken in the case where the code 1 cycle is the same.

When the reception operation start pulse is output from the external circuit 42, the reference PN code generator 5 determines the reference PN included in the reference signal based on the initial information (C) of the PN code set by the external circuit 42.
A code (h) is given to the correlator 1. SSC signal is received,
When the received PN code included in the received signal (b) and the reference PN code (h) match, the correlator 1 causes a correlation spike (d).
Is output to the binarization circuit 2. The binarization circuit 2 separates the correlation spike (d) into a positive side and a negative side as shown in FIG.
A correlation pulse (e) is generated and given to the first matched filter 3, the digital phase lock loop 7 and the demodulation circuit 9.

As described above, in the correlator 1, it is not known at which position the two PN codes match, and if the matching positions of both codes are not set correctly, the received data cannot be demodulated correctly. For example, when the two codes coincide with each other in the form as shown in FIG. 12 (a), the data bit A is on half of the received code and the data bit B is on the other half. The drawing shows the array of data bits, the received PN code and the reference PN code from the top, and the area indicated by L represents the integration section in which the correlation operation is performed by the correlator 1.
The PN code is a time-reversed version of the PN code A.

As described above, no matter which position the received code and the reference code initially match, it is necessary to perform the initial synchronization so that they eventually match at the position as shown in FIG. 12 (b). In the invention, this initial synchronization operation is performed as follows.

The transmitted data is composed of preamble data and information data as shown in FIG. 10 (a).

As shown in FIG. 10 (b), the transmitted data has a predetermined pattern for initial synchronization (pattern for initial synchronization).
And the correlation pulse (e) output from the binarization circuit 2 is input to the first matched filter 3. The first matched filter 3 outputs a pulse (f) to the up / down counter 4 when the pattern of the correlation pulse (e) matches the set predetermined pattern.

The up / down counter 4 keeps the reference until the pulse (f) is output from the first matched filter 3 as shown in FIG.
Initialized by a strobe pulse (i) indicating the first bit of the reference PN code (h) output from the PN code generator 5, the up-counting is repeated from the offset value (a) set by the external circuit 42. When the pulse (f) is output from the first matched filter 3, the up / down counter 4
Switches from up-counting to down-counting at the timing of the pulse, and when the count value of the counter 4 becomes 0, outputs a borrow pulse (g) to the PN code phase control pulse generating circuit 8.

The PN code phase control pulse generation circuit 8 is triggered by the borrow pulse (G) to send the phase control pulse (Y) of the reference PN code (H) to the reference PN code generator 5, sampling pulse and window pulse generator 6 and digital phase. Output to lock loop circuit.

Through the series of operations described above, the received PN code and the reference PN code (h) match.

FIG. 4, FIG. 5 and FIG. 6 show a configuration example of the first matched filter 3.

In FIG. 4, 11 is a shift register, 12 is a pulse counter, and 13 is a comparator.

As shown in FIG. 5, the shift register 11 has a plurality of shift registers SR _{1 to} SRn connected in series, each driven by a code clock, and an output terminal is set for each fixed length. Is output to the pulse counter 12.

The pulse counter 12 counts the total number of pulses output from each shift register in parallel, converts the count into binary data, and outputs the binary data to the comparator 13. This pulse counter 12
Is composed of a plurality of half adders 14 and full adders 15 as shown in FIG.

The parallel outputs of the shift registers are input to each half adder 14 as a set of two, and half addition is performed. The resulting addition output is the 2 ⁰ place and carry output is converted into binary data by allocating the 2 ^first.

Further, each converted into binary data is input to the full adder 15 and added. In this way, the total number of pulses output from the shift register 11 in parallel is converted into binary data.

The comparator 13 compares the binary data output from the pulse counter 12 with the threshold value set by the external circuit 42, and outputs a pulse when the binary data reaches the threshold value.

In the first matched filter 3 having the above-described configuration, for example, when all the data patterns for initial synchronization transmitted are "1", a positive correlation spike occurs. That is, the positive correlation spike occurs at a half cycle of the time (hereinafter referred to as delay time) T corresponding to the integration section of the correlator 1, and the negative correlation spike does not occur. Therefore, the binarization circuit 2 generates a positive correlation pulse in the same cycle as the correlation spike, but does not generate a negative correlation pulse.

This correlation pulse is input to the shift register 11, which has a delay time T as shown in FIG.
The output terminal is set for each 1/2. Therefore, if the signal is normally received, the pulse is increased in parallel from the shift register 11 every 1/2 of the delay time T, and is output in parallel, and is converted into binary data by the pulse counter 12 as described above. Then, when the comparator 13 reaches the threshold value set by the external circuit 42, the comparator 13 outputs a pulse.

According to the above-described configuration of the first matched filter 3, even if the output of the correlator 1 is abnormal due to noise or the like, it is possible to match only the normal correlation pulse.

It should be noted that a plurality of shift registers forming the shift register 11
The intervals of the output terminals set in SR _{1 to} SRn are modified according to the pattern of the data for initial synchronization to be transmitted.

7 and 8 show a configuration example of the second matched filter 10. In FIG. 7, 21 is a shift register, 22 is a pulse counter, and 23 is a comparator.

As shown in FIG. 8, the shift register 21 is composed of a plurality of shift registers SR ₁ ′ to SRn ′ connected in series, and is driven by a clock having a cycle equal to the length of one data bit. Has the output terminal set.

Demodulated data is input to the shift register 21, and when the demodulated data matches the pattern set to detect the start timing of the information data included in the preamble data as shown in FIG. 10 (b), An inverter INV is appropriately connected to the output of each shift register so that pulses are output from all the shift registers SR ₁ ′ to SRn ′, and the output of each shift register is output to the pulse counter 22. Is output.

The pulse counter 22 and the comparator 23 are configured in the same manner as described above, and the pulse counter 22 counts the total number of pulses output from the shift register 21 and converts it into binary data. Output. The comparator 23 compares the binary data with a threshold value set by the external circuit 42, and outputs a pulse when the binary data reaches the threshold value.

Now, the initial synchronization is established as described above, and a predetermined arrangement relationship between both codes is established.

However, if there is an error in the code clock frequency between the two codes, the position where the two codes match gradually shifts from the above arrangement relationship. That is, even if the initial synchronization is established, if the code clock frequencies between the two codes are different, the position where the two codes match gradually deviates from the normal position.

Therefore, in the present invention, the following measures are taken so as to correct the above-mentioned shift, that is, the phase error and hold the synchronization.

Reference PN output from the PN code phase control pulse generation circuit 8
The sampling pulse and window pulse generator 6 and the digital phase-locked loop circuit 7 are initialized by the phase control pulse (Y) of reference numeral (H).

As shown in FIG. 9, the circuit 6 generates sampling pulses S ₁ and S ₂ before and after the correlation pulse (e) obtained in a normal positional relationship, and outputs it to the circuit 7. The circuit 7 constantly samples the correlation pulse (e) with the sampling pulses S ₁ and S ₂ , and monitors the shift direction of the correlation pulse.

The circuit 7 counts the number of times each time sampling is performed by an internal counter, and if there is a difference in the number of sampling times by both sampling pulses, the amount of deviation of advance or delay when the difference reaches a predetermined value is calculated. The indicated pulse (wo) is output to the circuit 8.

The circuit 8 is triggered by the pulse (2), and outputs the phase control pulse of the reference PN code (h) corresponding to the deviation detection amount of the correlation pulse due to both sampling pulses to the reference PN code generator 5.
To control the phase. As a result, the phase error between both codes is corrected and the synchronization can be maintained.

However, when the error in the code clock frequency between the two codes is significant, the limit of the phase control amount of the phase control pulse of the reference PN code (h) corresponding to the shift detection amount by the both sampling pulses is exceeded, and normal synchronization is maintained. There is a possibility that the operation cannot be performed.

The synchronization holding operation in the above case will be described below based on the normal temporal relationship between the correlation pulse (e) and the sampling pulse (nu) (A in FIG. 3).
On the other hand, the positional relationship (B in FIG. 3) in which the correlation pulse (e) is shifted forward in time will be described as an example.

The comparator circuit 41 counts the number of times the pulse (wo) indicating the amount of deviation between the lead and the delay output from the digital phase lock loop circuit 7 is counted, the number of outputs is increased in the lead direction, and the count value is set from the external circuit 42. When the threshold value is reached, a leading tendency detection pulse (SO) is output to the external circuit 42 as a deviation direction detection pulse. The external circuit 42 changes the phase control amount (T) of the phase control pulse (Y) corresponding to the lead tendency detection pulse (SO) output from the comparison circuit 41 from the initially set 1 chip to 2 chips.

That is, the amount of phase controlled by the phase control pulse (Y) of the reference PN code changes from 1 chip to 2 chips as shown in C and D of FIG.

In this way, the phase control amount of the reference PN code is changed and the synchronization is stably maintained by detecting the tendency of the correlation pulse (e) with respect to the sampling pulse (e) in the direction of advance or delay.

FIG. 11 shows a configuration example of the comparison circuit 41.

In FIG. 11, 31 and 32 are counters, and 33 and 34 are comparators. The counters 31 and 32 are supplied with a pulse (wo) indicating the amount of advance or delay deviation output from the digital phase lock loop circuit 7. Then, the count values are output from the counters 31 and 32 to the comparators 33 and 34. When the count values output from the counters 31 and 32 reach the threshold value set by the external circuit 42, the comparators 33 and 34 output the lead and lag tendency detection pulses to the external circuit 42 as deviation direction detection pulses, and the counters 31 and 32 return to the initial values.

By performing the initial synchronization of the received PN code and the reference PN code in the correlator 1 and holding the synchronization as described above, the demodulation circuit 9 can perform accurate data demodulation as follows.

As shown in FIG. 9, the positional relationship between the correlation pulse (e) and the sampling pulses S ₁ and S ₂ is always maintained.

The sampling pulse and window pulse generator 6 is
As shown in FIG. 9, a window pulse (L) having a width equal to the interval from the rising edge of the sampling pulse S _{1 to} the falling edge of the sampling pulse S ₂ is generated and output to the circuit 9. The circuit 9 extracts the correlation pulse (e) by the window pulse (le) and performs accurate data demodulation.

[Effects of the Invention] As described above, according to the present invention, there is an advantage that a normal synchronization holding operation can be performed even when a code clock frequency error is significant.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the binarization circuit in the above embodiment, and FIG. 3 is a timing chart for explaining the synchronization holding operation in the above embodiment. 4, 5 and 6 are block diagrams showing an example of the configuration of the first matched filter in the above embodiment, and FIGS. 7 and 8 are configurations of the second matched filter in the above embodiment. FIG. 9 is a block diagram showing an example, FIG. 9 is a waveform diagram for explaining the synchronization holding operation and demodulation of the above embodiment, FIG. 10 is a configuration diagram of transmission data and preamble data, and FIG. 11 is a configuration example of a comparison circuit. FIG. 12 and FIG. 12 are diagrams showing that the correct arrangement of the received PN code and the reference PN code is required. 1 ... Correlator, 2 ... Binarization circuit, 3 ... First matched filter, 4 ... Up-down counter, 5 ... Reference PN code generator, 6 ... Sampling pulse and window pulse generator, 7: Digital phase lock loop circuit,
8 ... PN code phase control pulse generation circuit, 9 ... Demodulation circuit, 10 ... Second matched filter, 41 ... Comparison circuit, 42 ...
… External circuit.

Claims (1)

[Claims] 1. A correlation pulse generated by a correlation spike output from the correlator, the correlator having a correlation between a reception pseudo-noise code included in a reception signal and a reference pseudo-noise code generated on the reception side. Sampling pulses are generated at timings before and after chronologically, the shift signal indicating the shift direction and the shift amount thereof is detected based on the correlation pulse and the sampling pulse, and the phase control pulse corresponding to the shift signal detects the shift signal. In a spread spectrum receiver having phase control means for controlling the phase of the reference pseudo-noise code, and maintaining the synchronization of both codes, a counting means for counting the number of times the shift signal is output, and the phase based on the counting means. And a phase control amount changing means of the pseudo noise code for the phase control pulse of the control means. Receiver.