JPH02226826A - Spread spectrum receiver - Google Patents

Abstract

PURPOSE:To perform a normal synchronism holding operation even when an error in code clock frequency is remarkable by counting how many times the direction and quantity of deviation of a correlation pulse are detected and varying the quantity of phase control over a phase control pulse when the difference in the counted value reaches a specific value. CONSTITUTION:This receiver is provided with a correlator 1, a binarization coding circuit 2, a 1st matching filter 3, an up/down counter 4, a reference artificial noise (reference PN) code generator 5, a sampling pulse and wind pulse generator 6, a digital phase-locked loop circuit 7, a PN code phase control pulse generating circuit 8, a demodulating circuit 9, a 2nd matching filter 10, a comparator 41, and an external circuit 42. Then the number of times of the detection of the direction and quantity of deviation of the correlation pulse is counted and when the difference in the counted value reaches the specific value, the quantity of phase control over the phase control pulse is varied. Consequently, even when the error in the code clock frequency between both received PN and reference PN codes is remarkable, the normal synchronism holding operation is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a receiver used in spread spectrum communication (hereinafter abbreviated as SSC in this specification).

[Summary of the Invention] A correlator for correlating a received pseudo-noise (hereinafter abbreviated as PN) code included in a received signal with a base IPN code generated on the receiving side, the correlator A sampling pulse is generated temporally before and after the correlation pulse generated from the correlation spike output from the , the correlation pulse is sampled, the direction and amount of deviation are detected, and the corresponding phase control pulse is generated. In the SSc receiver which maintains the synchronization of both codes by controlling the phase of the reference PN code, the SSc receiver includes means for counting the number of detections of the direction and amount of deviation, and a means for counting the number of times the deviation direction and deviation amount are detected, and the difference between the counted values reaches a predetermined value. and means for changing the phase control amount of the phase control pulse when the phase control pulse reaches the phase control pulse.

[Prior Art] As a conventional method, there is Japanese Patent Application No. 1983-283056 filed by the applicant on November 11, 1988.

The above method includes a correlator that takes the correlation between the received PN code included in the received signal and the reference PN code generated on the receiving side, and the correlation pulse generated from the correlation spike output from the correlator is A sampling pulse is generated before and after the correlation pulse is sampled to detect the direction and amount of deviation, and the phase of the reference PN code is controlled by the corresponding phase control pulse to synchronize both codes. Perform a holding operation.

[Problems to be Solved by the Invention] However, if the difference between the code clock frequencies of both codes is significant, the phase control amount of the phase control pulse corresponding to the detection of the deviation direction and deviation amount by both the sampling pulses becomes inappropriate. There is a problem that normal synchronization maintenance operation is not performed.

[Object of the Invention] An object of the present invention is to provide an SSC receiver that can perform a normal synchronization maintenance operation even when there is a significant difference between the code clock frequencies of both codes.

[Means for Solving the Problems] In order to achieve the above object, the present invention includes a correlator that correlates the received PN code included in the received signal with the reference PN code generated on the receiving side. Sampling pulses are generated at timings before and after the correlation pulse generated from the correlation spike output from the correlator, and a deviation signal indicating the direction and amount of deviation between them is generated based on the correlation pulse and the sampling pulse. The reference PN is detected by the phase control pulse corresponding to this deviation signal.
The spread spectrum receiver includes a phase control means for controlling the phase of the code and maintains the synchronization of both codes, and includes a counting means for counting the number of outputs of the shifted signal, and a counting means for counting the number of outputs of the shifted signal, and a count means for counting the number of times the phase control means is output based on the counting means. The gist of the present invention is to include a means for changing the phase control amount of the PN code for the phase control pulse.

[Operation] The number of detections of the direction and amount of deviation of the correlation pulse is counted, and when the difference between the counted values reaches a predetermined value, the phase control amount of the phase control pulse is changed.

[Examples] The present invention will be explained in more detail below using Examples with reference to the drawings, but these are merely illustrative and various modifications and improvements can be made without going beyond the scope of the present invention. Of course it is possible.

FIG. 1 shows an embodiment of the SSC receiver according to the present invention.
is a correlator, 2 is a binarization circuit, 3 is a first matched filter, 4 is an up/down counter, 5 is a reference PN code generator, 6 is a sampling pulse and wind pulse generator, 7 is a digital phase lock loop circuit □Route, 8
is a PN code phase control pulse generation circuit, 9 is a demodulation circuit, 10 is a second matched filter, 41 is a comparison circuit, 42
is an external circuit.

In FIG. 1, the binarization circuit 2 converts the correlation spike (d) that appears when the received PN code and the reference PN code (h) match in the correlator 1 and in the vicinity thereof to the positive and negative sides of the polarity. Generate separated correlated pulses (e). The first matched filter 3 generates a pulse (E) (initial synchronization detection signal) when the pattern of the correlation pulse (E) output from the binarization circuit 2 matches a predetermined judgment pattern.
Output.

Up/down counter 4 is reference PN code generator 5
It is initialized by the strobe pulse (S) output from the first matched filter 3 and up-counts from the offset value (A) set from an external circuit such as a microprocessor, but the pulse (H) is output from the first matched filter 3. When this occurs, it is triggered to perform a down count and generate a borrow pulse (g).

The reference PN code generator 5 receives the reference i! set from the external circuit 42. l! Standard P based on the initial information (c) of the PN code
Outputs an N code (ch) and a strobe pulse (su) indicating its first bit.

The sampling and wind pulse generator 6 samples the correlation pulse (e) output from the binarization circuit 2 and outputs a sampling pulse (nu) and a wind pulse (ru) for sampling and extraction. The digital phase-locked loop circuit 7 maintains synchronization between the received PN code contained in the received signal (b) input to the correlator 1 and the reference PN code (h) contained in the reference signal.

The PN code phase control pulse generation circuit 8 is triggered by the pulses (g) and (wo) output from the up/down counter 4 and the digital phase lock loop 7, and generates the phase control pulse (y) of the reference PN code (ch). Output. The demodulation circuit 9 is a second matched filter 10 that demodulates binary data using the correlation pulse (e) output from the binarization circuit 2 and the wind pulse (ru) output from the sampling and wind pulse generator 6. is the binary data output from the demodulation circuit 9 (
A pulse (shi) is output when the ri) matches a predetermined pattern.

Note that each of the above circuits is triggered by a reception operation starting pulse outputted from the external circuit 42 to start its respective operation.

Next, the operation of the embodiment of the present invention described above will be explained in more detail, but in order to make the explanation easier, it is assumed that one period of the PN code and the length of the data bit are equal, and the correlation W! Let us take as an example the case where the integral interval by 1 is equal to one period of the PN code.

When the reception operation activation pulse is output from the external circuit 42, the reference PN code generator 65 generates the base*PN code (C) included in the reference signal based on the initial information (C) of the PN code set by the external circuit 42. is given to correlator 1.

When the ssc signal is received and the received PN code included in the received signal (b) matches the reference PN code (h), the correlation I
A correlation spike (d) is output from ll to the binarization circuit 2. As shown in FIG. 2, the binarization circuit 2 separates the correlation spike (d) into the positive side and the negative side, generates the correlation pulse (e), and connects the first matched filter 3, digital phase lock loop 7 and It is given to the demodulation circuit 9.

Now, as mentioned above, in correlator 1, both PNs
It is unknown at what position the codes match, and if the matching position of the same code is not set correctly, the received data cannot be demodulated correctly. It is necessary to perform initial synchronization, and in the present invention, this initial synchronization is performed as follows.

The transmitted data is composed of preamble data and information data as shown in FIG. 10(a).

The transmitted data includes a predetermined pattern for initial synchronization (initial synchronization pattern) as shown in FIG. ) is input to the first matched filter 3 . When the pattern of the correlation pulse (e) matches a predetermined pattern, the first matched filter 3
Pulse (to) ti-output to up/down counter 4.

The up/down counter 4 is connected to the first up/down counter 4 as shown in FIG.
It is initialized by the strobe pulse (su) indicating the first bit of the reference PN code (chi) output from the reference PN code generator 5 until the pulse (to) is output from the matched filter 3 of the external circuit 42. When a pulse (to) is output from the first matched filter 3 that repeatedly counts up from the set offset value (a),
The up/down counter 4 switches from up counting to down counting 1- at the timing of the pulse, and when the count value of the counter 4 reaches 0, outputs a borrow pulse (g) to the PN code phase control pulse generation circuit 8.

The PN code phase control pulse generation circuit 8 is triggered by the borrow pulse (g), and based on the phase control pulse (y) of the reference PN code (h), generates the igPN code generator S, the sampling pulse and wind pulse generator 6, and the digital phase. Output to lock loop circuit.

Through the above-described series of operations, the received PN code and the reference PN code (chi) come to match.

4, 5 and 6 show the first matched filter 3
- An example of the configuration is shown below.

In FIG. 4, 11 is a shift register, 12 is a pulse counter, and 13 is a comparator.

As shown in FIG. 5, the shift register 11 has a plurality of shift registers SR, ~SR'a connected in series, each driven by a code clock, and an output terminal set for each fixed length. and their respective outputs are given to a pulse counter 12.

The pulse counter 12 counts the total number of pulses output in parallel from each shift register, converts the count into binary data, and outputs it to the comparator 13. This pulse counter 12 consists of a plurality of half adders 14 and full adders 15, for example, as shown in FIG.

The parallel outputs of the shift registers are input into each half adder 14 as a set of two, and half addition is performed. The resulting addition output ρ is approximately 2°, and the carry output is
It is converted into binary data by assigning it to the 21st position.

Further, each of the converted binary data is input to a full adder 15 and added. In this way shift register 1
The total number of pulses output in parallel from 1 is converted into binary data.

Comparator 13 outputs 2 from pulse counter 12
Compare the binary data with the threshold set by the external circuit, and
Outputs a pulse when the forward data reaches the threshold.

In the first matched filter 3 having the above-described configuration, for example, when the transmitted data pattern for initial synchronization is all "1", a correlation spike occurs. In other words, the correlation spike on the positive side takes 1/1 of the time (hereinafter referred to as delay time) corresponding to the integration interval of correlator 1 (hereinafter referred to as delay time).
2, and no negative correlation spikes occur. Therefore, the binarization circuit 2 generates positive correlation spikes with the same period as the correlation spikes, but does not generate negative correlation spikes.

This correlation spike is input to the shift register 11, which has output terminals set every 1/2 of the delay time T, as shown in FIG. Therefore, if the signal is being received normally, the pulses will be outputted in parallel from the shift register 11 while increasing every 1/2 of the delay time T, and converted into binary data by the pulse counter 12 as described above. The comparator 13 outputs a pulse when the converted signal reaches a threshold value set by the external circuit 42 to the comparator 13 .

According to the above-described configuration of the first matched filter 3, even if an abnormality occurs in the output of the correlator 1 due to noise or the like, it is possible to match only normal correlation pulses.

Note that the intervals between the output terminals set in the plurality of shift registers SR, SR, constituting the shift register 11 are modified in accordance with the pattern of data for initial synchronization that is transmitted.

FIGS. 7 and 8 show examples of the configuration of the second matched filter 1°. In FIG. 7, 21 is a shift register, 22 is a pulse counter, and 23 is a comparator.

The shift register 21 is as shown in FIG.

It consists of a plurality of shift registers SR,' to SR,' connected in series and driven by a clock having a period equal to the length of one data bit, and each shift register is provided with an output terminal.

Demodulated data is input to the shift register 21, and when the demodulated data matches the pattern set to detect the start timing of information data included in the preamble data, as shown in FIG. 10(b), ,
An inverter INV is connected to the output of each shift register as appropriate so that pulses are output from all shift registers SRz'-SR,'.
The output of each shift register is output to a pulse counter 22.

The pulse counter 22 and the comparator 23 are constructed in the same manner as described above, and the pulse counter 22 counts the total number of pulses output from the shift register 21 and calculates 2.
Convert to decimal data.

Output to comparator 23. The comparator 23 compares this binary data with a threshold value set from an external circuit 42, and outputs a pulse when the binary data reaches the threshold value.

Now, initial synchronization is established as described above, and a predetermined arrangement relationship between the two codes is established.

However, if there is an error in the code clock frequency between the two codes, the position where the same codes match will gradually shift from the above arrangement relationship.In other words, even if initial synchronization is achieved, the code clock frequency between the two codes will gradually shift. If they are different, the positions with the same signs will gradually deviate from the normal positions.

Therefore, in the present invention, the following measures are taken to correct the above-mentioned deviation, that is, phase error, and maintain synchronization.

The sampling pulse and wind pulse generator 6 and the digital phase lock loop circuit 7 are initialized by the phase control pulse (Y) of the reference PN code (J) outputted from the PN code phase control pulse generation circuit 8.

As shown in FIG. 9, the circuit 6 generates sampling pulses S, . The circuit 7 constantly samples the correlation pulse (e) using the sampling pulse Sl+32 and monitors the direction of deviation of the correlation pulse.

The circuit 7 is operated every time sampling is performed.

The internal counter counts the number of times, and if there is a difference in the number of samplings by both sampling pulses,
When this difference reaches a predetermined value, a pulse (w) indicating the amount of advance or delay deviation is output to the circuit 8.

The circuit 8 is I-triggered by the above-mentioned pulse (w), and supplies the phase control pulse of the reference PN code (h) corresponding to the detected amount of deviation of the correlation pulse by both sampling pulses to the reference PN code generator 5 to change its phase. Control. As a result, the phase error between both codes is corrected, and synchronization can be maintained.

However, if the error in the code clock frequency between the two codes is significant, the phase control amount of the phase control pulse of the reference PN code (H) corresponding to the amount of deviation detected by the two sampling pulses exceeds the limit, and normal synchronization is maintained. There is a possibility that the operation will not be possible.

The synchronization holding operation in the above case will be explained below based on the temporally normal positional relationship (A in Fig. 3) between the correlation pulse (E) and the sampling pulse (N).

An explanation will be given by taking as an example the positional relationship (B in FIG. 3) in which the correlation pulse (E) is shifted forward in time with respect to the sampling pulse (N).

Comparison circuit 41 is digital phase-locked loop circuit 7
A pulse indicating the amount of lead and lag deviation output from (
The number of outputs of wo) is counted, and when the number of outputs increases in the advancing direction and the count value reaches the threshold value set from the external circuit 42, an advancing direction detection pulse (so) is output as a deviation direction detection pulse.
is output to the external circuit 42. The external circuit 42 changes the phase control amount (T) of the phase control pulse (Y) corresponding to the leading tendency detection pulse (S) outputted from the comparator circuit 41 from the initially set 1 chip to 2 chips.

That is, the phase amount controlled by the phase control pulse (Y) of the reference PN code changes from 1 chip to 2 chips, as shown in C and D in FIG.

In this way, by detecting the tendency of the lead or lag of the correlation pulse (e) with respect to the sampling pulse (e), the phase control amount of the reference PN code is changed to stably maintain synchronization.

FIG. 11 shows an example of the configuration of the comparison circuit 41.

In FIG. 11, 31 and 32 are counters, 33
and 34 are comparators. The counters 31 and 32 receive pulses (w) indicating the lead and lag deviation amounts output from the digital phase lock loop circuit 7. Then, the count values from the counters 31 and 32 are outputted to the comparators 33 and 34. When the count values output from the counters 31 and 32 reach a threshold set by the external circuit 42, the comparators 33 and 34 output lead and lag trend detection pulses as deviation direction detection pulses to the external circuit 42.

By performing the initial synchronization of the received PN code and the reference PN code in the correlator 1 and maintaining the synchronization as described above, accurate data demodulation can be performed by the demodulation circuit 9 as described below.

As shown in FIG. 9, the positional relationship between the correlation pulse (e) and the sampling pulses S, , S2 is always maintained.

The sampling pulse and wind pulse generator 6 generates a wind pulse having a width equal to the interval from the rising edge of the sampling pulse S1 to the falling edge of the sampling pulse S2, as shown in FIG.
is generated and output to the circuit 9 described above. The circuit 9 extracts a correlation pulse (E) using a wind pulse (R) and performs accurate data demodulation.

[Effects of the Invention] As explained above, according to the present invention, there is an advantage that a normal synchronization holding operation can be performed even when the error in the code clock frequency is significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the binarization circuit in the above embodiment, FIG. 3 is a timing chart for explaining the initial synchronization operation of the above embodiment, FIG. 4, FIG. 5, and FIG. 6 are block diagrams showing an example of the configuration of the first matched filter in the above embodiment, and FIGS. 7 and 8 are block diagrams showing an example of the configuration of the second matched filter in the above embodiment. A block diagram showing an example, FIG. 9 is a waveform diagram for explaining the synchronization holding operation and demodulation of the above embodiment, FIG. 10 is a configuration diagram of transmission data and preamble data, and FIG. 11 is a configuration example of a comparison circuit. FIG. 1 ・・・・・・・・・ Correlator, 2 ・・・・・・・・・
Binarization circuit, 3...First matched filter, 4...Up/down counter, 5
......Reference PN code generator, 6...
. . . Sampling pulse and wind pulse generator, 7 . . . Digital phase lock loop circuit, 8 . . . PN code phase control pulse generation circuit, 9 . ...Demodulation circuit, 10...
...Second matched filter, 41...
...Comparison circuit, 42...External circuit. Figure 2 Patent applicant Clarion Co., Ltd.

Claims (1)

[Scope of Claims] A correlator that takes a correlation between a received pseudo-noise code included in a received signal and a reference pseudo-noise code generated on the receiving side, and a correlation generated from a correlation spike output from the correlator. A sampling pulse is generated before and after the pulse, a deviation signal indicating the direction and amount of deviation between them is detected based on the correlation pulse and the sampling pulse, and a phase control pulse corresponding to this deviation signal is used to generate a sampling pulse. A spread spectrum receiver comprising a phase control means for controlling the phase of the reference pseudo-noise code and maintaining synchronization of both codes, a counting means for counting the number of outputs of the deviation signal, and a counting means for counting the number of outputs of the deviation signal; A spread spectrum receiver comprising: means for changing the phase control amount of a pseudo noise code for the phase control pulse of the phase control means.