JPH073836B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit having a programmable chip function.

[Technical background of the invention and its problems]

In recent years, the following LSIs have emerged in response to the demand for a large number of small quantities.

(1) Standard cell method The circuit block having the basic logic function used in the LSI is registered in the computer in advance, and these circuit blocks are arranged and wired by the automatic processing of the computer to obtain the desired final product. To get

(2) Gate array method The basic circuits that make up the logic gates are arranged in an array on the wafer in advance, and the wiring pattern is determined on this by automatic wiring as in the standard cell method.
To get

Although these have a shorter development period than fully hand-designed LSIs, they require a manufacturing process using lithographic techniques.
There is a problem that it takes several weeks to several months from the completion of design to the completion of LSI.

On the other hand, the following method has been proposed by the applicant (Japanese Patent Application No. 58-157718).

That is, as shown in FIG. 3, a plurality of circuits blocks 31a constituted by one or more logical functional element, 31b ...... 31 _N is completed the wiring process by techniques previously dedicated IC built in the substrate, The input and output signals of each circuit block are electrically
It is guided to a switch matrix in which ON / OFF states can be written, and can be connected to all input signals of each circuit block through a switch element 32 such as an E ² PROM or a MOSFET having a 1-bit memory. 33 is a T-shaped signal output wiring,
Reference numeral 34 is a signal input wiring.

According to this method, since it is field programmable, the user can obtain a desired LSI having high functions remarkably quickly by writing the logic function by himself. Moreover, it is possible to design an LSI in the form of connecting the input signal and the output signal of the circuit block having a certain fixed logic function, and even a designer who is familiar with the logic design on the board can understand it. easy.

However, the switch
If the ON / OFF state is specified, many terminals for writing are required in addition to the terminals required for the original operation. In a typical example, the number of switches is 1,280,000 per chip, which requires 21 address signals and 1 write signal for a total of 22 switches. For example, the chip area becomes large and the package becomes large and expensive. There was a problem.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object thereof is to reduce the number of signal input terminals in a programmable LSI.

[Outline of Invention]

That is, the essence of the present invention is that the memory elements, which are provided in the switches in the programmable LSI and control ON and OFF, are connected to each other so that writing can be performed by the shift register operation.

〔The invention's effect〕

According to the present invention, the signal terminal required for writing ON / OFF of the switch matrix is, for example, one shift data,
A total of two shift clocks are required, which is a significant reduction. Also, a decoder circuit is not necessary. As a result, the size of the chip and the size of the package can be reduced.

Example of Invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First,
The layout will be described with reference to FIG. That, Si wafer side to the circuit block 31a, which is built is 31b ...... 31 _N, each circuit block is 4 Inputsuto NAND gates, etc., and is composed of one or more logical functional element. This logic function element has a CMOS structure and is a dedicated IC, that is, a handwritten standard cell in a standard cell system or a pre-wired gate array.

The structure of the circuit block is as follows.

Block with 2 4-imped NAND gates …… 15 blocks with 4 2-imped NAND gates …… 14 block with 1 8-imput NAND gates ………… 1
Block with 4 inverters ...... 100 block with 8 bit register …… 19 block with 2 D type flip flops ……
Block with 19 four 4-imped AND gates ... 17
Block with four 2-to-1 data selectors ... 13 Block with two 4-bit binary counters ... 11
Blocks with two 2-4 line decoders …… 7 blocks with 3-8 line decoders …… 3 blocks with two 4-1 selectors …… 5 blocks with 8-1 selectors …… 4 Blocks with 8 bit serial input-parallel output shift register ...... 3 blocks Blocks with 8 bit parallel input-serial output shift register ...... 3 blocks with 8 bit serial input-serial output shift register ...... 2 single A block with two stable multi-pibrator ...
Block with four 2-imped OR gates ... 4 Block with four 2-impact NOR gates ... 3
Blocks with two AND-OR inverters… 3 blocks 64 bits RAM block… 3 blocks 2 Implant EXCLUSIVE-OR gates with 4 blocks… 2 blocks 4 bit comparator block… 3 blocks JK flip-flop Block with two ... 4
9-bit even / odd parity generator / checkered block ... 3 4-bit binary full adder block ... 2 2 2-imput multiplexer 4 blocks ...
Block with 5 SR-Ratches 2 Blocks with ALU ...... 1 Block with 8 bit addressable latches ...... 1 Block with a helicopter generator ...
A circuit block consisting of one, that is, 274 MSIs is provided so that it can be used for various purposes. The average number of inputs and the number of outputs of each circuit block are eight. The input section and the output section of the logic function element serve as the input section and the output section of the circuit block, and the output section is provided with output buffers (not shown). The output section is connected to the T-shaped signal output wiring 33, and the input section is connected to the signal input wiring 34 intersecting with the T-shaped signal output wiring 33. A switch element 32 is provided at the intersection. Therefore, the wiring between the input and output sections is basically one switch, and the equipotential wiring length associated with one current path is 2.5 on average with the side length of the chip being l, as can be seen from FIG. It is held down by l and the delay due to the time constant is prevented.

FIG. 1 (a) is a schematic plan view of a switch matrix,
(B) is an input waveform diagram. That is, 32 is a MOSFET showing the switch element, and 11a to 11 are 1-bit memory elements, which take in the data of the input terminal I in synchronization with the clock input (CK) and output it to the output Q and the shift output. Each memory element is connected in a cascade, has a shift input section 12 and a shift output section 13, and constitutes a shift register operated by a clock input 14. Reference numerals 15 and 16 are input pads. When the input shown in FIG. 1 (b) is made to this shift register, only the Q outputs of 11g, 11j and 11k of the memory elements are High.
Then, the gate of the corresponding MOSFET switch becomes high potential and it turns on, and the others turn off and the desired connection is made.

FIG. 2 shows another embodiment. The figure shows one intersection of the switch matrix. In this embodiment, the wiring 33 and
The connection of 34 is turned on and off according to the contents of the memory element 23 N
It is programmed by a channel type MOSFET 21 and a P channel type MOSFET 22. The gate inputs of both MOSFETs are connected to the inverted outputs Q24,25 of the memory element.
Memory element 23 constitutes one bit of a shift register operated by shift input 28, shift output 29, and inverting input 211 of shift clocks 210 and 210.

According to the second embodiment, it is possible to provide a shift register circuit suitable for the case where the switch element is CMOS.

[Brief description of drawings]

1 (a) and 1 (b) are a plan view and an input waveform diagram illustrating an embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment, and FIG. 3 is a plan view illustrating a conventional example. . In the figure, 11a, 11b ... 11 ... Memory element 32 ... Switch element 31a, 31b, ... 31 _N ... Circuit block.

Claims (1)

[Claims] 1. A plurality of circuit blocks formed on a substrate and having a logic function itself and having a signal input portion and a signal output portion, and adjacent to the plurality of circuit block regions, the substrate. And a wiring region formed on the circuit block region, the circuit block region is composed of a set of a plurality of types of logic functional element, the wiring region is composed of a signal input wiring group and a signal output wiring group intersecting each other, The signal input wiring group is connected to the signal input section of each circuit block, the signal output wiring group is connected to the signal output section of each circuit block, and these connections are connected to the circuit block. A switch element composed of a MOSFET is provided at each intersection of the signal input wiring group and the signal output wiring group which is performed in the region.
In the semiconductor integrated circuit in which the input / output relationship of signals between each circuit block is determined by controlling the N and OFF states and a desired integrated circuit is constructed, the gate of the MOSFET is connected with a memory element, A semiconductor integrated circuit characterized in that a shift register is configured by connecting these memory elements to each other.